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f904cdbb DB |
1 | /* |
2 | * (C) Copyright 2006-2008 | |
3 | * Texas Instruments. | |
4 | * Richard Woodruff <r-woodruff2@ti.com> | |
5 | * Syed Mohammed Khasim <x0khasim@ti.com> | |
6 | * | |
7 | * Configuration settings for the TI OMAP3530 Beagle board. | |
8 | * | |
1a459660 | 9 | * SPDX-License-Identifier: GPL-2.0+ |
f904cdbb DB |
10 | */ |
11 | ||
12 | #ifndef __CONFIG_H | |
13 | #define __CONFIG_H | |
f904cdbb DB |
14 | |
15 | /* | |
16 | * High Level Configuration Options | |
17 | */ | |
f904cdbb DB |
18 | #define CONFIG_OMAP 1 /* in a TI OMAP core */ |
19 | #define CONFIG_OMAP34XX 1 /* which is a 34XX */ | |
f904cdbb | 20 | #define CONFIG_OMAP3_BEAGLE 1 /* working with BEAGLE */ |
308252ad | 21 | #define CONFIG_OMAP_GPIO |
f904cdbb | 22 | |
cae377b5 VH |
23 | #define CONFIG_SDRC /* The chip has SDRC controller */ |
24 | ||
f904cdbb DB |
25 | #include <asm/arch/cpu.h> /* get chip and board defs */ |
26 | #include <asm/arch/omap3.h> | |
27 | ||
6a6b62e3 SP |
28 | /* |
29 | * Display CPU and Board information | |
30 | */ | |
31 | #define CONFIG_DISPLAY_CPUINFO 1 | |
32 | #define CONFIG_DISPLAY_BOARDINFO 1 | |
33 | ||
f904cdbb DB |
34 | /* Clock Defines */ |
35 | #define V_OSCK 26000000 /* Clock output from T2 */ | |
36 | #define V_SCLK (V_OSCK >> 1) | |
37 | ||
f904cdbb DB |
38 | #define CONFIG_MISC_INIT_R |
39 | ||
03a2075a TR |
40 | #define CONFIG_OF_LIBFDT |
41 | #define CONFIG_CMD_BOOTZ | |
b485556b | 42 | |
f904cdbb DB |
43 | #define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ |
44 | #define CONFIG_SETUP_MEMORY_TAGS 1 | |
45 | #define CONFIG_INITRD_TAG 1 | |
46 | #define CONFIG_REVISION_TAG 1 | |
47 | ||
48 | /* | |
49 | * Size of malloc() pool | |
50 | */ | |
9c44ddcc | 51 | #define CONFIG_ENV_SIZE (128 << 10) /* 128 KiB */ |
f904cdbb | 52 | /* Sector */ |
9c44ddcc | 53 | #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (128 << 10)) |
f904cdbb DB |
54 | |
55 | /* | |
56 | * Hardware drivers | |
57 | */ | |
58 | ||
59 | /* | |
60 | * NS16550 Configuration | |
61 | */ | |
62 | #define V_NS16550_CLK 48000000 /* 48MHz (APLL96/2) */ | |
63 | ||
64 | #define CONFIG_SYS_NS16550 | |
65 | #define CONFIG_SYS_NS16550_SERIAL | |
66 | #define CONFIG_SYS_NS16550_REG_SIZE (-4) | |
67 | #define CONFIG_SYS_NS16550_CLK V_NS16550_CLK | |
68 | ||
69 | /* | |
70 | * select serial console configuration | |
71 | */ | |
72 | #define CONFIG_CONS_INDEX 3 | |
73 | #define CONFIG_SYS_NS16550_COM3 OMAP34XX_UART3 | |
74 | #define CONFIG_SERIAL3 3 /* UART3 on Beagle Rev 2 */ | |
75 | ||
76 | /* allow to overwrite serial and ethaddr */ | |
77 | #define CONFIG_ENV_OVERWRITE | |
78 | #define CONFIG_BAUDRATE 115200 | |
79 | #define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600,\ | |
80 | 115200} | |
0cd31144 | 81 | #define CONFIG_GENERIC_MMC 1 |
f904cdbb | 82 | #define CONFIG_MMC 1 |
0cd31144 | 83 | #define CONFIG_OMAP_HSMMC 1 |
f904cdbb DB |
84 | #define CONFIG_DOS_PARTITION 1 |
85 | ||
70d8c944 JK |
86 | /* Status LED */ |
87 | #define CONFIG_STATUS_LED 1 | |
88 | #define CONFIG_BOARD_SPECIFIC_LED 1 | |
89 | #define STATUS_LED_BIT 0x01 | |
90 | #define STATUS_LED_STATE STATUS_LED_ON | |
91 | #define STATUS_LED_PERIOD (CONFIG_SYS_HZ / 2) | |
92 | #define STATUS_LED_BIT1 0x02 | |
93 | #define STATUS_LED_STATE1 STATUS_LED_ON | |
94 | #define STATUS_LED_PERIOD1 (CONFIG_SYS_HZ / 2) | |
95 | #define STATUS_LED_BOOT STATUS_LED_BIT | |
96 | #define STATUS_LED_GREEN STATUS_LED_BIT1 | |
97 | ||
f74fc4ae JK |
98 | /* Enable Multi Bus support for I2C */ |
99 | #define CONFIG_I2C_MULTI_BUS 1 | |
100 | ||
101 | /* Probe all devices */ | |
8c4e0ca6 | 102 | #define CONFIG_SYS_I2C_NOPROBES {{0x0, 0x0}} |
f74fc4ae | 103 | |
25374bfb | 104 | /* USB */ |
c2af345e IY |
105 | #define CONFIG_MUSB_GADGET |
106 | #define CONFIG_USB_MUSB_OMAP2PLUS | |
107 | #define CONFIG_MUSB_PIO_ONLY | |
108 | #define CONFIG_USB_GADGET_DUALSPEED | |
25374bfb | 109 | #define CONFIG_TWL4030_USB 1 |
c642b151 IY |
110 | #define CONFIG_USB_ETHER |
111 | #define CONFIG_USB_ETHER_RNDIS | |
25374bfb | 112 | |
d90859a6 AH |
113 | /* USB EHCI */ |
114 | #define CONFIG_CMD_USB | |
115 | #define CONFIG_USB_EHCI | |
928c4bdf | 116 | |
29321c05 | 117 | #define CONFIG_USB_EHCI_OMAP |
29321c05 IY |
118 | #define CONFIG_OMAP_EHCI_PHY1_RESET_GPIO 147 |
119 | ||
928c4bdf G |
120 | #define CONFIG_USB_ULPI |
121 | #define CONFIG_USB_ULPI_VIEWPORT_OMAP | |
122 | ||
d90859a6 | 123 | #define CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS 3 |
2162439a KK |
124 | #define CONFIG_USB_HOST_ETHER |
125 | #define CONFIG_USB_ETHER_SMSC95XX | |
54b62d59 | 126 | #define CONFIG_USB_ETHER_ASIX |
2162439a | 127 | |
d90859a6 | 128 | |
f904cdbb DB |
129 | /* commands to include */ |
130 | #include <config_cmd_default.h> | |
131 | ||
776bebb7 TR |
132 | #define CONFIG_CMD_ASKENV |
133 | ||
95c6f6d3 | 134 | #define CONFIG_CMD_CACHE |
f904cdbb DB |
135 | #define CONFIG_CMD_EXT2 /* EXT2 Support */ |
136 | #define CONFIG_CMD_FAT /* FAT support */ | |
917cfc70 | 137 | #define CONFIG_CMD_MTDPARTS /* Enable MTD parts commands */ |
942556a9 | 138 | #define CONFIG_MTD_DEVICE /* needed for mtdparts commands */ |
917cfc70 NM |
139 | #define MTDIDS_DEFAULT "nand0=nand" |
140 | #define MTDPARTS_DEFAULT "mtdparts=nand:512k(x-loader),"\ | |
141 | "1920k(u-boot),128k(u-boot-env),"\ | |
142 | "4m(kernel),-(fs)" | |
f904cdbb DB |
143 | |
144 | #define CONFIG_CMD_I2C /* I2C serial bus support */ | |
145 | #define CONFIG_CMD_MMC /* MMC support */ | |
d90859a6 | 146 | #define CONFIG_USB_STORAGE /* USB storage support */ |
f904cdbb | 147 | #define CONFIG_CMD_NAND /* NAND support */ |
70d8c944 | 148 | #define CONFIG_CMD_LED /* LED support */ |
2162439a KK |
149 | #define CONFIG_CMD_NET /* bootp, tftpboot, rarpboot */ |
150 | #define CONFIG_CMD_NFS /* NFS support */ | |
151 | #define CONFIG_CMD_PING | |
54b62d59 | 152 | #define CONFIG_CMD_DHCP |
933d3701 | 153 | #define CONFIG_CMD_SETEXPR /* Evaluate expressions */ |
aae58b95 | 154 | #define CONFIG_CMD_GPIO /* Enable gpio command */ |
f904cdbb DB |
155 | |
156 | #undef CONFIG_CMD_FLASH /* flinfo, erase, protect */ | |
157 | #undef CONFIG_CMD_FPGA /* FPGA configuration Support */ | |
158 | #undef CONFIG_CMD_IMI /* iminfo */ | |
159 | #undef CONFIG_CMD_IMLS /* List all found images */ | |
f904cdbb DB |
160 | |
161 | #define CONFIG_SYS_NO_FLASH | |
0297ec7e | 162 | #define CONFIG_HARD_I2C 1 |
f904cdbb DB |
163 | #define CONFIG_SYS_I2C_SPEED 100000 |
164 | #define CONFIG_SYS_I2C_SLAVE 1 | |
ca5f80ae | 165 | #define CONFIG_I2C_MULTI_BUS 1 |
f904cdbb | 166 | #define CONFIG_DRIVER_OMAP34XX_I2C 1 |
25a4d017 | 167 | #define CONFIG_VIDEO_OMAP3 /* DSS Support */ |
f904cdbb | 168 | |
2c155130 TR |
169 | /* |
170 | * TWL4030 | |
171 | */ | |
172 | #define CONFIG_TWL4030_POWER 1 | |
173 | #define CONFIG_TWL4030_LED 1 | |
174 | ||
f904cdbb DB |
175 | /* |
176 | * Board NAND Info. | |
177 | */ | |
60c23173 | 178 | #define CONFIG_SYS_NAND_QUIET_TEST 1 |
f904cdbb DB |
179 | #define CONFIG_NAND_OMAP_GPMC |
180 | #define CONFIG_SYS_NAND_ADDR NAND_BASE /* physical address */ | |
181 | /* to access nand */ | |
182 | #define CONFIG_SYS_NAND_BASE NAND_BASE /* physical address */ | |
183 | /* to access nand at */ | |
184 | /* CS0 */ | |
185 | #define GPMC_NAND_ECC_LP_x16_LAYOUT 1 | |
186 | ||
187 | #define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND */ | |
188 | /* devices */ | |
f904cdbb DB |
189 | |
190 | /* Environment information */ | |
1dd07fe8 | 191 | #define CONFIG_BOOTDELAY 3 |
f904cdbb DB |
192 | |
193 | #define CONFIG_EXTRA_ENV_SETTINGS \ | |
f4b36ea9 JK |
194 | "loadaddr=0x80200000\0" \ |
195 | "rdaddr=0x81000000\0" \ | |
25374bfb | 196 | "usbtty=cdc_acm\0" \ |
a33e3c79 | 197 | "bootfile=uImage\0" \ |
27b8c8f2 | 198 | "console=ttyO2,115200n8\0" \ |
f6e593bb | 199 | "mpurate=auto\0" \ |
847b83d0 | 200 | "buddy=none\0" \ |
c522eac4 JK |
201 | "optargs=\0" \ |
202 | "camera=none\0" \ | |
13d2cb98 | 203 | "vram=12M\0" \ |
f4b36ea9 | 204 | "dvimode=640x480MR-16@60\0" \ |
13d2cb98 | 205 | "defaultdisplay=dvi\0" \ |
0cd31144 | 206 | "mmcdev=0\0" \ |
13d2cb98 SS |
207 | "mmcroot=/dev/mmcblk0p2 rw\0" \ |
208 | "mmcrootfstype=ext3 rootwait\0" \ | |
3c6e50d7 SS |
209 | "nandroot=ubi0:rootfs ubi.mtd=4\0" \ |
210 | "nandrootfstype=ubifs\0" \ | |
f4b36ea9 JK |
211 | "ramroot=/dev/ram0 rw ramdisk_size=65536 initrd=0x81000000,64M\0" \ |
212 | "ramrootfstype=ext2\0" \ | |
f904cdbb | 213 | "mmcargs=setenv bootargs console=${console} " \ |
c522eac4 | 214 | "${optargs} " \ |
5af32460 | 215 | "mpurate=${mpurate} " \ |
b1660314 | 216 | "buddy=${buddy} "\ |
c522eac4 | 217 | "camera=${camera} "\ |
13d2cb98 SS |
218 | "vram=${vram} " \ |
219 | "omapfb.mode=dvi:${dvimode} " \ | |
13d2cb98 SS |
220 | "omapdss.def_disp=${defaultdisplay} " \ |
221 | "root=${mmcroot} " \ | |
222 | "rootfstype=${mmcrootfstype}\0" \ | |
f904cdbb | 223 | "nandargs=setenv bootargs console=${console} " \ |
c522eac4 | 224 | "${optargs} " \ |
5af32460 | 225 | "mpurate=${mpurate} " \ |
b1660314 | 226 | "buddy=${buddy} "\ |
c522eac4 | 227 | "camera=${camera} "\ |
13d2cb98 SS |
228 | "vram=${vram} " \ |
229 | "omapfb.mode=dvi:${dvimode} " \ | |
13d2cb98 SS |
230 | "omapdss.def_disp=${defaultdisplay} " \ |
231 | "root=${nandroot} " \ | |
232 | "rootfstype=${nandrootfstype}\0" \ | |
f835ea71 JK |
233 | "bootenv=uEnv.txt\0" \ |
234 | "loadbootenv=fatload mmc ${mmcdev} ${loadaddr} ${bootenv}\0" \ | |
cf073e49 AH |
235 | "importbootenv=echo Importing environment from mmc ...; " \ |
236 | "env import -t $loadaddr $filesize\0" \ | |
f4b36ea9 JK |
237 | "ramargs=setenv bootargs console=${console} " \ |
238 | "${optargs} " \ | |
239 | "mpurate=${mpurate} " \ | |
240 | "buddy=${buddy} "\ | |
241 | "vram=${vram} " \ | |
242 | "omapfb.mode=dvi:${dvimode} " \ | |
243 | "omapdss.def_disp=${defaultdisplay} " \ | |
244 | "root=${ramroot} " \ | |
245 | "rootfstype=${ramrootfstype}\0" \ | |
246 | "loadramdisk=fatload mmc ${mmcdev} ${rdaddr} ramdisk.gz\0" \ | |
e5549f0f KK |
247 | "loaduimagefat=fatload mmc ${mmcdev} ${loadaddr} uImage\0" \ |
248 | "loaduimage=ext2load mmc ${mmcdev}:2 ${loadaddr} /boot/uImage\0" \ | |
f904cdbb DB |
249 | "mmcboot=echo Booting from mmc ...; " \ |
250 | "run mmcargs; " \ | |
251 | "bootm ${loadaddr}\0" \ | |
252 | "nandboot=echo Booting from nand ...; " \ | |
253 | "run nandargs; " \ | |
254 | "nand read ${loadaddr} 280000 400000; " \ | |
255 | "bootm ${loadaddr}\0" \ | |
f4b36ea9 JK |
256 | "ramboot=echo Booting from ramdisk ...; " \ |
257 | "run ramargs; " \ | |
258 | "bootm ${loadaddr}\0" \ | |
aae58b95 JF |
259 | "userbutton=if gpio input 173; then run userbutton_xm; " \ |
260 | "else run userbutton_nonxm; fi;\0" \ | |
261 | "userbutton_xm=gpio input 4;\0" \ | |
262 | "userbutton_nonxm=gpio input 7;\0" | |
d7aff44a | 263 | /* "run userbutton" will return 1 (false) if pressed and 0 (true) if not */ |
f904cdbb | 264 | #define CONFIG_BOOTCOMMAND \ |
66968110 | 265 | "mmc dev ${mmcdev}; if mmc rescan; then " \ |
aae58b95 JF |
266 | "if run userbutton; then " \ |
267 | "setenv bootenv uEnv.txt;" \ | |
268 | "else " \ | |
f835ea71 JK |
269 | "setenv bootenv user.txt;" \ |
270 | "fi;" \ | |
cf073e49 AH |
271 | "echo SD/MMC found on device ${mmcdev};" \ |
272 | "if run loadbootenv; then " \ | |
f835ea71 | 273 | "echo Loaded environment from ${bootenv};" \ |
cf073e49 AH |
274 | "run importbootenv;" \ |
275 | "fi;" \ | |
276 | "if test -n $uenvcmd; then " \ | |
277 | "echo Running uenvcmd ...;" \ | |
278 | "run uenvcmd;" \ | |
279 | "fi;" \ | |
280 | "if run loaduimage; then " \ | |
281 | "run mmcboot;" \ | |
282 | "fi;" \ | |
283 | "fi;" \ | |
284 | "run nandboot;" \ | |
f904cdbb DB |
285 | |
286 | #define CONFIG_AUTO_COMPLETE 1 | |
287 | /* | |
288 | * Miscellaneous configurable options | |
289 | */ | |
f904cdbb DB |
290 | #define CONFIG_SYS_LONGHELP /* undef to save memory */ |
291 | #define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */ | |
1270ec13 | 292 | #define CONFIG_SYS_PROMPT "OMAP3 beagleboard.org # " |
f62b1257 | 293 | #define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */ |
f904cdbb DB |
294 | /* Print Buffer Size */ |
295 | #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ | |
296 | sizeof(CONFIG_SYS_PROMPT) + 16) | |
933d3701 | 297 | #define CONFIG_SYS_MAXARGS 32 /* max number of command args */ |
f904cdbb DB |
298 | /* Boot Argument Buffer Size */ |
299 | #define CONFIG_SYS_BARGSIZE (CONFIG_SYS_CBSIZE) | |
300 | ||
780a97f8 JK |
301 | #define CONFIG_SYS_ALT_MEMTEST 1 |
302 | #define CONFIG_SYS_MEMTEST_START (0x82000000) /* memtest */ | |
303 | /* defaults */ | |
304 | #define CONFIG_SYS_MEMTEST_END (0x87FFFFFF) /* 128MB */ | |
305 | #define CONFIG_SYS_MEMTEST_SCRATCH (0x81000000) /* dummy address */ | |
f904cdbb | 306 | |
f904cdbb DB |
307 | #define CONFIG_SYS_LOAD_ADDR (OMAP34XX_SDRC_CS0) /* default */ |
308 | /* load address */ | |
309 | ||
310 | /* | |
d3a513c2 MP |
311 | * OMAP3 has 12 GP timers, they can be driven by the system clock |
312 | * (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK). | |
313 | * This rate is divided by a local divisor. | |
f904cdbb | 314 | */ |
f904cdbb | 315 | #define CONFIG_SYS_TIMERBASE (OMAP34XX_GPT2) |
d3a513c2 MP |
316 | #define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */ |
317 | #define CONFIG_SYS_HZ 1000 | |
f904cdbb | 318 | |
f904cdbb DB |
319 | /*----------------------------------------------------------------------- |
320 | * Physical Memory Map | |
321 | */ | |
322 | #define CONFIG_NR_DRAM_BANKS 2 /* CS1 may or may not be populated */ | |
323 | #define PHYS_SDRAM_1 OMAP34XX_SDRC_CS0 | |
f904cdbb DB |
324 | #define PHYS_SDRAM_2 OMAP34XX_SDRC_CS1 |
325 | ||
f904cdbb DB |
326 | /*----------------------------------------------------------------------- |
327 | * FLASH and environment organization | |
328 | */ | |
329 | ||
330 | /* **** PISMO SUPPORT *** */ | |
331 | ||
332 | /* Configure the PISMO */ | |
333 | #define PISMO1_NAND_SIZE GPMC_SIZE_128M | |
334 | #define PISMO1_ONEN_SIZE GPMC_SIZE_128M | |
335 | ||
9c44ddcc | 336 | #define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 2 sectors */ |
f904cdbb | 337 | |
6cbec7b3 LC |
338 | #if defined(CONFIG_CMD_NAND) |
339 | #define CONFIG_SYS_FLASH_BASE PISMO1_NAND_BASE | |
340 | #endif | |
f904cdbb DB |
341 | |
342 | /* Monitor at start of flash */ | |
343 | #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE | |
344 | #define CONFIG_SYS_ONENAND_BASE ONENAND_MAP | |
345 | ||
346 | #define CONFIG_ENV_IS_IN_NAND 1 | |
347 | #define ONENAND_ENV_OFFSET 0x260000 /* environment starts here */ | |
348 | #define SMNAND_ENV_OFFSET 0x260000 /* environment starts here */ | |
349 | ||
6cbec7b3 LC |
350 | #define CONFIG_SYS_ENV_SECT_SIZE (128 << 10) /* 128 KiB */ |
351 | #define CONFIG_ENV_OFFSET SMNAND_ENV_OFFSET | |
f904cdbb DB |
352 | #define CONFIG_ENV_ADDR SMNAND_ENV_OFFSET |
353 | ||
561142af | 354 | #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 |
31bfcf1c SS |
355 | #define CONFIG_SYS_INIT_RAM_ADDR 0x4020f800 |
356 | #define CONFIG_SYS_INIT_RAM_SIZE 0x800 | |
357 | #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \ | |
358 | CONFIG_SYS_INIT_RAM_SIZE - \ | |
359 | GENERATED_GBL_DATA_SIZE) | |
561142af | 360 | |
53736baa DB |
361 | #define CONFIG_OMAP3_SPI |
362 | ||
8e40852f A |
363 | #define CONFIG_SYS_CACHELINE_SIZE 64 |
364 | ||
75c57a35 TR |
365 | /* Defines for SPL */ |
366 | #define CONFIG_SPL | |
47f7bcae | 367 | #define CONFIG_SPL_FRAMEWORK |
75c57a35 TR |
368 | #define CONFIG_SPL_NAND_SIMPLE |
369 | #define CONFIG_SPL_TEXT_BASE 0x40200800 | |
e0820ccc | 370 | #define CONFIG_SPL_MAX_SIZE (54 * 1024) /* 8 KB for stack */ |
75c57a35 TR |
371 | #define CONFIG_SPL_STACK LOW_LEVEL_SRAM_STACK |
372 | ||
373 | #define CONFIG_SPL_BSS_START_ADDR 0x80000000 | |
374 | #define CONFIG_SPL_BSS_MAX_SIZE 0x80000 /* 512 KB */ | |
375 | ||
376 | #define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x300 /* address 0x60000 */ | |
377 | #define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS 0x200 /* 256 KB */ | |
378 | #define CONFIG_SYS_MMC_SD_FAT_BOOT_PARTITION 1 | |
379 | #define CONFIG_SPL_FAT_LOAD_PAYLOAD_NAME "u-boot.img" | |
380 | ||
49175c49 | 381 | #define CONFIG_SPL_BOARD_INIT |
75c57a35 TR |
382 | #define CONFIG_SPL_LIBCOMMON_SUPPORT |
383 | #define CONFIG_SPL_LIBDISK_SUPPORT | |
384 | #define CONFIG_SPL_I2C_SUPPORT | |
385 | #define CONFIG_SPL_LIBGENERIC_SUPPORT | |
386 | #define CONFIG_SPL_MMC_SUPPORT | |
387 | #define CONFIG_SPL_FAT_SUPPORT | |
388 | #define CONFIG_SPL_SERIAL_SUPPORT | |
389 | #define CONFIG_SPL_NAND_SUPPORT | |
6f2f01b9 SW |
390 | #define CONFIG_SPL_NAND_BASE |
391 | #define CONFIG_SPL_NAND_DRIVERS | |
392 | #define CONFIG_SPL_NAND_ECC | |
16e41c85 | 393 | #define CONFIG_SPL_GPIO_SUPPORT |
75c57a35 TR |
394 | #define CONFIG_SPL_POWER_SUPPORT |
395 | #define CONFIG_SPL_OMAP3_ID_NAND | |
396 | #define CONFIG_SPL_LDSCRIPT "$(CPUDIR)/omap-common/u-boot-spl.lds" | |
397 | ||
398 | /* NAND boot config */ | |
399 | #define CONFIG_SYS_NAND_5_ADDR_CYCLE | |
400 | #define CONFIG_SYS_NAND_PAGE_COUNT 64 | |
401 | #define CONFIG_SYS_NAND_PAGE_SIZE 2048 | |
402 | #define CONFIG_SYS_NAND_OOBSIZE 64 | |
403 | #define CONFIG_SYS_NAND_BLOCK_SIZE (128*1024) | |
404 | #define CONFIG_SYS_NAND_BAD_BLOCK_POS 0 | |
405 | #define CONFIG_SYS_NAND_ECCPOS {2, 3, 4, 5, 6, 7, 8, 9,\ | |
406 | 10, 11, 12, 13} | |
407 | #define CONFIG_SYS_NAND_ECCSIZE 512 | |
408 | #define CONFIG_SYS_NAND_ECCBYTES 3 | |
75c57a35 TR |
409 | #define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE |
410 | #define CONFIG_SYS_NAND_U_BOOT_OFFS 0x80000 | |
411 | ||
412 | /* | |
413 | * 1MB into the SDRAM to allow for SPL's bss at the beginning of SDRAM | |
414 | * 64 bytes before this address should be set aside for u-boot.img's | |
415 | * header. That is 0x800FFFC0--0x80100000 should not be used for any | |
416 | * other needs. | |
417 | */ | |
418 | #define CONFIG_SYS_TEXT_BASE 0x80100000 | |
419 | #define CONFIG_SYS_SPL_MALLOC_START 0x80208000 | |
420 | #define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000 | |
421 | ||
f904cdbb | 422 | #endif /* __CONFIG_H */ |