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f904cdbb DB |
1 | /* |
2 | * (C) Copyright 2006-2008 | |
3 | * Texas Instruments. | |
4 | * Richard Woodruff <r-woodruff2@ti.com> | |
5 | * Syed Mohammed Khasim <x0khasim@ti.com> | |
6 | * | |
7 | * Configuration settings for the TI OMAP3530 Beagle board. | |
8 | * | |
9 | * See file CREDITS for list of people who contributed to this | |
10 | * project. | |
11 | * | |
12 | * This program is free software; you can redistribute it and/or | |
13 | * modify it under the terms of the GNU General Public License as | |
14 | * published by the Free Software Foundation; either version 2 of | |
15 | * the License, or (at your option) any later version. | |
16 | * | |
17 | * This program is distributed in the hope that it will be useful, | |
18 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
19 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
20 | * GNU General Public License for more details. | |
21 | * | |
22 | * You should have received a copy of the GNU General Public License | |
23 | * along with this program; if not, write to the Free Software | |
24 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | |
25 | * MA 02111-1307 USA | |
26 | */ | |
27 | ||
28 | #ifndef __CONFIG_H | |
29 | #define __CONFIG_H | |
f904cdbb DB |
30 | |
31 | /* | |
32 | * High Level Configuration Options | |
33 | */ | |
f904cdbb DB |
34 | #define CONFIG_OMAP 1 /* in a TI OMAP core */ |
35 | #define CONFIG_OMAP34XX 1 /* which is a 34XX */ | |
f904cdbb DB |
36 | #define CONFIG_OMAP3_BEAGLE 1 /* working with BEAGLE */ |
37 | ||
cae377b5 VH |
38 | #define CONFIG_SDRC /* The chip has SDRC controller */ |
39 | ||
f904cdbb DB |
40 | #include <asm/arch/cpu.h> /* get chip and board defs */ |
41 | #include <asm/arch/omap3.h> | |
42 | ||
6a6b62e3 SP |
43 | /* |
44 | * Display CPU and Board information | |
45 | */ | |
46 | #define CONFIG_DISPLAY_CPUINFO 1 | |
47 | #define CONFIG_DISPLAY_BOARDINFO 1 | |
48 | ||
f904cdbb DB |
49 | /* Clock Defines */ |
50 | #define V_OSCK 26000000 /* Clock output from T2 */ | |
51 | #define V_SCLK (V_OSCK >> 1) | |
52 | ||
53 | #undef CONFIG_USE_IRQ /* no support for IRQs */ | |
54 | #define CONFIG_MISC_INIT_R | |
55 | ||
b485556b | 56 | #define CONFIG_OF_LIBFDT 1 |
b485556b | 57 | |
f904cdbb DB |
58 | #define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ |
59 | #define CONFIG_SETUP_MEMORY_TAGS 1 | |
60 | #define CONFIG_INITRD_TAG 1 | |
61 | #define CONFIG_REVISION_TAG 1 | |
62 | ||
63 | /* | |
64 | * Size of malloc() pool | |
65 | */ | |
9c44ddcc | 66 | #define CONFIG_ENV_SIZE (128 << 10) /* 128 KiB */ |
f904cdbb | 67 | /* Sector */ |
9c44ddcc | 68 | #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (128 << 10)) |
f904cdbb DB |
69 | |
70 | /* | |
71 | * Hardware drivers | |
72 | */ | |
73 | ||
74 | /* | |
75 | * NS16550 Configuration | |
76 | */ | |
77 | #define V_NS16550_CLK 48000000 /* 48MHz (APLL96/2) */ | |
78 | ||
79 | #define CONFIG_SYS_NS16550 | |
80 | #define CONFIG_SYS_NS16550_SERIAL | |
81 | #define CONFIG_SYS_NS16550_REG_SIZE (-4) | |
82 | #define CONFIG_SYS_NS16550_CLK V_NS16550_CLK | |
83 | ||
84 | /* | |
85 | * select serial console configuration | |
86 | */ | |
87 | #define CONFIG_CONS_INDEX 3 | |
88 | #define CONFIG_SYS_NS16550_COM3 OMAP34XX_UART3 | |
89 | #define CONFIG_SERIAL3 3 /* UART3 on Beagle Rev 2 */ | |
90 | ||
91 | /* allow to overwrite serial and ethaddr */ | |
92 | #define CONFIG_ENV_OVERWRITE | |
93 | #define CONFIG_BAUDRATE 115200 | |
94 | #define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600,\ | |
95 | 115200} | |
0cd31144 | 96 | #define CONFIG_GENERIC_MMC 1 |
f904cdbb | 97 | #define CONFIG_MMC 1 |
0cd31144 | 98 | #define CONFIG_OMAP_HSMMC 1 |
f904cdbb DB |
99 | #define CONFIG_DOS_PARTITION 1 |
100 | ||
70d8c944 JK |
101 | /* Status LED */ |
102 | #define CONFIG_STATUS_LED 1 | |
103 | #define CONFIG_BOARD_SPECIFIC_LED 1 | |
104 | #define STATUS_LED_BIT 0x01 | |
105 | #define STATUS_LED_STATE STATUS_LED_ON | |
106 | #define STATUS_LED_PERIOD (CONFIG_SYS_HZ / 2) | |
107 | #define STATUS_LED_BIT1 0x02 | |
108 | #define STATUS_LED_STATE1 STATUS_LED_ON | |
109 | #define STATUS_LED_PERIOD1 (CONFIG_SYS_HZ / 2) | |
110 | #define STATUS_LED_BOOT STATUS_LED_BIT | |
111 | #define STATUS_LED_GREEN STATUS_LED_BIT1 | |
112 | ||
f74fc4ae JK |
113 | /* Enable Multi Bus support for I2C */ |
114 | #define CONFIG_I2C_MULTI_BUS 1 | |
115 | ||
116 | /* Probe all devices */ | |
8c4e0ca6 | 117 | #define CONFIG_SYS_I2C_NOPROBES {{0x0, 0x0}} |
f74fc4ae | 118 | |
25374bfb TR |
119 | /* USB */ |
120 | #define CONFIG_MUSB_UDC 1 | |
121 | #define CONFIG_USB_OMAP3 1 | |
122 | #define CONFIG_TWL4030_USB 1 | |
123 | ||
124 | /* USB device configuration */ | |
125 | #define CONFIG_USB_DEVICE 1 | |
126 | #define CONFIG_USB_TTY 1 | |
127 | #define CONFIG_SYS_CONSOLE_IS_IN_ENV 1 | |
25374bfb | 128 | |
d90859a6 AH |
129 | /* USB EHCI */ |
130 | #define CONFIG_CMD_USB | |
131 | #define CONFIG_USB_EHCI | |
928c4bdf | 132 | |
29321c05 IY |
133 | #define CONFIG_USB_EHCI_OMAP |
134 | /*#define CONFIG_EHCI_DCACHE*/ /* leave it disabled for now */ | |
135 | #define CONFIG_OMAP_EHCI_PHY1_RESET_GPIO 147 | |
136 | ||
928c4bdf G |
137 | #define CONFIG_USB_ULPI |
138 | #define CONFIG_USB_ULPI_VIEWPORT_OMAP | |
139 | ||
d90859a6 | 140 | #define CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS 3 |
2162439a KK |
141 | #define CONFIG_USB_HOST_ETHER |
142 | #define CONFIG_USB_ETHER_SMSC95XX | |
54b62d59 | 143 | #define CONFIG_USB_ETHER_ASIX |
2162439a | 144 | |
d90859a6 | 145 | |
f904cdbb DB |
146 | /* commands to include */ |
147 | #include <config_cmd_default.h> | |
148 | ||
95c6f6d3 | 149 | #define CONFIG_CMD_CACHE |
f904cdbb DB |
150 | #define CONFIG_CMD_EXT2 /* EXT2 Support */ |
151 | #define CONFIG_CMD_FAT /* FAT support */ | |
152 | #define CONFIG_CMD_JFFS2 /* JFFS2 Support */ | |
917cfc70 | 153 | #define CONFIG_CMD_MTDPARTS /* Enable MTD parts commands */ |
942556a9 | 154 | #define CONFIG_MTD_DEVICE /* needed for mtdparts commands */ |
917cfc70 NM |
155 | #define MTDIDS_DEFAULT "nand0=nand" |
156 | #define MTDPARTS_DEFAULT "mtdparts=nand:512k(x-loader),"\ | |
157 | "1920k(u-boot),128k(u-boot-env),"\ | |
158 | "4m(kernel),-(fs)" | |
f904cdbb DB |
159 | |
160 | #define CONFIG_CMD_I2C /* I2C serial bus support */ | |
161 | #define CONFIG_CMD_MMC /* MMC support */ | |
d90859a6 | 162 | #define CONFIG_USB_STORAGE /* USB storage support */ |
f904cdbb | 163 | #define CONFIG_CMD_NAND /* NAND support */ |
70d8c944 | 164 | #define CONFIG_CMD_LED /* LED support */ |
2162439a KK |
165 | #define CONFIG_CMD_NET /* bootp, tftpboot, rarpboot */ |
166 | #define CONFIG_CMD_NFS /* NFS support */ | |
167 | #define CONFIG_CMD_PING | |
54b62d59 | 168 | #define CONFIG_CMD_DHCP |
933d3701 | 169 | #define CONFIG_CMD_SETEXPR /* Evaluate expressions */ |
f904cdbb DB |
170 | |
171 | #undef CONFIG_CMD_FLASH /* flinfo, erase, protect */ | |
172 | #undef CONFIG_CMD_FPGA /* FPGA configuration Support */ | |
173 | #undef CONFIG_CMD_IMI /* iminfo */ | |
174 | #undef CONFIG_CMD_IMLS /* List all found images */ | |
f904cdbb DB |
175 | |
176 | #define CONFIG_SYS_NO_FLASH | |
0297ec7e | 177 | #define CONFIG_HARD_I2C 1 |
f904cdbb DB |
178 | #define CONFIG_SYS_I2C_SPEED 100000 |
179 | #define CONFIG_SYS_I2C_SLAVE 1 | |
180 | #define CONFIG_SYS_I2C_BUS 0 | |
181 | #define CONFIG_SYS_I2C_BUS_SELECT 1 | |
ca5f80ae | 182 | #define CONFIG_I2C_MULTI_BUS 1 |
f904cdbb | 183 | #define CONFIG_DRIVER_OMAP34XX_I2C 1 |
25a4d017 | 184 | #define CONFIG_VIDEO_OMAP3 /* DSS Support */ |
f904cdbb | 185 | |
2c155130 TR |
186 | /* |
187 | * TWL4030 | |
188 | */ | |
189 | #define CONFIG_TWL4030_POWER 1 | |
190 | #define CONFIG_TWL4030_LED 1 | |
191 | ||
f904cdbb DB |
192 | /* |
193 | * Board NAND Info. | |
194 | */ | |
60c23173 | 195 | #define CONFIG_SYS_NAND_QUIET_TEST 1 |
f904cdbb DB |
196 | #define CONFIG_NAND_OMAP_GPMC |
197 | #define CONFIG_SYS_NAND_ADDR NAND_BASE /* physical address */ | |
198 | /* to access nand */ | |
199 | #define CONFIG_SYS_NAND_BASE NAND_BASE /* physical address */ | |
200 | /* to access nand at */ | |
201 | /* CS0 */ | |
202 | #define GPMC_NAND_ECC_LP_x16_LAYOUT 1 | |
203 | ||
204 | #define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND */ | |
205 | /* devices */ | |
f904cdbb DB |
206 | #define CONFIG_JFFS2_NAND |
207 | /* nand device jffs2 lives on */ | |
208 | #define CONFIG_JFFS2_DEV "nand0" | |
209 | /* start of jffs2 partition */ | |
210 | #define CONFIG_JFFS2_PART_OFFSET 0x680000 | |
211 | #define CONFIG_JFFS2_PART_SIZE 0xf980000 /* size of jffs2 */ | |
212 | /* partition */ | |
213 | ||
214 | /* Environment information */ | |
4c37e8de | 215 | #define CONFIG_BOOTDELAY 2 |
f904cdbb DB |
216 | |
217 | #define CONFIG_EXTRA_ENV_SETTINGS \ | |
f4b36ea9 JK |
218 | "loadaddr=0x80200000\0" \ |
219 | "rdaddr=0x81000000\0" \ | |
25374bfb | 220 | "usbtty=cdc_acm\0" \ |
e6829308 | 221 | "bootfile=uImage.beagle\0" \ |
27b8c8f2 | 222 | "console=ttyO2,115200n8\0" \ |
f6e593bb | 223 | "mpurate=auto\0" \ |
b1660314 | 224 | "buddy=none "\ |
c522eac4 JK |
225 | "optargs=\0" \ |
226 | "camera=none\0" \ | |
13d2cb98 | 227 | "vram=12M\0" \ |
f4b36ea9 | 228 | "dvimode=640x480MR-16@60\0" \ |
13d2cb98 | 229 | "defaultdisplay=dvi\0" \ |
0cd31144 | 230 | "mmcdev=0\0" \ |
13d2cb98 SS |
231 | "mmcroot=/dev/mmcblk0p2 rw\0" \ |
232 | "mmcrootfstype=ext3 rootwait\0" \ | |
3c6e50d7 SS |
233 | "nandroot=ubi0:rootfs ubi.mtd=4\0" \ |
234 | "nandrootfstype=ubifs\0" \ | |
f4b36ea9 JK |
235 | "ramroot=/dev/ram0 rw ramdisk_size=65536 initrd=0x81000000,64M\0" \ |
236 | "ramrootfstype=ext2\0" \ | |
f904cdbb | 237 | "mmcargs=setenv bootargs console=${console} " \ |
c522eac4 | 238 | "${optargs} " \ |
5af32460 | 239 | "mpurate=${mpurate} " \ |
b1660314 | 240 | "buddy=${buddy} "\ |
c522eac4 | 241 | "camera=${camera} "\ |
13d2cb98 SS |
242 | "vram=${vram} " \ |
243 | "omapfb.mode=dvi:${dvimode} " \ | |
13d2cb98 SS |
244 | "omapdss.def_disp=${defaultdisplay} " \ |
245 | "root=${mmcroot} " \ | |
246 | "rootfstype=${mmcrootfstype}\0" \ | |
f904cdbb | 247 | "nandargs=setenv bootargs console=${console} " \ |
c522eac4 | 248 | "${optargs} " \ |
5af32460 | 249 | "mpurate=${mpurate} " \ |
b1660314 | 250 | "buddy=${buddy} "\ |
c522eac4 | 251 | "camera=${camera} "\ |
13d2cb98 SS |
252 | "vram=${vram} " \ |
253 | "omapfb.mode=dvi:${dvimode} " \ | |
13d2cb98 SS |
254 | "omapdss.def_disp=${defaultdisplay} " \ |
255 | "root=${nandroot} " \ | |
256 | "rootfstype=${nandrootfstype}\0" \ | |
f835ea71 JK |
257 | "bootenv=uEnv.txt\0" \ |
258 | "loadbootenv=fatload mmc ${mmcdev} ${loadaddr} ${bootenv}\0" \ | |
cf073e49 AH |
259 | "importbootenv=echo Importing environment from mmc ...; " \ |
260 | "env import -t $loadaddr $filesize\0" \ | |
f4b36ea9 JK |
261 | "ramargs=setenv bootargs console=${console} " \ |
262 | "${optargs} " \ | |
263 | "mpurate=${mpurate} " \ | |
264 | "buddy=${buddy} "\ | |
265 | "vram=${vram} " \ | |
266 | "omapfb.mode=dvi:${dvimode} " \ | |
267 | "omapdss.def_disp=${defaultdisplay} " \ | |
268 | "root=${ramroot} " \ | |
269 | "rootfstype=${ramrootfstype}\0" \ | |
270 | "loadramdisk=fatload mmc ${mmcdev} ${rdaddr} ramdisk.gz\0" \ | |
e5549f0f KK |
271 | "loaduimagefat=fatload mmc ${mmcdev} ${loadaddr} uImage\0" \ |
272 | "loaduimage=ext2load mmc ${mmcdev}:2 ${loadaddr} /boot/uImage\0" \ | |
f904cdbb DB |
273 | "mmcboot=echo Booting from mmc ...; " \ |
274 | "run mmcargs; " \ | |
275 | "bootm ${loadaddr}\0" \ | |
276 | "nandboot=echo Booting from nand ...; " \ | |
277 | "run nandargs; " \ | |
278 | "nand read ${loadaddr} 280000 400000; " \ | |
279 | "bootm ${loadaddr}\0" \ | |
f4b36ea9 JK |
280 | "ramboot=echo Booting from ramdisk ...; " \ |
281 | "run ramargs; " \ | |
282 | "bootm ${loadaddr}\0" \ | |
f904cdbb DB |
283 | |
284 | #define CONFIG_BOOTCOMMAND \ | |
0cd31144 | 285 | "if mmc rescan ${mmcdev}; then " \ |
f835ea71 JK |
286 | "if userbutton; then " \ |
287 | "setenv bootenv user.txt;" \ | |
288 | "fi;" \ | |
cf073e49 AH |
289 | "echo SD/MMC found on device ${mmcdev};" \ |
290 | "if run loadbootenv; then " \ | |
f835ea71 | 291 | "echo Loaded environment from ${bootenv};" \ |
cf073e49 AH |
292 | "run importbootenv;" \ |
293 | "fi;" \ | |
294 | "if test -n $uenvcmd; then " \ | |
295 | "echo Running uenvcmd ...;" \ | |
296 | "run uenvcmd;" \ | |
297 | "fi;" \ | |
298 | "if run loaduimage; then " \ | |
299 | "run mmcboot;" \ | |
300 | "fi;" \ | |
301 | "fi;" \ | |
302 | "run nandboot;" \ | |
f904cdbb DB |
303 | |
304 | #define CONFIG_AUTO_COMPLETE 1 | |
305 | /* | |
306 | * Miscellaneous configurable options | |
307 | */ | |
f904cdbb DB |
308 | #define CONFIG_SYS_LONGHELP /* undef to save memory */ |
309 | #define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */ | |
310 | #define CONFIG_SYS_PROMPT_HUSH_PS2 "> " | |
1270ec13 | 311 | #define CONFIG_SYS_PROMPT "OMAP3 beagleboard.org # " |
f62b1257 | 312 | #define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */ |
f904cdbb DB |
313 | /* Print Buffer Size */ |
314 | #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ | |
315 | sizeof(CONFIG_SYS_PROMPT) + 16) | |
933d3701 | 316 | #define CONFIG_SYS_MAXARGS 32 /* max number of command args */ |
f904cdbb DB |
317 | /* Boot Argument Buffer Size */ |
318 | #define CONFIG_SYS_BARGSIZE (CONFIG_SYS_CBSIZE) | |
319 | ||
780a97f8 JK |
320 | #define CONFIG_SYS_ALT_MEMTEST 1 |
321 | #define CONFIG_SYS_MEMTEST_START (0x82000000) /* memtest */ | |
322 | /* defaults */ | |
323 | #define CONFIG_SYS_MEMTEST_END (0x87FFFFFF) /* 128MB */ | |
324 | #define CONFIG_SYS_MEMTEST_SCRATCH (0x81000000) /* dummy address */ | |
f904cdbb | 325 | |
f904cdbb DB |
326 | #define CONFIG_SYS_LOAD_ADDR (OMAP34XX_SDRC_CS0) /* default */ |
327 | /* load address */ | |
328 | ||
329 | /* | |
d3a513c2 MP |
330 | * OMAP3 has 12 GP timers, they can be driven by the system clock |
331 | * (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK). | |
332 | * This rate is divided by a local divisor. | |
f904cdbb | 333 | */ |
f904cdbb | 334 | #define CONFIG_SYS_TIMERBASE (OMAP34XX_GPT2) |
d3a513c2 MP |
335 | #define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */ |
336 | #define CONFIG_SYS_HZ 1000 | |
f904cdbb DB |
337 | |
338 | /*----------------------------------------------------------------------- | |
339 | * Stack sizes | |
340 | * | |
341 | * The stack sizes are set up in start.S using the settings below | |
342 | */ | |
9c44ddcc | 343 | #define CONFIG_STACKSIZE (128 << 10) /* regular stack 128 KiB */ |
f904cdbb DB |
344 | |
345 | /*----------------------------------------------------------------------- | |
346 | * Physical Memory Map | |
347 | */ | |
348 | #define CONFIG_NR_DRAM_BANKS 2 /* CS1 may or may not be populated */ | |
349 | #define PHYS_SDRAM_1 OMAP34XX_SDRC_CS0 | |
f904cdbb DB |
350 | #define PHYS_SDRAM_2 OMAP34XX_SDRC_CS1 |
351 | ||
f904cdbb DB |
352 | /*----------------------------------------------------------------------- |
353 | * FLASH and environment organization | |
354 | */ | |
355 | ||
356 | /* **** PISMO SUPPORT *** */ | |
357 | ||
358 | /* Configure the PISMO */ | |
359 | #define PISMO1_NAND_SIZE GPMC_SIZE_128M | |
360 | #define PISMO1_ONEN_SIZE GPMC_SIZE_128M | |
361 | ||
9c44ddcc | 362 | #define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 2 sectors */ |
f904cdbb | 363 | |
6cbec7b3 LC |
364 | #if defined(CONFIG_CMD_NAND) |
365 | #define CONFIG_SYS_FLASH_BASE PISMO1_NAND_BASE | |
366 | #endif | |
f904cdbb DB |
367 | |
368 | /* Monitor at start of flash */ | |
369 | #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE | |
370 | #define CONFIG_SYS_ONENAND_BASE ONENAND_MAP | |
371 | ||
372 | #define CONFIG_ENV_IS_IN_NAND 1 | |
373 | #define ONENAND_ENV_OFFSET 0x260000 /* environment starts here */ | |
374 | #define SMNAND_ENV_OFFSET 0x260000 /* environment starts here */ | |
375 | ||
6cbec7b3 LC |
376 | #define CONFIG_SYS_ENV_SECT_SIZE (128 << 10) /* 128 KiB */ |
377 | #define CONFIG_ENV_OFFSET SMNAND_ENV_OFFSET | |
f904cdbb DB |
378 | #define CONFIG_ENV_ADDR SMNAND_ENV_OFFSET |
379 | ||
561142af | 380 | #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 |
31bfcf1c SS |
381 | #define CONFIG_SYS_INIT_RAM_ADDR 0x4020f800 |
382 | #define CONFIG_SYS_INIT_RAM_SIZE 0x800 | |
383 | #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \ | |
384 | CONFIG_SYS_INIT_RAM_SIZE - \ | |
385 | GENERATED_GBL_DATA_SIZE) | |
561142af | 386 | |
53736baa DB |
387 | #define CONFIG_OMAP3_SPI |
388 | ||
8e40852f A |
389 | #define CONFIG_SYS_CACHELINE_SIZE 64 |
390 | ||
75c57a35 TR |
391 | /* Defines for SPL */ |
392 | #define CONFIG_SPL | |
393 | #define CONFIG_SPL_NAND_SIMPLE | |
394 | #define CONFIG_SPL_TEXT_BASE 0x40200800 | |
395 | #define CONFIG_SPL_MAX_SIZE (45 * 1024) | |
396 | #define CONFIG_SPL_STACK LOW_LEVEL_SRAM_STACK | |
397 | ||
398 | #define CONFIG_SPL_BSS_START_ADDR 0x80000000 | |
399 | #define CONFIG_SPL_BSS_MAX_SIZE 0x80000 /* 512 KB */ | |
400 | ||
401 | #define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x300 /* address 0x60000 */ | |
402 | #define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS 0x200 /* 256 KB */ | |
403 | #define CONFIG_SYS_MMC_SD_FAT_BOOT_PARTITION 1 | |
404 | #define CONFIG_SPL_FAT_LOAD_PAYLOAD_NAME "u-boot.img" | |
405 | ||
406 | #define CONFIG_SPL_LIBCOMMON_SUPPORT | |
407 | #define CONFIG_SPL_LIBDISK_SUPPORT | |
408 | #define CONFIG_SPL_I2C_SUPPORT | |
409 | #define CONFIG_SPL_LIBGENERIC_SUPPORT | |
410 | #define CONFIG_SPL_MMC_SUPPORT | |
411 | #define CONFIG_SPL_FAT_SUPPORT | |
412 | #define CONFIG_SPL_SERIAL_SUPPORT | |
413 | #define CONFIG_SPL_NAND_SUPPORT | |
414 | #define CONFIG_SPL_POWER_SUPPORT | |
415 | #define CONFIG_SPL_OMAP3_ID_NAND | |
416 | #define CONFIG_SPL_LDSCRIPT "$(CPUDIR)/omap-common/u-boot-spl.lds" | |
417 | ||
418 | /* NAND boot config */ | |
419 | #define CONFIG_SYS_NAND_5_ADDR_CYCLE | |
420 | #define CONFIG_SYS_NAND_PAGE_COUNT 64 | |
421 | #define CONFIG_SYS_NAND_PAGE_SIZE 2048 | |
422 | #define CONFIG_SYS_NAND_OOBSIZE 64 | |
423 | #define CONFIG_SYS_NAND_BLOCK_SIZE (128*1024) | |
424 | #define CONFIG_SYS_NAND_BAD_BLOCK_POS 0 | |
425 | #define CONFIG_SYS_NAND_ECCPOS {2, 3, 4, 5, 6, 7, 8, 9,\ | |
426 | 10, 11, 12, 13} | |
427 | #define CONFIG_SYS_NAND_ECCSIZE 512 | |
428 | #define CONFIG_SYS_NAND_ECCBYTES 3 | |
75c57a35 TR |
429 | #define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE |
430 | #define CONFIG_SYS_NAND_U_BOOT_OFFS 0x80000 | |
431 | ||
432 | /* | |
433 | * 1MB into the SDRAM to allow for SPL's bss at the beginning of SDRAM | |
434 | * 64 bytes before this address should be set aside for u-boot.img's | |
435 | * header. That is 0x800FFFC0--0x80100000 should not be used for any | |
436 | * other needs. | |
437 | */ | |
438 | #define CONFIG_SYS_TEXT_BASE 0x80100000 | |
439 | #define CONFIG_SYS_SPL_MALLOC_START 0x80208000 | |
440 | #define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000 | |
441 | ||
f904cdbb | 442 | #endif /* __CONFIG_H */ |