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f904cdbb DB |
1 | /* |
2 | * (C) Copyright 2006-2008 | |
3 | * Texas Instruments. | |
4 | * Richard Woodruff <r-woodruff2@ti.com> | |
5 | * Syed Mohammed Khasim <x0khasim@ti.com> | |
6 | * | |
7 | * Configuration settings for the TI OMAP3530 Beagle board. | |
8 | * | |
9 | * See file CREDITS for list of people who contributed to this | |
10 | * project. | |
11 | * | |
12 | * This program is free software; you can redistribute it and/or | |
13 | * modify it under the terms of the GNU General Public License as | |
14 | * published by the Free Software Foundation; either version 2 of | |
15 | * the License, or (at your option) any later version. | |
16 | * | |
17 | * This program is distributed in the hope that it will be useful, | |
18 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
19 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
20 | * GNU General Public License for more details. | |
21 | * | |
22 | * You should have received a copy of the GNU General Public License | |
23 | * along with this program; if not, write to the Free Software | |
24 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | |
25 | * MA 02111-1307 USA | |
26 | */ | |
27 | ||
28 | #ifndef __CONFIG_H | |
29 | #define __CONFIG_H | |
f904cdbb DB |
30 | |
31 | /* | |
32 | * High Level Configuration Options | |
33 | */ | |
f56348af | 34 | #define CONFIG_ARMV7 1 /* This is an ARM V7 CPU core */ |
f904cdbb DB |
35 | #define CONFIG_OMAP 1 /* in a TI OMAP core */ |
36 | #define CONFIG_OMAP34XX 1 /* which is a 34XX */ | |
37 | #define CONFIG_OMAP3430 1 /* which is in a 3430 */ | |
38 | #define CONFIG_OMAP3_BEAGLE 1 /* working with BEAGLE */ | |
39 | ||
cae377b5 VH |
40 | #define CONFIG_SDRC /* The chip has SDRC controller */ |
41 | ||
f904cdbb DB |
42 | #include <asm/arch/cpu.h> /* get chip and board defs */ |
43 | #include <asm/arch/omap3.h> | |
44 | ||
6a6b62e3 SP |
45 | /* |
46 | * Display CPU and Board information | |
47 | */ | |
48 | #define CONFIG_DISPLAY_CPUINFO 1 | |
49 | #define CONFIG_DISPLAY_BOARDINFO 1 | |
50 | ||
f904cdbb DB |
51 | /* Clock Defines */ |
52 | #define V_OSCK 26000000 /* Clock output from T2 */ | |
53 | #define V_SCLK (V_OSCK >> 1) | |
54 | ||
55 | #undef CONFIG_USE_IRQ /* no support for IRQs */ | |
56 | #define CONFIG_MISC_INIT_R | |
57 | ||
b485556b JR |
58 | #define CONFIG_OF_LIBFDT 1 |
59 | /* | |
60 | * The early kernel mapping on ARM currently only maps from the base of DRAM | |
61 | * to the end of the kernel image. The kernel is loaded at DRAM base + 0x8000. | |
62 | * The early kernel pagetable uses DRAM base + 0x4000 to DRAM base + 0x8000, | |
63 | * so that leaves DRAM base to DRAM base + 0x4000 available. | |
64 | */ | |
65 | #define CONFIG_SYS_BOOTMAPSZ 0x4000 | |
66 | ||
f904cdbb DB |
67 | #define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ |
68 | #define CONFIG_SETUP_MEMORY_TAGS 1 | |
69 | #define CONFIG_INITRD_TAG 1 | |
70 | #define CONFIG_REVISION_TAG 1 | |
71 | ||
72 | /* | |
73 | * Size of malloc() pool | |
74 | */ | |
9c44ddcc | 75 | #define CONFIG_ENV_SIZE (128 << 10) /* 128 KiB */ |
f904cdbb | 76 | /* Sector */ |
9c44ddcc | 77 | #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (128 << 10)) |
f904cdbb DB |
78 | /* initial data */ |
79 | ||
80 | /* | |
81 | * Hardware drivers | |
82 | */ | |
83 | ||
84 | /* | |
85 | * NS16550 Configuration | |
86 | */ | |
87 | #define V_NS16550_CLK 48000000 /* 48MHz (APLL96/2) */ | |
88 | ||
89 | #define CONFIG_SYS_NS16550 | |
90 | #define CONFIG_SYS_NS16550_SERIAL | |
91 | #define CONFIG_SYS_NS16550_REG_SIZE (-4) | |
92 | #define CONFIG_SYS_NS16550_CLK V_NS16550_CLK | |
93 | ||
94 | /* | |
95 | * select serial console configuration | |
96 | */ | |
97 | #define CONFIG_CONS_INDEX 3 | |
98 | #define CONFIG_SYS_NS16550_COM3 OMAP34XX_UART3 | |
99 | #define CONFIG_SERIAL3 3 /* UART3 on Beagle Rev 2 */ | |
100 | ||
101 | /* allow to overwrite serial and ethaddr */ | |
102 | #define CONFIG_ENV_OVERWRITE | |
103 | #define CONFIG_BAUDRATE 115200 | |
104 | #define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600,\ | |
105 | 115200} | |
0cd31144 | 106 | #define CONFIG_GENERIC_MMC 1 |
f904cdbb | 107 | #define CONFIG_MMC 1 |
0cd31144 | 108 | #define CONFIG_OMAP_HSMMC 1 |
f904cdbb DB |
109 | #define CONFIG_DOS_PARTITION 1 |
110 | ||
70d8c944 JK |
111 | /* Status LED */ |
112 | #define CONFIG_STATUS_LED 1 | |
113 | #define CONFIG_BOARD_SPECIFIC_LED 1 | |
114 | #define STATUS_LED_BIT 0x01 | |
115 | #define STATUS_LED_STATE STATUS_LED_ON | |
116 | #define STATUS_LED_PERIOD (CONFIG_SYS_HZ / 2) | |
117 | #define STATUS_LED_BIT1 0x02 | |
118 | #define STATUS_LED_STATE1 STATUS_LED_ON | |
119 | #define STATUS_LED_PERIOD1 (CONFIG_SYS_HZ / 2) | |
120 | #define STATUS_LED_BOOT STATUS_LED_BIT | |
121 | #define STATUS_LED_GREEN STATUS_LED_BIT1 | |
122 | ||
30563a04 NM |
123 | /* DDR - I use Micron DDR */ |
124 | #define CONFIG_OMAP3_MICRON_DDR 1 | |
125 | ||
25374bfb TR |
126 | /* USB */ |
127 | #define CONFIG_MUSB_UDC 1 | |
128 | #define CONFIG_USB_OMAP3 1 | |
129 | #define CONFIG_TWL4030_USB 1 | |
130 | ||
131 | /* USB device configuration */ | |
132 | #define CONFIG_USB_DEVICE 1 | |
133 | #define CONFIG_USB_TTY 1 | |
134 | #define CONFIG_SYS_CONSOLE_IS_IN_ENV 1 | |
25374bfb | 135 | |
f904cdbb DB |
136 | /* commands to include */ |
137 | #include <config_cmd_default.h> | |
138 | ||
95c6f6d3 | 139 | #define CONFIG_CMD_CACHE |
f904cdbb DB |
140 | #define CONFIG_CMD_EXT2 /* EXT2 Support */ |
141 | #define CONFIG_CMD_FAT /* FAT support */ | |
142 | #define CONFIG_CMD_JFFS2 /* JFFS2 Support */ | |
917cfc70 | 143 | #define CONFIG_CMD_MTDPARTS /* Enable MTD parts commands */ |
942556a9 | 144 | #define CONFIG_MTD_DEVICE /* needed for mtdparts commands */ |
917cfc70 NM |
145 | #define MTDIDS_DEFAULT "nand0=nand" |
146 | #define MTDPARTS_DEFAULT "mtdparts=nand:512k(x-loader),"\ | |
147 | "1920k(u-boot),128k(u-boot-env),"\ | |
148 | "4m(kernel),-(fs)" | |
f904cdbb DB |
149 | |
150 | #define CONFIG_CMD_I2C /* I2C serial bus support */ | |
151 | #define CONFIG_CMD_MMC /* MMC support */ | |
152 | #define CONFIG_CMD_NAND /* NAND support */ | |
70d8c944 | 153 | #define CONFIG_CMD_LED /* LED support */ |
f904cdbb DB |
154 | |
155 | #undef CONFIG_CMD_FLASH /* flinfo, erase, protect */ | |
156 | #undef CONFIG_CMD_FPGA /* FPGA configuration Support */ | |
157 | #undef CONFIG_CMD_IMI /* iminfo */ | |
158 | #undef CONFIG_CMD_IMLS /* List all found images */ | |
159 | #undef CONFIG_CMD_NET /* bootp, tftpboot, rarpboot */ | |
160 | #undef CONFIG_CMD_NFS /* NFS support */ | |
161 | ||
162 | #define CONFIG_SYS_NO_FLASH | |
0297ec7e | 163 | #define CONFIG_HARD_I2C 1 |
f904cdbb DB |
164 | #define CONFIG_SYS_I2C_SPEED 100000 |
165 | #define CONFIG_SYS_I2C_SLAVE 1 | |
166 | #define CONFIG_SYS_I2C_BUS 0 | |
167 | #define CONFIG_SYS_I2C_BUS_SELECT 1 | |
ca5f80ae | 168 | #define CONFIG_I2C_MULTI_BUS 1 |
f904cdbb DB |
169 | #define CONFIG_DRIVER_OMAP34XX_I2C 1 |
170 | ||
2c155130 TR |
171 | /* |
172 | * TWL4030 | |
173 | */ | |
174 | #define CONFIG_TWL4030_POWER 1 | |
175 | #define CONFIG_TWL4030_LED 1 | |
176 | ||
f904cdbb DB |
177 | /* |
178 | * Board NAND Info. | |
179 | */ | |
60c23173 | 180 | #define CONFIG_SYS_NAND_QUIET_TEST 1 |
f904cdbb DB |
181 | #define CONFIG_NAND_OMAP_GPMC |
182 | #define CONFIG_SYS_NAND_ADDR NAND_BASE /* physical address */ | |
183 | /* to access nand */ | |
184 | #define CONFIG_SYS_NAND_BASE NAND_BASE /* physical address */ | |
185 | /* to access nand at */ | |
186 | /* CS0 */ | |
187 | #define GPMC_NAND_ECC_LP_x16_LAYOUT 1 | |
188 | ||
189 | #define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND */ | |
190 | /* devices */ | |
f904cdbb DB |
191 | #define CONFIG_JFFS2_NAND |
192 | /* nand device jffs2 lives on */ | |
193 | #define CONFIG_JFFS2_DEV "nand0" | |
194 | /* start of jffs2 partition */ | |
195 | #define CONFIG_JFFS2_PART_OFFSET 0x680000 | |
196 | #define CONFIG_JFFS2_PART_SIZE 0xf980000 /* size of jffs2 */ | |
197 | /* partition */ | |
198 | ||
199 | /* Environment information */ | |
200 | #define CONFIG_BOOTDELAY 10 | |
201 | ||
202 | #define CONFIG_EXTRA_ENV_SETTINGS \ | |
203 | "loadaddr=0x82000000\0" \ | |
25374bfb | 204 | "usbtty=cdc_acm\0" \ |
f904cdbb | 205 | "console=ttyS2,115200n8\0" \ |
5af32460 | 206 | "mpurate=500\0" \ |
13d2cb98 SS |
207 | "vram=12M\0" \ |
208 | "dvimode=1024x768MR-16@60\0" \ | |
209 | "defaultdisplay=dvi\0" \ | |
0cd31144 | 210 | "mmcdev=0\0" \ |
13d2cb98 SS |
211 | "mmcroot=/dev/mmcblk0p2 rw\0" \ |
212 | "mmcrootfstype=ext3 rootwait\0" \ | |
213 | "nandroot=/dev/mtdblock4 rw\0" \ | |
214 | "nandrootfstype=jffs2\0" \ | |
f904cdbb | 215 | "mmcargs=setenv bootargs console=${console} " \ |
5af32460 | 216 | "mpurate=${mpurate} " \ |
13d2cb98 SS |
217 | "vram=${vram} " \ |
218 | "omapfb.mode=dvi:${dvimode} " \ | |
219 | "omapfb.debug=y " \ | |
220 | "omapdss.def_disp=${defaultdisplay} " \ | |
221 | "root=${mmcroot} " \ | |
222 | "rootfstype=${mmcrootfstype}\0" \ | |
f904cdbb | 223 | "nandargs=setenv bootargs console=${console} " \ |
5af32460 | 224 | "mpurate=${mpurate} " \ |
13d2cb98 SS |
225 | "vram=${vram} " \ |
226 | "omapfb.mode=dvi:${dvimode} " \ | |
227 | "omapfb.debug=y " \ | |
228 | "omapdss.def_disp=${defaultdisplay} " \ | |
229 | "root=${nandroot} " \ | |
230 | "rootfstype=${nandrootfstype}\0" \ | |
cf073e49 AH |
231 | "loadbootenv=fatload mmc ${mmcdev} ${loadaddr} uEnv.txt\0" \ |
232 | "importbootenv=echo Importing environment from mmc ...; " \ | |
233 | "env import -t $loadaddr $filesize\0" \ | |
0cd31144 | 234 | "loaduimage=fatload mmc ${mmcdev} ${loadaddr} uImage\0" \ |
f904cdbb DB |
235 | "mmcboot=echo Booting from mmc ...; " \ |
236 | "run mmcargs; " \ | |
237 | "bootm ${loadaddr}\0" \ | |
238 | "nandboot=echo Booting from nand ...; " \ | |
239 | "run nandargs; " \ | |
240 | "nand read ${loadaddr} 280000 400000; " \ | |
241 | "bootm ${loadaddr}\0" \ | |
242 | ||
243 | #define CONFIG_BOOTCOMMAND \ | |
0cd31144 | 244 | "if mmc rescan ${mmcdev}; then " \ |
cf073e49 AH |
245 | "echo SD/MMC found on device ${mmcdev};" \ |
246 | "if run loadbootenv; then " \ | |
247 | "run importbootenv;" \ | |
248 | "fi;" \ | |
249 | "if test -n $uenvcmd; then " \ | |
250 | "echo Running uenvcmd ...;" \ | |
251 | "run uenvcmd;" \ | |
252 | "fi;" \ | |
253 | "if run loaduimage; then " \ | |
254 | "run mmcboot;" \ | |
255 | "fi;" \ | |
256 | "fi;" \ | |
257 | "run nandboot;" \ | |
f904cdbb DB |
258 | |
259 | #define CONFIG_AUTO_COMPLETE 1 | |
260 | /* | |
261 | * Miscellaneous configurable options | |
262 | */ | |
f904cdbb DB |
263 | #define CONFIG_SYS_LONGHELP /* undef to save memory */ |
264 | #define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */ | |
265 | #define CONFIG_SYS_PROMPT_HUSH_PS2 "> " | |
1270ec13 | 266 | #define CONFIG_SYS_PROMPT "OMAP3 beagleboard.org # " |
f904cdbb DB |
267 | #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ |
268 | /* Print Buffer Size */ | |
269 | #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ | |
270 | sizeof(CONFIG_SYS_PROMPT) + 16) | |
271 | #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ | |
272 | /* Boot Argument Buffer Size */ | |
273 | #define CONFIG_SYS_BARGSIZE (CONFIG_SYS_CBSIZE) | |
274 | ||
275 | #define CONFIG_SYS_MEMTEST_START (OMAP34XX_SDRC_CS0) /* memtest */ | |
276 | /* works on */ | |
277 | #define CONFIG_SYS_MEMTEST_END (OMAP34XX_SDRC_CS0 + \ | |
278 | 0x01F00000) /* 31MB */ | |
279 | ||
f904cdbb DB |
280 | #define CONFIG_SYS_LOAD_ADDR (OMAP34XX_SDRC_CS0) /* default */ |
281 | /* load address */ | |
282 | ||
283 | /* | |
d3a513c2 MP |
284 | * OMAP3 has 12 GP timers, they can be driven by the system clock |
285 | * (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK). | |
286 | * This rate is divided by a local divisor. | |
f904cdbb | 287 | */ |
f904cdbb | 288 | #define CONFIG_SYS_TIMERBASE (OMAP34XX_GPT2) |
d3a513c2 MP |
289 | #define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */ |
290 | #define CONFIG_SYS_HZ 1000 | |
f904cdbb DB |
291 | |
292 | /*----------------------------------------------------------------------- | |
293 | * Stack sizes | |
294 | * | |
295 | * The stack sizes are set up in start.S using the settings below | |
296 | */ | |
9c44ddcc | 297 | #define CONFIG_STACKSIZE (128 << 10) /* regular stack 128 KiB */ |
f904cdbb | 298 | #ifdef CONFIG_USE_IRQ |
9c44ddcc SP |
299 | #define CONFIG_STACKSIZE_IRQ (4 << 10) /* IRQ stack 4 KiB */ |
300 | #define CONFIG_STACKSIZE_FIQ (4 << 10) /* FIQ stack 4 KiB */ | |
f904cdbb DB |
301 | #endif |
302 | ||
303 | /*----------------------------------------------------------------------- | |
304 | * Physical Memory Map | |
305 | */ | |
306 | #define CONFIG_NR_DRAM_BANKS 2 /* CS1 may or may not be populated */ | |
307 | #define PHYS_SDRAM_1 OMAP34XX_SDRC_CS0 | |
9c44ddcc | 308 | #define PHYS_SDRAM_1_SIZE (32 << 20) /* at least 32 MiB */ |
f904cdbb DB |
309 | #define PHYS_SDRAM_2 OMAP34XX_SDRC_CS1 |
310 | ||
311 | /* SDRAM Bank Allocation method */ | |
312 | #define SDRC_R_B_C 1 | |
313 | ||
314 | /*----------------------------------------------------------------------- | |
315 | * FLASH and environment organization | |
316 | */ | |
317 | ||
318 | /* **** PISMO SUPPORT *** */ | |
319 | ||
320 | /* Configure the PISMO */ | |
321 | #define PISMO1_NAND_SIZE GPMC_SIZE_128M | |
322 | #define PISMO1_ONEN_SIZE GPMC_SIZE_128M | |
323 | ||
9c44ddcc | 324 | #define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 2 sectors */ |
f904cdbb DB |
325 | |
326 | #define CONFIG_SYS_FLASH_BASE boot_flash_base | |
327 | ||
328 | /* Monitor at start of flash */ | |
329 | #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE | |
330 | #define CONFIG_SYS_ONENAND_BASE ONENAND_MAP | |
331 | ||
332 | #define CONFIG_ENV_IS_IN_NAND 1 | |
333 | #define ONENAND_ENV_OFFSET 0x260000 /* environment starts here */ | |
334 | #define SMNAND_ENV_OFFSET 0x260000 /* environment starts here */ | |
335 | ||
336 | #define CONFIG_SYS_ENV_SECT_SIZE boot_flash_sec | |
337 | #define CONFIG_ENV_OFFSET boot_flash_off | |
338 | #define CONFIG_ENV_ADDR SMNAND_ENV_OFFSET | |
339 | ||
f904cdbb | 340 | #ifndef __ASSEMBLY__ |
f904cdbb DB |
341 | extern unsigned int boot_flash_base; |
342 | extern volatile unsigned int boot_flash_env_addr; | |
343 | extern unsigned int boot_flash_off; | |
344 | extern unsigned int boot_flash_sec; | |
345 | extern unsigned int boot_flash_type; | |
346 | #endif | |
347 | ||
561142af | 348 | #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 |
31bfcf1c SS |
349 | #define CONFIG_SYS_INIT_RAM_ADDR 0x4020f800 |
350 | #define CONFIG_SYS_INIT_RAM_SIZE 0x800 | |
351 | #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \ | |
352 | CONFIG_SYS_INIT_RAM_SIZE - \ | |
353 | GENERATED_GBL_DATA_SIZE) | |
561142af | 354 | |
53736baa DB |
355 | #define CONFIG_OMAP3_SPI |
356 | ||
f904cdbb | 357 | #endif /* __CONFIG_H */ |