[people/ms/u-boot.git] / include / configs / omap3_beagle.h

/*
 * (C) Copyright 2006-2008
 * Texas Instruments.
 * Richard Woodruff <r-woodruff2@ti.com>
 * Syed Mohammed Khasim <x0khasim@ti.com>
 *
 * Configuration settings for the TI OMAP3530 Beagle board.
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

#ifndef __CONFIG_H
#define __CONFIG_H

/*
 * High Level Configuration Options
 */
#define CONFIG_OMAP		1	/* in a TI OMAP core */
#define CONFIG_OMAP34XX		1	/* which is a 34XX */
#define CONFIG_OMAP3_BEAGLE	1	/* working with BEAGLE */
#define CONFIG_OMAP_GPIO
#define CONFIG_OMAP_COMMON

#define CONFIG_SDRC	/* The chip has SDRC controller */

#include <asm/arch/cpu.h>		/* get chip and board defs */
#include <asm/arch/omap3.h>

/*
 * Display CPU and Board information
 */
#define CONFIG_DISPLAY_CPUINFO		1
#define CONFIG_DISPLAY_BOARDINFO	1

/* Clock Defines */
#define V_OSCK			26000000	/* Clock output from T2 */
#define V_SCLK			(V_OSCK >> 1)

#define CONFIG_MISC_INIT_R

#define CONFIG_OF_LIBFDT
#define CONFIG_CMD_BOOTZ

#define CONFIG_CMDLINE_TAG		1	/* enable passing of ATAGs */
#define CONFIG_SETUP_MEMORY_TAGS	1
#define CONFIG_INITRD_TAG		1
#define CONFIG_REVISION_TAG		1

/*
 * Size of malloc() pool
 */
#define CONFIG_ENV_SIZE			(128 << 10)	/* 128 KiB */
						/* Sector */
#define CONFIG_SYS_MALLOC_LEN		(CONFIG_ENV_SIZE + (128 << 10))

/*
 * Hardware drivers
 */

/*
 * NS16550 Configuration
 */
#define V_NS16550_CLK			48000000	/* 48MHz (APLL96/2) */

#define CONFIG_SYS_NS16550
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE	(-4)
#define CONFIG_SYS_NS16550_CLK		V_NS16550_CLK

/*
 * select serial console configuration
 */
#define CONFIG_CONS_INDEX		3
#define CONFIG_SYS_NS16550_COM3		OMAP34XX_UART3
#define CONFIG_SERIAL3			3	/* UART3 on Beagle Rev 2 */

/* allow to overwrite serial and ethaddr */
#define CONFIG_ENV_OVERWRITE
#define CONFIG_BAUDRATE			115200
#define CONFIG_SYS_BAUDRATE_TABLE	{4800, 9600, 19200, 38400, 57600,\
					115200}
#define CONFIG_GENERIC_MMC		1
#define CONFIG_MMC			1
#define CONFIG_OMAP_HSMMC		1
#define CONFIG_DOS_PARTITION		1

/* Status LED */
#define CONFIG_STATUS_LED		1
#define CONFIG_BOARD_SPECIFIC_LED	1
#define STATUS_LED_BIT			0x01
#define STATUS_LED_STATE		STATUS_LED_ON
#define STATUS_LED_PERIOD		(CONFIG_SYS_HZ / 2)
#define STATUS_LED_BIT1			0x02
#define STATUS_LED_STATE1		STATUS_LED_ON
#define STATUS_LED_PERIOD1		(CONFIG_SYS_HZ / 2)
#define STATUS_LED_BOOT			STATUS_LED_BIT
#define STATUS_LED_GREEN		STATUS_LED_BIT1

/* Enable Multi Bus support for I2C */
#define CONFIG_I2C_MULTI_BUS		1

/* Probe all devices */
#define CONFIG_SYS_I2C_NOPROBES		{{0x0, 0x0}}

/* USB */
#define CONFIG_MUSB_GADGET
#define CONFIG_USB_MUSB_OMAP2PLUS
#define CONFIG_MUSB_PIO_ONLY
#define CONFIG_USB_GADGET_DUALSPEED
#define CONFIG_TWL4030_USB		1
#define CONFIG_USB_ETHER
#define CONFIG_USB_ETHER_RNDIS

/* USB EHCI */
#define CONFIG_CMD_USB
#define CONFIG_USB_EHCI

#define CONFIG_USB_EHCI_OMAP
#define CONFIG_OMAP_EHCI_PHY1_RESET_GPIO	147

#define CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS 3
#define CONFIG_USB_HOST_ETHER
#define CONFIG_USB_ETHER_SMSC95XX
#define CONFIG_USB_ETHER_ASIX

/* GPIO banks */
#define CONFIG_OMAP3_GPIO_5		/* GPIO128..159 is in GPIO bank 5 */
#define CONFIG_OMAP3_GPIO_6		/* GPIO160..191 is in GPIO bank 6 */

/* commands to include */
#include <config_cmd_default.h>

#define CONFIG_CMD_ASKENV

#define CONFIG_CMD_CACHE
#define CONFIG_CMD_EXT2		/* EXT2 Support			*/
#define CONFIG_CMD_FAT		/* FAT support			*/
#define CONFIG_CMD_FS_GENERIC	/* Generic FS support */
#define CONFIG_CMD_MTDPARTS	/* Enable MTD parts commands */
#define CONFIG_MTD_DEVICE	/* needed for mtdparts commands */
#define MTDIDS_DEFAULT			"nand0=nand"
#define MTDPARTS_DEFAULT		"mtdparts=nand:512k(x-loader),"\
					"1920k(u-boot),128k(u-boot-env),"\
					"4m(kernel),-(fs)"

#define CONFIG_CMD_I2C		/* I2C serial bus support	*/
#define CONFIG_CMD_MMC		/* MMC support			*/
#define CONFIG_USB_STORAGE	/* USB storage support		*/
#define CONFIG_CMD_NAND		/* NAND support			*/
#define CONFIG_CMD_LED		/* LED support			*/
#define CONFIG_CMD_NET      /* bootp, tftpboot, rarpboot    */
#define CONFIG_CMD_NFS      /* NFS support          */
#define CONFIG_CMD_PING
#define CONFIG_CMD_DHCP
#define CONFIG_CMD_SETEXPR	/* Evaluate expressions		*/
#define CONFIG_CMD_GPIO     /* Enable gpio command */

#undef CONFIG_CMD_FLASH		/* flinfo, erase, protect	*/
#undef CONFIG_CMD_FPGA		/* FPGA configuration Support	*/
#undef CONFIG_CMD_IMI		/* iminfo			*/
#undef CONFIG_CMD_IMLS		/* List all found images	*/

#define CONFIG_SYS_NO_FLASH
#define CONFIG_SYS_I2C
#define CONFIG_SYS_OMAP24_I2C_SPEED	100000
#define CONFIG_SYS_OMAP24_I2C_SLAVE	1
#define CONFIG_SYS_I2C_OMAP34XX
#define CONFIG_VIDEO_OMAP3	/* DSS Support			*/

/*
 * TWL4030
 */
#define CONFIG_TWL4030_POWER		1
#define CONFIG_TWL4030_LED		1

/*
 * Board NAND Info.
 */
#define CONFIG_SYS_NAND_QUIET_TEST	1
#define CONFIG_NAND_OMAP_GPMC
#define CONFIG_SYS_NAND_ADDR		NAND_BASE	/* physical address */
							/* to access nand */
#define CONFIG_SYS_NAND_BASE		NAND_BASE	/* physical address */
							/* to access nand at */
							/* CS0 */
#define CONFIG_SYS_MAX_NAND_DEVICE	1		/* Max number of NAND */
							/* devices */

/* Environment information */
#define CONFIG_BOOTDELAY		3

#define CONFIG_EXTRA_ENV_SETTINGS \
	"loadaddr=0x80200000\0" \
	"rdaddr=0x81000000\0" \
	"fdt_high=0xffffffff\0" \
	"fdtaddr=0x80f80000\0" \
	"usbtty=cdc_acm\0" \
	"bootfile=uImage\0" \
	"ramdisk=ramdisk.gz\0" \
	"bootdir=/boot\0" \
	"bootpart=0:2\0" \
	"console=ttyO2,115200n8\0" \
	"mpurate=auto\0" \
	"buddy=none\0" \
	"optargs=\0" \
	"camera=none\0" \
	"vram=12M\0" \
	"dvimode=640x480MR-16@60\0" \
	"defaultdisplay=dvi\0" \
	"mmcdev=0\0" \
	"mmcroot=/dev/mmcblk0p2 rw\0" \
	"mmcrootfstype=ext3 rootwait\0" \
	"nandroot=ubi0:rootfs ubi.mtd=4\0" \
	"nandrootfstype=ubifs\0" \
	"ramroot=/dev/ram0 rw ramdisk_size=65536 initrd=0x81000000,64M\0" \
	"ramrootfstype=ext2\0" \
	"mmcargs=setenv bootargs console=${console} " \
		"${optargs} " \
		"mpurate=${mpurate} " \
		"buddy=${buddy} "\
		"camera=${camera} "\
		"vram=${vram} " \
		"omapfb.mode=dvi:${dvimode} " \
		"omapdss.def_disp=${defaultdisplay} " \
		"root=${mmcroot} " \
		"rootfstype=${mmcrootfstype}\0" \
	"nandargs=setenv bootargs console=${console} " \
		"${optargs} " \
		"mpurate=${mpurate} " \
		"buddy=${buddy} "\
		"camera=${camera} "\
		"vram=${vram} " \
		"omapfb.mode=dvi:${dvimode} " \
		"omapdss.def_disp=${defaultdisplay} " \
		"root=${nandroot} " \
		"rootfstype=${nandrootfstype}\0" \
	"findfdt=" \
		"if test $beaglerev = AxBx; then " \
			"setenv fdtfile omap3-beagle.dtb; fi; " \
		"if test $beaglerev = Cx; then " \
			"setenv fdtfile omap3-beagle.dtb; fi; " \
		"if test $beaglerev = C4; then " \
			"setenv fdtfile omap3-beagle.dtb; fi; " \
		"if test $beaglerev = xMAB; then " \
			"setenv fdtfile omap3-beagle-xm.dtb; fi; " \
		"if test $beaglerev = xMC; then " \
			"setenv fdtfile omap3-beagle-xm.dtb; fi; " \
		"if test $fdtfile = undefined; then " \
			"echo WARNING: Could not determine device tree to use; fi; \0" \
	"bootenv=uEnv.txt\0" \
	"loadbootenv=fatload mmc ${mmcdev} ${loadaddr} ${bootenv}\0" \
	"importbootenv=echo Importing environment from mmc ...; " \
		"env import -t $loadaddr $filesize\0" \
	"ramargs=setenv bootargs console=${console} " \
		"${optargs} " \
		"mpurate=${mpurate} " \
		"buddy=${buddy} "\
		"vram=${vram} " \
		"omapfb.mode=dvi:${dvimode} " \
		"omapdss.def_disp=${defaultdisplay} " \
		"root=${ramroot} " \
		"rootfstype=${ramrootfstype}\0" \
	"loadramdisk=load mmc ${bootpart} ${rdaddr} ${bootdir}/${ramdisk}\0" \
	"loadimage=load mmc ${bootpart} ${loadaddr} ${bootdir}/${bootfile}\0" \
	"loadfdt=load mmc ${bootpart} ${fdtaddr} ${bootdir}/${fdtfile}\0" \
	"mmcboot=echo Booting from mmc ...; " \
		"run mmcargs; " \
		"bootm ${loadaddr}\0" \
	"mmcbootz=echo Booting with DT from mmc${mmcdev} ...; " \
		"run mmcargs; " \
		"bootz ${loadaddr} - ${fdtaddr}\0" \
	"nandboot=echo Booting from nand ...; " \
		"run nandargs; " \
		"nand read ${loadaddr} 280000 400000; " \
		"bootm ${loadaddr}\0" \
	"ramboot=echo Booting from ramdisk ...; " \
		"run ramargs; " \
		"bootm ${loadaddr}\0" \
	"userbutton=if gpio input 173; then run userbutton_xm; " \
		"else run userbutton_nonxm; fi;\0" \
	"userbutton_xm=gpio input 4;\0" \
	"userbutton_nonxm=gpio input 7;\0"
/* "run userbutton" will return 1 (false) if pressed and 0 (true) if not */
#define CONFIG_BOOTCOMMAND \
	"run findfdt; " \
	"mmc dev ${mmcdev}; if mmc rescan; then " \
		"if run userbutton; then " \
			"setenv bootenv uEnv.txt;" \
		"else " \
			"setenv bootenv user.txt;" \
		"fi;" \
		"echo SD/MMC found on device ${mmcdev};" \
		"if run loadbootenv; then " \
			"echo Loaded environment from ${bootenv};" \
			"run importbootenv;" \
		"fi;" \
		"if test -n $uenvcmd; then " \
			"echo Running uenvcmd ...;" \
			"run uenvcmd;" \
		"fi;" \
		"if run loadimage; then " \
			"run mmcboot;" \
		"fi;" \
	"fi;" \
	"run nandboot;" \
	"setenv bootfile zImage;" \
	"if run loadimage; then " \
		"run loadfdt;" \
		"run mmcbootz; " \
	"fi; " \

#define CONFIG_AUTO_COMPLETE		1
/*
 * Miscellaneous configurable options
 */
#define CONFIG_SYS_LONGHELP		/* undef to save memory */
#define CONFIG_SYS_HUSH_PARSER		/* use "hush" command parser */
#define CONFIG_SYS_PROMPT		"OMAP3 beagleboard.org # "
#define CONFIG_SYS_CBSIZE		512	/* Console I/O Buffer Size */
/* Print Buffer Size */
#define CONFIG_SYS_PBSIZE		(CONFIG_SYS_CBSIZE + \
					sizeof(CONFIG_SYS_PROMPT) + 16)
#define CONFIG_SYS_MAXARGS		32	/* max number of command args */
/* Boot Argument Buffer Size */
#define CONFIG_SYS_BARGSIZE		(CONFIG_SYS_CBSIZE)

#define CONFIG_SYS_ALT_MEMTEST		1
#define CONFIG_SYS_MEMTEST_START	(0x82000000)		/* memtest */
								/* defaults */
#define CONFIG_SYS_MEMTEST_END		(0x87FFFFFF) 		/* 128MB */
#define CONFIG_SYS_MEMTEST_SCRATCH	(0x81000000)	/* dummy address */

#define CONFIG_SYS_LOAD_ADDR		(OMAP34XX_SDRC_CS0)	/* default */
							/* load address */

/*
 * OMAP3 has 12 GP timers, they can be driven by the system clock
 * (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK).
 * This rate is divided by a local divisor.
 */
#define CONFIG_SYS_TIMERBASE		(OMAP34XX_GPT2)
#define CONFIG_SYS_PTV			2       /* Divisor: 2^(PTV+1) => 8 */

/*-----------------------------------------------------------------------
 * Physical Memory Map
 */
#define CONFIG_NR_DRAM_BANKS	2	/* CS1 may or may not be populated */
#define PHYS_SDRAM_1		OMAP34XX_SDRC_CS0
#define PHYS_SDRAM_2		OMAP34XX_SDRC_CS1

/*-----------------------------------------------------------------------
 * FLASH and environment organization
 */

/* **** PISMO SUPPORT *** */

/* Configure the PISMO */
#define PISMO1_NAND_SIZE		GPMC_SIZE_128M
#define PISMO1_ONEN_SIZE		GPMC_SIZE_128M

#define CONFIG_SYS_MONITOR_LEN		(256 << 10)	/* Reserve 2 sectors */

#if defined(CONFIG_CMD_NAND)
#define CONFIG_SYS_FLASH_BASE		PISMO1_NAND_BASE
#endif

/* Monitor at start of flash */
#define CONFIG_SYS_MONITOR_BASE		CONFIG_SYS_FLASH_BASE
#define CONFIG_SYS_ONENAND_BASE		ONENAND_MAP

#define CONFIG_ENV_IS_IN_NAND		1
#define ONENAND_ENV_OFFSET		0x260000 /* environment starts here */
#define SMNAND_ENV_OFFSET		0x260000 /* environment starts here */

#define CONFIG_SYS_ENV_SECT_SIZE	(128 << 10)	/* 128 KiB */
#define CONFIG_ENV_OFFSET		SMNAND_ENV_OFFSET
#define CONFIG_ENV_ADDR			SMNAND_ENV_OFFSET

#define CONFIG_SYS_SDRAM_BASE		PHYS_SDRAM_1
#define CONFIG_SYS_INIT_RAM_ADDR	0x4020f800
#define CONFIG_SYS_INIT_RAM_SIZE	0x800
#define CONFIG_SYS_INIT_SP_ADDR		(CONFIG_SYS_INIT_RAM_ADDR + \
					 CONFIG_SYS_INIT_RAM_SIZE - \
					 GENERATED_GBL_DATA_SIZE)

#define CONFIG_OMAP3_SPI

#define CONFIG_SYS_CACHELINE_SIZE	64

/* Defines for SPL */
#define CONFIG_SPL
#define CONFIG_SPL_FRAMEWORK
#define CONFIG_SPL_NAND_SIMPLE
#define CONFIG_SPL_TEXT_BASE		0x40200800
#define CONFIG_SPL_MAX_SIZE		(54 * 1024)	/* 8 KB for stack */
#define CONFIG_SPL_STACK		LOW_LEVEL_SRAM_STACK

#define CONFIG_SPL_BSS_START_ADDR	0x80000000
#define CONFIG_SPL_BSS_MAX_SIZE		0x80000		/* 512 KB */

#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR	0x300 /* address 0x60000 */
#define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS	0x200 /* 256 KB */
#define CONFIG_SYS_MMC_SD_FAT_BOOT_PARTITION	1
#define CONFIG_SPL_FAT_LOAD_PAYLOAD_NAME	"u-boot.img"

#define CONFIG_SPL_BOARD_INIT
#define CONFIG_SPL_LIBCOMMON_SUPPORT
#define CONFIG_SPL_LIBDISK_SUPPORT
#define CONFIG_SPL_I2C_SUPPORT
#define CONFIG_SPL_LIBGENERIC_SUPPORT
#define CONFIG_SPL_MMC_SUPPORT
#define CONFIG_SPL_FAT_SUPPORT
#define CONFIG_SPL_SERIAL_SUPPORT
#define CONFIG_SPL_NAND_SUPPORT
#define CONFIG_SPL_NAND_BASE
#define CONFIG_SPL_NAND_DRIVERS
#define CONFIG_SPL_NAND_ECC
#define CONFIG_SPL_GPIO_SUPPORT
#define CONFIG_SPL_POWER_SUPPORT
#define CONFIG_SPL_OMAP3_ID_NAND
#define CONFIG_SPL_LDSCRIPT		"$(CPUDIR)/omap-common/u-boot-spl.lds"

/* NAND boot config */
#define CONFIG_SYS_NAND_5_ADDR_CYCLE
#define CONFIG_SYS_NAND_PAGE_COUNT	64
#define CONFIG_SYS_NAND_PAGE_SIZE	2048
#define CONFIG_SYS_NAND_OOBSIZE		64
#define CONFIG_SYS_NAND_BLOCK_SIZE	(128*1024)
#define CONFIG_SYS_NAND_BAD_BLOCK_POS	0
#define CONFIG_SYS_NAND_ECCPOS		{2, 3, 4, 5, 6, 7, 8, 9,\
						10, 11, 12, 13}
#define CONFIG_SYS_NAND_ECCSIZE		512
#define CONFIG_SYS_NAND_ECCBYTES	3
#define CONFIG_NAND_OMAP_ECCSCHEME	OMAP_ECC_HAM1_CODE_HW
#define CONFIG_SYS_NAND_U_BOOT_START	CONFIG_SYS_TEXT_BASE
#define CONFIG_SYS_NAND_U_BOOT_OFFS	0x80000

/*
 * 1MB into the SDRAM to allow for SPL's bss at the beginning of SDRAM
 * 64 bytes before this address should be set aside for u-boot.img's
 * header. That is 0x800FFFC0--0x80100000 should not be used for any
 * other needs.
 */
#define CONFIG_SYS_TEXT_BASE		0x80100000
#define CONFIG_SYS_SPL_MALLOC_START	0x80208000
#define CONFIG_SYS_SPL_MALLOC_SIZE	0x100000

#endif /* __CONFIG_H */
Commit	Line	Data
f904cdbb DB	1	/*
	2	* (C) Copyright 2006-2008
	3	* Texas Instruments.
	4	* Richard Woodruff <r-woodruff2@ti.com>
	5	* Syed Mohammed Khasim <x0khasim@ti.com>
	6	*
	7	* Configuration settings for the TI OMAP3530 Beagle board.
	8	*
3765b3e7	9	* SPDX-License-Identifier: GPL-2.0+
f904cdbb DB	10	*/
	11
	12	#ifndef __CONFIG_H
	13	#define __CONFIG_H
f904cdbb DB	14
	15	/*
	16	* High Level Configuration Options
	17	*/
f904cdbb DB	18	#define CONFIG_OMAP 1 /* in a TI OMAP core */
f904cdbb DB	19	#define CONFIG_OMAP34XX 1 /* which is a 34XX */
f904cdbb	20	#define CONFIG_OMAP3_BEAGLE 1 /* working with BEAGLE */
308252ad	21	#define CONFIG_OMAP_GPIO
806d2792	22	#define CONFIG_OMAP_COMMON
f904cdbb	23
cae377b5 VH	24	#define CONFIG_SDRC /* The chip has SDRC controller */
cae377b5 VH	25
f904cdbb DB	26	#include <asm/arch/cpu.h> /* get chip and board defs */
	27	#include <asm/arch/omap3.h>
	28
6a6b62e3 SP	29	/*
	30	* Display CPU and Board information
	31	*/
	32	#define CONFIG_DISPLAY_CPUINFO 1
	33	#define CONFIG_DISPLAY_BOARDINFO 1
	34
f904cdbb DB	35	/* Clock Defines */
	36	#define V_OSCK 26000000 /* Clock output from T2 */
	37	#define V_SCLK (V_OSCK >> 1)
	38
f904cdbb DB	39	#define CONFIG_MISC_INIT_R
f904cdbb DB	40
03a2075a TR	41	#define CONFIG_OF_LIBFDT
03a2075a TR	42	#define CONFIG_CMD_BOOTZ
b485556b	43
f904cdbb DB	44	#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */
	45	#define CONFIG_SETUP_MEMORY_TAGS 1
	46	#define CONFIG_INITRD_TAG 1
	47	#define CONFIG_REVISION_TAG 1
	48
	49	/*
	50	* Size of malloc() pool
	51	*/
9c44ddcc	52	#define CONFIG_ENV_SIZE (128 << 10) /* 128 KiB */
f904cdbb	53	/* Sector */
9c44ddcc	54	#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (128 << 10))
f904cdbb DB	55
	56	/*
	57	* Hardware drivers
	58	*/
	59
	60	/*
	61	* NS16550 Configuration
	62	*/
	63	#define V_NS16550_CLK 48000000 /* 48MHz (APLL96/2) */
	64
	65	#define CONFIG_SYS_NS16550
	66	#define CONFIG_SYS_NS16550_SERIAL
	67	#define CONFIG_SYS_NS16550_REG_SIZE (-4)
	68	#define CONFIG_SYS_NS16550_CLK V_NS16550_CLK
	69
	70	/*
	71	* select serial console configuration
	72	*/
	73	#define CONFIG_CONS_INDEX 3
	74	#define CONFIG_SYS_NS16550_COM3 OMAP34XX_UART3
	75	#define CONFIG_SERIAL3 3 /* UART3 on Beagle Rev 2 */
	76
	77	/* allow to overwrite serial and ethaddr */
	78	#define CONFIG_ENV_OVERWRITE
	79	#define CONFIG_BAUDRATE 115200
	80	#define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600,\
	81	115200}
0cd31144	82	#define CONFIG_GENERIC_MMC 1
f904cdbb	83	#define CONFIG_MMC 1
0cd31144	84	#define CONFIG_OMAP_HSMMC 1
f904cdbb DB	85	#define CONFIG_DOS_PARTITION 1
f904cdbb DB	86
70d8c944 JK	87	/* Status LED */
	88	#define CONFIG_STATUS_LED 1
	89	#define CONFIG_BOARD_SPECIFIC_LED 1
	90	#define STATUS_LED_BIT 0x01
	91	#define STATUS_LED_STATE STATUS_LED_ON
	92	#define STATUS_LED_PERIOD (CONFIG_SYS_HZ / 2)
	93	#define STATUS_LED_BIT1 0x02
	94	#define STATUS_LED_STATE1 STATUS_LED_ON
	95	#define STATUS_LED_PERIOD1 (CONFIG_SYS_HZ / 2)
	96	#define STATUS_LED_BOOT STATUS_LED_BIT
	97	#define STATUS_LED_GREEN STATUS_LED_BIT1
	98
f74fc4ae JK	99	/* Enable Multi Bus support for I2C */
	100	#define CONFIG_I2C_MULTI_BUS 1
	101
	102	/* Probe all devices */
8c4e0ca6	103	#define CONFIG_SYS_I2C_NOPROBES {{0x0, 0x0}}
f74fc4ae	104
25374bfb	105	/* USB */
c2af345e IY	106	#define CONFIG_MUSB_GADGET
	107	#define CONFIG_USB_MUSB_OMAP2PLUS
	108	#define CONFIG_MUSB_PIO_ONLY
	109	#define CONFIG_USB_GADGET_DUALSPEED
25374bfb	110	#define CONFIG_TWL4030_USB 1
c642b151 IY	111	#define CONFIG_USB_ETHER
c642b151 IY	112	#define CONFIG_USB_ETHER_RNDIS
25374bfb	113
d90859a6 AH	114	/* USB EHCI */
	115	#define CONFIG_CMD_USB
	116	#define CONFIG_USB_EHCI
928c4bdf	117
29321c05	118	#define CONFIG_USB_EHCI_OMAP
29321c05 IY	119	#define CONFIG_OMAP_EHCI_PHY1_RESET_GPIO 147
29321c05 IY	120
d90859a6	121	#define CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS 3
2162439a KK	122	#define CONFIG_USB_HOST_ETHER
2162439a KK	123	#define CONFIG_USB_ETHER_SMSC95XX
54b62d59	124	#define CONFIG_USB_ETHER_ASIX
2162439a	125
ce23b18b SR	126	/* GPIO banks */
	127	#define CONFIG_OMAP3_GPIO_5 /* GPIO128..159 is in GPIO bank 5 */
	128	#define CONFIG_OMAP3_GPIO_6 /* GPIO160..191 is in GPIO bank 6 */
d90859a6	129
f904cdbb DB	130	/* commands to include */
	131	#include <config_cmd_default.h>
	132
776bebb7 TR	133	#define CONFIG_CMD_ASKENV
776bebb7 TR	134
95c6f6d3	135	#define CONFIG_CMD_CACHE
f904cdbb DB	136	#define CONFIG_CMD_EXT2 /* EXT2 Support */
f904cdbb DB	137	#define CONFIG_CMD_FAT /* FAT support */
102ce9ea	138	#define CONFIG_CMD_FS_GENERIC /* Generic FS support */
917cfc70	139	#define CONFIG_CMD_MTDPARTS /* Enable MTD parts commands */
942556a9	140	#define CONFIG_MTD_DEVICE /* needed for mtdparts commands */
917cfc70 NM	141	#define MTDIDS_DEFAULT "nand0=nand"
	142	#define MTDPARTS_DEFAULT "mtdparts=nand:512k(x-loader),"\
	143	"1920k(u-boot),128k(u-boot-env),"\
	144	"4m(kernel),-(fs)"
f904cdbb DB	145
	146	#define CONFIG_CMD_I2C /* I2C serial bus support */
	147	#define CONFIG_CMD_MMC /* MMC support */
d90859a6	148	#define CONFIG_USB_STORAGE /* USB storage support */
f904cdbb	149	#define CONFIG_CMD_NAND /* NAND support */
70d8c944	150	#define CONFIG_CMD_LED /* LED support */
2162439a KK	151	#define CONFIG_CMD_NET /* bootp, tftpboot, rarpboot */
	152	#define CONFIG_CMD_NFS /* NFS support */
	153	#define CONFIG_CMD_PING
54b62d59	154	#define CONFIG_CMD_DHCP
933d3701	155	#define CONFIG_CMD_SETEXPR /* Evaluate expressions */
aae58b95	156	#define CONFIG_CMD_GPIO /* Enable gpio command */
f904cdbb DB	157
	158	#undef CONFIG_CMD_FLASH /* flinfo, erase, protect */
	159	#undef CONFIG_CMD_FPGA /* FPGA configuration Support */
	160	#undef CONFIG_CMD_IMI /* iminfo */
	161	#undef CONFIG_CMD_IMLS /* List all found images */
f904cdbb DB	162
f904cdbb DB	163	#define CONFIG_SYS_NO_FLASH
6789e84e HS	164	#define CONFIG_SYS_I2C
	165	#define CONFIG_SYS_OMAP24_I2C_SPEED 100000
	166	#define CONFIG_SYS_OMAP24_I2C_SLAVE 1
	167	#define CONFIG_SYS_I2C_OMAP34XX
25a4d017	168	#define CONFIG_VIDEO_OMAP3 /* DSS Support */
f904cdbb	169
2c155130 TR	170	/*
	171	* TWL4030
	172	*/
	173	#define CONFIG_TWL4030_POWER 1
	174	#define CONFIG_TWL4030_LED 1
	175
f904cdbb DB	176	/*
	177	* Board NAND Info.
	178	*/
60c23173	179	#define CONFIG_SYS_NAND_QUIET_TEST 1
f904cdbb DB	180	#define CONFIG_NAND_OMAP_GPMC
	181	#define CONFIG_SYS_NAND_ADDR NAND_BASE /* physical address */
	182	/* to access nand */
	183	#define CONFIG_SYS_NAND_BASE NAND_BASE /* physical address */
	184	/* to access nand at */
	185	/* CS0 */
f904cdbb DB	186	#define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND */
f904cdbb DB	187	/* devices */
f904cdbb DB	188
f904cdbb DB	189	/* Environment information */
1dd07fe8	190	#define CONFIG_BOOTDELAY 3
f904cdbb DB	191
f904cdbb DB	192	#define CONFIG_EXTRA_ENV_SETTINGS \
f4b36ea9 JK	193	"loadaddr=0x80200000\0" \
f4b36ea9 JK	194	"rdaddr=0x81000000\0" \
2ade496f NM	195	"fdt_high=0xffffffff\0" \
2ade496f NM	196	"fdtaddr=0x80f80000\0" \
25374bfb	197	"usbtty=cdc_acm\0" \
a33e3c79	198	"bootfile=uImage\0" \
102ce9ea NM	199	"ramdisk=ramdisk.gz\0" \
	200	"bootdir=/boot\0" \
	201	"bootpart=0:2\0" \
27b8c8f2	202	"console=ttyO2,115200n8\0" \
f6e593bb	203	"mpurate=auto\0" \
847b83d0	204	"buddy=none\0" \
c522eac4 JK	205	"optargs=\0" \
c522eac4 JK	206	"camera=none\0" \
13d2cb98	207	"vram=12M\0" \
f4b36ea9	208	"dvimode=640x480MR-16@60\0" \
13d2cb98	209	"defaultdisplay=dvi\0" \
0cd31144	210	"mmcdev=0\0" \
13d2cb98 SS	211	"mmcroot=/dev/mmcblk0p2 rw\0" \
13d2cb98 SS	212	"mmcrootfstype=ext3 rootwait\0" \
3c6e50d7 SS	213	"nandroot=ubi0:rootfs ubi.mtd=4\0" \
3c6e50d7 SS	214	"nandrootfstype=ubifs\0" \
f4b36ea9 JK	215	"ramroot=/dev/ram0 rw ramdisk_size=65536 initrd=0x81000000,64M\0" \
f4b36ea9 JK	216	"ramrootfstype=ext2\0" \
f904cdbb	217	"mmcargs=setenv bootargs console=${console} " \
c522eac4	218	"${optargs} " \
5af32460	219	"mpurate=${mpurate} " \
b1660314	220	"buddy=${buddy} "\
c522eac4	221	"camera=${camera} "\
13d2cb98 SS	222	"vram=${vram} " \
13d2cb98 SS	223	"omapfb.mode=dvi:${dvimode} " \
13d2cb98 SS	224	"omapdss.def_disp=${defaultdisplay} " \
	225	"root=${mmcroot} " \
	226	"rootfstype=${mmcrootfstype}\0" \
f904cdbb	227	"nandargs=setenv bootargs console=${console} " \
c522eac4	228	"${optargs} " \
5af32460	229	"mpurate=${mpurate} " \
b1660314	230	"buddy=${buddy} "\
c522eac4	231	"camera=${camera} "\
13d2cb98 SS	232	"vram=${vram} " \
13d2cb98 SS	233	"omapfb.mode=dvi:${dvimode} " \
13d2cb98 SS	234	"omapdss.def_disp=${defaultdisplay} " \
	235	"root=${nandroot} " \
	236	"rootfstype=${nandrootfstype}\0" \
2ade496f NM	237	"findfdt=" \
	238	"if test $beaglerev = AxBx; then " \
	239	"setenv fdtfile omap3-beagle.dtb; fi; " \
	240	"if test $beaglerev = Cx; then " \
	241	"setenv fdtfile omap3-beagle.dtb; fi; " \
5c9038b6 RN	242	"if test $beaglerev = C4; then " \
5c9038b6 RN	243	"setenv fdtfile omap3-beagle.dtb; fi; " \
2ade496f NM	244	"if test $beaglerev = xMAB; then " \
	245	"setenv fdtfile omap3-beagle-xm.dtb; fi; " \
	246	"if test $beaglerev = xMC; then " \
	247	"setenv fdtfile omap3-beagle-xm.dtb; fi; " \
	248	"if test $fdtfile = undefined; then " \
	249	"echo WARNING: Could not determine device tree to use; fi; \0" \
f835ea71 JK	250	"bootenv=uEnv.txt\0" \
f835ea71 JK	251	"loadbootenv=fatload mmc ${mmcdev} ${loadaddr} ${bootenv}\0" \
cf073e49 AH	252	"importbootenv=echo Importing environment from mmc ...; " \
cf073e49 AH	253	"env import -t $loadaddr $filesize\0" \
f4b36ea9 JK	254	"ramargs=setenv bootargs console=${console} " \
	255	"${optargs} " \
	256	"mpurate=${mpurate} " \
	257	"buddy=${buddy} "\
	258	"vram=${vram} " \
	259	"omapfb.mode=dvi:${dvimode} " \
	260	"omapdss.def_disp=${defaultdisplay} " \
	261	"root=${ramroot} " \
	262	"rootfstype=${ramrootfstype}\0" \
102ce9ea NM	263	"loadramdisk=load mmc ${bootpart} ${rdaddr} ${bootdir}/${ramdisk}\0" \
102ce9ea NM	264	"loadimage=load mmc ${bootpart} ${loadaddr} ${bootdir}/${bootfile}\0" \
2ade496f	265	"loadfdt=load mmc ${bootpart} ${fdtaddr} ${bootdir}/${fdtfile}\0" \
f904cdbb DB	266	"mmcboot=echo Booting from mmc ...; " \
	267	"run mmcargs; " \
	268	"bootm ${loadaddr}\0" \
ea70690d NM	269	"mmcbootz=echo Booting with DT from mmc${mmcdev} ...; " \
	270	"run mmcargs; " \
	271	"bootz ${loadaddr} - ${fdtaddr}\0" \
f904cdbb DB	272	"nandboot=echo Booting from nand ...; " \
	273	"run nandargs; " \
	274	"nand read ${loadaddr} 280000 400000; " \
	275	"bootm ${loadaddr}\0" \
f4b36ea9 JK	276	"ramboot=echo Booting from ramdisk ...; " \
	277	"run ramargs; " \
	278	"bootm ${loadaddr}\0" \
aae58b95 JF	279	"userbutton=if gpio input 173; then run userbutton_xm; " \
	280	"else run userbutton_nonxm; fi;\0" \
	281	"userbutton_xm=gpio input 4;\0" \
	282	"userbutton_nonxm=gpio input 7;\0"
d7aff44a	283	/* "run userbutton" will return 1 (false) if pressed and 0 (true) if not */
f904cdbb	284	#define CONFIG_BOOTCOMMAND \
2ade496f	285	"run findfdt; " \
66968110	286	"mmc dev ${mmcdev}; if mmc rescan; then " \
aae58b95 JF	287	"if run userbutton; then " \
	288	"setenv bootenv uEnv.txt;" \
	289	"else " \
f835ea71 JK	290	"setenv bootenv user.txt;" \
f835ea71 JK	291	"fi;" \
cf073e49 AH	292	"echo SD/MMC found on device ${mmcdev};" \
cf073e49 AH	293	"if run loadbootenv; then " \
f835ea71	294	"echo Loaded environment from ${bootenv};" \
cf073e49 AH	295	"run importbootenv;" \
	296	"fi;" \
	297	"if test -n $uenvcmd; then " \
	298	"echo Running uenvcmd ...;" \
	299	"run uenvcmd;" \
	300	"fi;" \
102ce9ea	301	"if run loadimage; then " \
cf073e49 AH	302	"run mmcboot;" \
	303	"fi;" \
	304	"fi;" \
	305	"run nandboot;" \
ea70690d NM	306	"setenv bootfile zImage;" \
	307	"if run loadimage; then " \
	308	"run loadfdt;" \
	309	"run mmcbootz; " \
	310	"fi; " \
f904cdbb DB	311
	312	#define CONFIG_AUTO_COMPLETE 1
	313	/*
	314	* Miscellaneous configurable options
	315	*/
f904cdbb DB	316	#define CONFIG_SYS_LONGHELP /* undef to save memory */
f904cdbb DB	317	#define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */
1270ec13	318	#define CONFIG_SYS_PROMPT "OMAP3 beagleboard.org # "
f62b1257	319	#define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */
f904cdbb DB	320	/* Print Buffer Size */
	321	#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
	322	sizeof(CONFIG_SYS_PROMPT) + 16)
933d3701	323	#define CONFIG_SYS_MAXARGS 32 /* max number of command args */
f904cdbb DB	324	/* Boot Argument Buffer Size */
	325	#define CONFIG_SYS_BARGSIZE (CONFIG_SYS_CBSIZE)
	326
780a97f8 JK	327	#define CONFIG_SYS_ALT_MEMTEST 1
	328	#define CONFIG_SYS_MEMTEST_START (0x82000000) /* memtest */
	329	/* defaults */
	330	#define CONFIG_SYS_MEMTEST_END (0x87FFFFFF) /* 128MB */
	331	#define CONFIG_SYS_MEMTEST_SCRATCH (0x81000000) /* dummy address */
f904cdbb	332
f904cdbb DB	333	#define CONFIG_SYS_LOAD_ADDR (OMAP34XX_SDRC_CS0) /* default */
	334	/* load address */
	335
	336	/*
d3a513c2 MP	337	* OMAP3 has 12 GP timers, they can be driven by the system clock
	338	* (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK).
	339	* This rate is divided by a local divisor.
f904cdbb	340	*/
f904cdbb	341	#define CONFIG_SYS_TIMERBASE (OMAP34XX_GPT2)
d3a513c2	342	#define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */
f904cdbb	343
f904cdbb DB	344	/*-----------------------------------------------------------------------
	345	* Physical Memory Map
	346	*/
	347	#define CONFIG_NR_DRAM_BANKS 2 /* CS1 may or may not be populated */
	348	#define PHYS_SDRAM_1 OMAP34XX_SDRC_CS0
f904cdbb DB	349	#define PHYS_SDRAM_2 OMAP34XX_SDRC_CS1
f904cdbb DB	350
f904cdbb DB	351	/*-----------------------------------------------------------------------
	352	* FLASH and environment organization
	353	*/
	354
	355	/* ** PISMO SUPPORT * */
	356
	357	/* Configure the PISMO */
	358	#define PISMO1_NAND_SIZE GPMC_SIZE_128M
	359	#define PISMO1_ONEN_SIZE GPMC_SIZE_128M
	360
9c44ddcc	361	#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 2 sectors */
f904cdbb	362
6cbec7b3 LC	363	#if defined(CONFIG_CMD_NAND)
	364	#define CONFIG_SYS_FLASH_BASE PISMO1_NAND_BASE
	365	#endif
f904cdbb DB	366
	367	/* Monitor at start of flash */
	368	#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
	369	#define CONFIG_SYS_ONENAND_BASE ONENAND_MAP
	370
	371	#define CONFIG_ENV_IS_IN_NAND 1
	372	#define ONENAND_ENV_OFFSET 0x260000 /* environment starts here */
	373	#define SMNAND_ENV_OFFSET 0x260000 /* environment starts here */
	374
6cbec7b3 LC	375	#define CONFIG_SYS_ENV_SECT_SIZE (128 << 10) /* 128 KiB */
6cbec7b3 LC	376	#define CONFIG_ENV_OFFSET SMNAND_ENV_OFFSET
f904cdbb DB	377	#define CONFIG_ENV_ADDR SMNAND_ENV_OFFSET
f904cdbb DB	378
561142af	379	#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
31bfcf1c SS	380	#define CONFIG_SYS_INIT_RAM_ADDR 0x4020f800
	381	#define CONFIG_SYS_INIT_RAM_SIZE 0x800
	382	#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \
	383	CONFIG_SYS_INIT_RAM_SIZE - \
	384	GENERATED_GBL_DATA_SIZE)
561142af	385
53736baa DB	386	#define CONFIG_OMAP3_SPI
53736baa DB	387
8e40852f A	388	#define CONFIG_SYS_CACHELINE_SIZE 64
8e40852f A	389
75c57a35 TR	390	/* Defines for SPL */
75c57a35 TR	391	#define CONFIG_SPL
47f7bcae	392	#define CONFIG_SPL_FRAMEWORK
75c57a35 TR	393	#define CONFIG_SPL_NAND_SIMPLE
75c57a35 TR	394	#define CONFIG_SPL_TEXT_BASE 0x40200800
e0820ccc	395	#define CONFIG_SPL_MAX_SIZE (54 * 1024) /* 8 KB for stack */
75c57a35 TR	396	#define CONFIG_SPL_STACK LOW_LEVEL_SRAM_STACK
	397
	398	#define CONFIG_SPL_BSS_START_ADDR 0x80000000
	399	#define CONFIG_SPL_BSS_MAX_SIZE 0x80000 /* 512 KB */
	400
	401	#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x300 /* address 0x60000 */
	402	#define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS 0x200 /* 256 KB */
	403	#define CONFIG_SYS_MMC_SD_FAT_BOOT_PARTITION 1
	404	#define CONFIG_SPL_FAT_LOAD_PAYLOAD_NAME "u-boot.img"
	405
49175c49	406	#define CONFIG_SPL_BOARD_INIT
75c57a35 TR	407	#define CONFIG_SPL_LIBCOMMON_SUPPORT
	408	#define CONFIG_SPL_LIBDISK_SUPPORT
	409	#define CONFIG_SPL_I2C_SUPPORT
	410	#define CONFIG_SPL_LIBGENERIC_SUPPORT
	411	#define CONFIG_SPL_MMC_SUPPORT
	412	#define CONFIG_SPL_FAT_SUPPORT
	413	#define CONFIG_SPL_SERIAL_SUPPORT
	414	#define CONFIG_SPL_NAND_SUPPORT
6f2f01b9 SW	415	#define CONFIG_SPL_NAND_BASE
	416	#define CONFIG_SPL_NAND_DRIVERS
	417	#define CONFIG_SPL_NAND_ECC
16e41c85	418	#define CONFIG_SPL_GPIO_SUPPORT
75c57a35 TR	419	#define CONFIG_SPL_POWER_SUPPORT
	420	#define CONFIG_SPL_OMAP3_ID_NAND
	421	#define CONFIG_SPL_LDSCRIPT "$(CPUDIR)/omap-common/u-boot-spl.lds"
	422
	423	/* NAND boot config */
	424	#define CONFIG_SYS_NAND_5_ADDR_CYCLE
	425	#define CONFIG_SYS_NAND_PAGE_COUNT 64
	426	#define CONFIG_SYS_NAND_PAGE_SIZE 2048
	427	#define CONFIG_SYS_NAND_OOBSIZE 64
	428	#define CONFIG_SYS_NAND_BLOCK_SIZE (128*1024)
	429	#define CONFIG_SYS_NAND_BAD_BLOCK_POS 0
	430	#define CONFIG_SYS_NAND_ECCPOS {2, 3, 4, 5, 6, 7, 8, 9,\
	431	10, 11, 12, 13}
	432	#define CONFIG_SYS_NAND_ECCSIZE 512
	433	#define CONFIG_SYS_NAND_ECCBYTES 3
3f719069	434	#define CONFIG_NAND_OMAP_ECCSCHEME OMAP_ECC_HAM1_CODE_HW
75c57a35 TR	435	#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE
	436	#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x80000
	437
	438	/*
	439	* 1MB into the SDRAM to allow for SPL's bss at the beginning of SDRAM
	440	* 64 bytes before this address should be set aside for u-boot.img's
	441	* header. That is 0x800FFFC0--0x80100000 should not be used for any
	442	* other needs.
	443	*/
	444	#define CONFIG_SYS_TEXT_BASE 0x80100000
	445	#define CONFIG_SYS_SPL_MALLOC_START 0x80208000
	446	#define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000
	447
f904cdbb	448	#endif /* __CONFIG_H */