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a56bd922 1/*
1eaeb58e 2 * (C) Copyright 2003-2004
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3 * MPC Data Limited (http://www.mpc-data.co.uk)
4 * Dave Peverley <dpeverley at mpc-data.co.uk>
5 *
6 * Configuation settings for the TI OMAP Perseus 2 board.
7 *
8 * See file CREDITS for list of people who contributed to this
9 * project.
10 *
11 * This program is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU General Public License as
13 * published by the Free Software Foundation; either version 2 of
14 * the License, or (at your option) any later version.
15 *
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
1eaeb58e 18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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19 * GNU General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, write to the Free Software
23 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
24 * MA 02111-1307 USA
25 */
26
27#ifndef __CONFIG_H
28#define __CONFIG_H
29
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30/* allow to overwrite serial and ethaddr */
31#define CONFIG_ENV_OVERWRITE
32
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33/*
34 * High Level Configuration Options
35 * (easy to change)
36 */
37
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38#define CONFIG_ARM926EJS 1 /* This is an arm926ejs CPU core */
39#define CONFIG_OMAP 1 /* in a TI OMAP core */
40#define CONFIG_OMAP730 1 /* which is in a 730 */
41#define CONFIG_P2_OMAP730 1 /* a Perseus 2 Board */
a56bd922 42
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43/*
44 * Input clock of PLL
45 * The OMAP730 Perseus 2 has 13MHz input clock
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46 */
47
1eaeb58e 48#define CONFIG_SYS_CLK_FREQ 13000000
a56bd922 49
1eaeb58e 50#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */
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51
52#define CONFIG_MISC_INIT_R
53
1eaeb58e 54#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */
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55#define CONFIG_SETUP_MEMORY_TAGS 1
56
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57/*
58 * Size of malloc() pool
59 */
60
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61#define CFG_MALLOC_LEN (CFG_ENV_SIZE + 128*1024)
62#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
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63
64/*
65 * Hardware drivers
66 */
67
68#define CONFIG_DRIVER_LAN91C96
1eaeb58e 69#define CONFIG_LAN91C96_BASE 0x04000300
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70#define CONFIG_LAN91C96_EXT_PHY
71
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72/*
73 * NS16550 Configuration
74 */
75
76#define CFG_NS16550
77#define CFG_NS16550_SERIAL
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78#define CFG_NS16550_REG_SIZE (1)
79#define CFG_NS16550_CLK (48000000) /* can be 12M/32Khz or 48Mhz */
80#define CFG_NS16550_COM1 0xfffb0000 /* uart1, bluetooth uart
81 * on perseus */
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82
83/*
84 * select serial console configuration
85 */
86
1eaeb58e 87#define CONFIG_SERIAL1 1 /* we use SERIAL 1 on OMAP730 Perseus 2 */
a56bd922 88
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89#define CONFIG_CONS_INDEX 1
90#define CONFIG_BAUDRATE 115200
91#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
a56bd922 92
a56bd922 93
1eaeb58e 94/*
a5cb2309 95 * Command line configuration.
a56bd922 96 */
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97#include <config_cmd_default.h>
98
99#define CONFIG_CMD_DHCP
100
101
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102/*
103 * BOOTP options
104 */
105#define CONFIG_BOOTP_SUBNETMASK
106#define CONFIG_BOOTP_GATEWAY
107#define CONFIG_BOOTP_HOSTNAME
108#define CONFIG_BOOTP_BOOTPATH
109
a56bd922 110
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111#include <configs/omap730.h>
112#include <configs/h2_p2_dbg_board.h>
113
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114#define CONFIG_BOOTDELAY 3
115#define CONFIG_BOOTARGS "mem=32M console=ttyS0,115200n8 noinitrd root=/dev/nfs rw ip=bootp"
a56bd922 116
1eaeb58e 117#define CONFIG_LOADADDR 0x10000000
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118
119#define CONFIG_ETHADDR
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120#define CONFIG_NETMASK 255.255.255.0
121#define CONFIG_IPADDR 192.168.0.23
122#define CONFIG_SERVERIP 192.150.0.100
123#define CONFIG_BOOTFILE "uImage" /* File to load */
a56bd922 124
a5cb2309 125#if defined(CONFIG_CMD_KGDB)
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126#define CONFIG_KGDB_BAUDRATE 115200 /* Speed to run kgdb serial port */
127#define CONFIG_KGDB_SER_INDEX 1 /* Which serial port to use */
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128#endif
129
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130/*
131 * Miscellaneous configurable options
132 */
133
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134#define CFG_LONGHELP /* undef to save memory */
135#define CFG_PROMPT "OMAP730 P2 # " /* Monitor Command Prompt */
136#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
a56bd922 137/* Print Buffer Size */
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138#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16)
139#define CFG_MAXARGS 16 /* max number of command args */
140#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
a56bd922 141
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142#define CFG_MEMTEST_START 0x10000000 /* memtest works on */
143#define CFG_MEMTEST_END 0x12000000 /* 32 MB in DRAM */
a56bd922 144
1eaeb58e 145#undef CFG_CLKS_IN_HZ /* everything, incl board info, in Hz */
a56bd922 146
1eaeb58e 147#define CFG_LOAD_ADDR 0x10000000 /* default load address */
a56bd922 148
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149/* The OMAP730 has 3 general purpose MPU timers, they can be driven by
150 * the RefClk (12Mhz) or by DPLL1. This time is further subdivided by a
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151 * local divisor.
152 */
153
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154#define CFG_TIMERBASE 0xFFFEC500 /* use timer 1 */
155#define CFG_PVT 7 /* 2^(pvt+1), divide by 256 */
156#define CFG_HZ ((CONFIG_SYS_CLK_FREQ)/(2 << CFG_PVT))
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157
158/*-----------------------------------------------------------------------
159 * Stack sizes
160 *
161 * The stack sizes are set up in start.S using the settings below
162 */
163
1eaeb58e 164#define CONFIG_STACKSIZE (128*1024) /* regular stack */
a56bd922 165#ifdef CONFIG_USE_IRQ
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166#define CONFIG_STACKSIZE_IRQ (4*1024) /* IRQ stack */
167#define CONFIG_STACKSIZE_FIQ (4*1024) /* FIQ stack */
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168#endif
169
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170/*-----------------------------------------------------------------------
171 * Physical Memory Map
172 */
173
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174#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */
175#define PHYS_SDRAM_1 0x10000000 /* SDRAM Bank #1 */
176#define PHYS_SDRAM_1_SIZE 0x02000000 /* 32 MB */
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177
178#if defined(CONFIG_CS0_BOOT)
1eaeb58e 179#define PHYS_FLASH_1 0x0C000000
a56bd922 180#elif defined(CONFIG_CS3_BOOT)
1eaeb58e 181#define PHYS_FLASH_1 0x00000000
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182#else
183#error Unknown Boot Chip-Select number
184#endif
185
1eaeb58e 186#define CFG_FLASH_BASE PHYS_FLASH_1
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187
188/*-----------------------------------------------------------------------
189 * FLASH and environment organization
190 */
191
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192#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
193#define PHYS_FLASH_SIZE 0x02000000 /* 32MB */
194#define CFG_MAX_FLASH_SECT (259) /* max number of sectors on one chip */
a56bd922 195/* addr of environment */
1eaeb58e 196#define CFG_ENV_ADDR (CFG_FLASH_BASE + 0x020000)
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197
198/* timeout values are in ticks */
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199#define CFG_FLASH_ERASE_TOUT (20*CFG_HZ) /* Timeout for Flash Erase */
200#define CFG_FLASH_WRITE_TOUT (20*CFG_HZ) /* Timeout for Flash Write */
a56bd922 201
5a1aceb0 202#define CONFIG_ENV_IS_IN_FLASH 1
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203#define CFG_ENV_SIZE 0x20000 /* Total Size of Environment Sector */
204#define CFG_ENV_OFFSET 0x20000 /* environment starts here */
a56bd922 205
1eaeb58e 206#endif /* ! __CONFIG_H */