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49f5befa XX |
1 | /* |
2 | * Copyright 2013 Freescale Semiconductor, Inc. | |
3 | * | |
3aab0cd8 | 4 | * SPDX-License-Identifier: GPL-2.0+ |
49f5befa XX |
5 | */ |
6 | ||
7 | /* | |
8 | * QorIQ P1 Tower boards configuration file | |
9 | */ | |
10 | #ifndef __CONFIG_H | |
11 | #define __CONFIG_H | |
12 | ||
13 | #if defined(CONFIG_TWR_P1025) | |
14 | #define CONFIG_BOARDNAME "TWR-P1025" | |
49f5befa XX |
15 | #define CONFIG_PHY_ATHEROS |
16 | #define CONFIG_QE | |
17 | #define CONFIG_SYS_LBC_LBCR 0x00080000 /* Conversion of LBC addr */ | |
18 | #define CONFIG_SYS_LBC_LCRR 0x80000002 /* LB clock ratio reg */ | |
19 | #endif | |
20 | ||
21 | #ifdef CONFIG_SDCARD | |
22 | #define CONFIG_RAMBOOT_SDCARD | |
23 | #define CONFIG_SYS_RAMBOOT | |
24 | #define CONFIG_SYS_EXTRA_ENV_RELOC | |
25 | #define CONFIG_SYS_TEXT_BASE 0x11000000 | |
e222b1f3 | 26 | #define CONFIG_RESET_VECTOR_ADDRESS 0x110bfffc |
49f5befa XX |
27 | #endif |
28 | ||
29 | #ifndef CONFIG_SYS_TEXT_BASE | |
e222b1f3 | 30 | #define CONFIG_SYS_TEXT_BASE 0xeff40000 |
49f5befa XX |
31 | #endif |
32 | ||
33 | #ifndef CONFIG_RESET_VECTOR_ADDRESS | |
34 | #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc | |
35 | #endif | |
36 | ||
37 | #ifndef CONFIG_SYS_MONITOR_BASE | |
38 | #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ | |
39 | #endif | |
40 | ||
49f5befa XX |
41 | #define CONFIG_MP |
42 | ||
b38eaec5 RD |
43 | #define CONFIG_PCIE1 /* PCIE controller 1 (slot 1) */ |
44 | #define CONFIG_PCIE2 /* PCIE controller 2 (slot 2) */ | |
49f5befa XX |
45 | #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ |
46 | #define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */ | |
47 | #define CONFIG_FSL_PCIE_RESET /* need PCIe reset errata */ | |
48 | #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ | |
49 | ||
49f5befa XX |
50 | #define CONFIG_TSEC_ENET /* tsec ethernet support */ |
51 | #define CONFIG_ENV_OVERWRITE | |
52 | ||
49f5befa XX |
53 | #define CONFIG_SATA_SIL3114 |
54 | #define CONFIG_SYS_SATA_MAX_DEVICE 2 | |
55 | #define CONFIG_LIBATA | |
56 | #define CONFIG_LBA48 | |
57 | ||
58 | #ifndef __ASSEMBLY__ | |
59 | extern unsigned long get_board_sys_clk(unsigned long dummy); | |
60 | #endif | |
61 | #define CONFIG_SYS_CLK_FREQ get_board_sys_clk(0) /*sysclk for TWR-P1025 */ | |
62 | ||
63 | #define CONFIG_DDR_CLK_FREQ 66666666 | |
64 | ||
65 | #define CONFIG_HWCONFIG | |
66 | /* | |
67 | * These can be toggled for performance analysis, otherwise use default. | |
68 | */ | |
69 | #define CONFIG_L2_CACHE | |
70 | #define CONFIG_BTB | |
71 | ||
49f5befa XX |
72 | #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */ |
73 | #define CONFIG_SYS_MEMTEST_END 0x1fffffff | |
74 | #define CONFIG_PANIC_HANG /* do not reset board on panic */ | |
75 | ||
76 | #define CONFIG_SYS_CCSRBAR 0xffe00000 | |
77 | #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR | |
78 | ||
79 | /* DDR Setup */ | |
49f5befa XX |
80 | |
81 | #define CONFIG_SYS_SDRAM_SIZE_LAW LAW_SIZE_512M | |
82 | #define CONFIG_CHIP_SELECTS_PER_CTRL 1 | |
83 | ||
84 | #define CONFIG_SYS_SDRAM_SIZE (1u << (CONFIG_SYS_SDRAM_SIZE_LAW - 19)) | |
85 | #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 | |
86 | #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE | |
87 | ||
49f5befa XX |
88 | #define CONFIG_DIMM_SLOTS_PER_CTLR 1 |
89 | ||
90 | /* Default settings for DDR3 */ | |
91 | #define CONFIG_SYS_DDR_CS0_BNDS 0x0000001f | |
92 | #define CONFIG_SYS_DDR_CS0_CONFIG 0x80014202 | |
93 | #define CONFIG_SYS_DDR_CS0_CONFIG_2 0x00000000 | |
94 | #define CONFIG_SYS_DDR_CS1_BNDS 0x00000000 | |
95 | #define CONFIG_SYS_DDR_CS1_CONFIG 0x00000000 | |
96 | #define CONFIG_SYS_DDR_CS1_CONFIG_2 0x00000000 | |
97 | ||
98 | #define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef | |
99 | #define CONFIG_SYS_DDR_INIT_ADDR 0x00000000 | |
100 | #define CONFIG_SYS_DDR_INIT_EXT_ADDR 0x00000000 | |
101 | #define CONFIG_SYS_DDR_MODE_CONTROL 0x00000000 | |
102 | ||
103 | #define CONFIG_SYS_DDR_ZQ_CONTROL 0x89080600 | |
104 | #define CONFIG_SYS_DDR_WRLVL_CONTROL 0x8655a608 | |
105 | #define CONFIG_SYS_DDR_SR_CNTR 0x00000000 | |
106 | #define CONFIG_SYS_DDR_RCW_1 0x00000000 | |
107 | #define CONFIG_SYS_DDR_RCW_2 0x00000000 | |
108 | #define CONFIG_SYS_DDR_CONTROL 0xc70c0000 /* Type = DDR3 */ | |
109 | #define CONFIG_SYS_DDR_CONTROL_2 0x04401050 | |
110 | #define CONFIG_SYS_DDR_TIMING_4 0x00220001 | |
111 | #define CONFIG_SYS_DDR_TIMING_5 0x03402400 | |
112 | ||
113 | #define CONFIG_SYS_DDR_TIMING_3 0x00020000 | |
114 | #define CONFIG_SYS_DDR_TIMING_0 0x00220004 | |
115 | #define CONFIG_SYS_DDR_TIMING_1 0x5c5b6544 | |
116 | #define CONFIG_SYS_DDR_TIMING_2 0x0fa880de | |
117 | #define CONFIG_SYS_DDR_CLK_CTRL 0x03000000 | |
118 | #define CONFIG_SYS_DDR_MODE_1 0x80461320 | |
119 | #define CONFIG_SYS_DDR_MODE_2 0x00008000 | |
120 | #define CONFIG_SYS_DDR_INTERVAL 0x09480000 | |
121 | ||
122 | /* | |
123 | * Memory map | |
124 | * | |
125 | * 0x0000_0000 0x1fff_ffff DDR Up to 512MB cacheable | |
126 | * 0x8000_0000 0xdfff_ffff PCI Express Mem 1.5G non-cacheable(PCIe * 3) | |
127 | * 0xffc0_0000 0xffc3_ffff PCI IO range 256k non-cacheable | |
128 | * | |
129 | * Localbus | |
130 | * 0xe000_0000 0xe002_0000 SSD1289 128K non-cacheable | |
131 | * 0xec00_0000 0xefff_ffff FLASH Up to 64M non-cacheable | |
132 | * | |
133 | * 0xff90_0000 0xff97_ffff L2 SRAM Up to 512K cacheable | |
134 | * 0xffd0_0000 0xffd0_3fff init ram 16K Cacheable | |
135 | * 0xffe0_0000 0xffef_ffff CCSR 1M non-cacheable | |
136 | */ | |
137 | ||
138 | /* | |
139 | * Local Bus Definitions | |
140 | */ | |
141 | #define CONFIG_SYS_MAX_FLASH_SECT 512 /* 64M */ | |
142 | #define CONFIG_SYS_FLASH_BASE 0xec000000 | |
143 | ||
144 | #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE | |
145 | ||
146 | #define CONFIG_FLASH_BR_PRELIM (BR_PHYS_ADDR((CONFIG_SYS_FLASH_BASE_PHYS)) \ | |
147 | | BR_PS_16 | BR_V) | |
148 | ||
149 | #define CONFIG_FLASH_OR_PRELIM 0xfc0000b1 | |
150 | ||
151 | #define CONFIG_SYS_SSD_BASE 0xe0000000 | |
152 | #define CONFIG_SYS_SSD_BASE_PHYS CONFIG_SYS_SSD_BASE | |
153 | #define CONFIG_SSD_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_SSD_BASE_PHYS) | \ | |
154 | BR_PS_16 | BR_V) | |
155 | #define CONFIG_SSD_OR_PRELIM (OR_AM_64KB | OR_GPCM_CSNT | OR_GPCM_XACS | \ | |
156 | OR_GPCM_ACS_DIV2 | OR_GPCM_SCY | \ | |
157 | OR_GPCM_TRLX | OR_GPCM_EHTR | OR_GPCM_EAD) | |
158 | ||
159 | #define CONFIG_SYS_BR2_PRELIM CONFIG_SSD_BR_PRELIM | |
160 | #define CONFIG_SYS_OR2_PRELIM CONFIG_SSD_OR_PRELIM | |
161 | ||
162 | #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS} | |
163 | #define CONFIG_SYS_FLASH_QUIET_TEST | |
164 | #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ | |
165 | ||
166 | #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ | |
167 | ||
168 | #undef CONFIG_SYS_FLASH_CHECKSUM | |
169 | #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ | |
170 | #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ | |
171 | ||
172 | #define CONFIG_FLASH_CFI_DRIVER | |
173 | #define CONFIG_SYS_FLASH_CFI | |
174 | #define CONFIG_SYS_FLASH_EMPTY_INFO | |
175 | #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE | |
176 | ||
177 | #define CONFIG_BOARD_EARLY_INIT_R /* call board_early_init_r function */ | |
178 | ||
179 | #define CONFIG_SYS_INIT_RAM_LOCK | |
180 | #define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 | |
181 | /* Initial L1 address */ | |
182 | #define CONFIG_SYS_INIT_RAM_ADDR_PHYS CONFIG_SYS_INIT_RAM_ADDR | |
183 | #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0 | |
184 | #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS | |
185 | /* Size of used area in RAM */ | |
186 | #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 | |
187 | ||
188 | #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \ | |
189 | GENERATED_GBL_DATA_SIZE) | |
190 | #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET | |
191 | ||
9307cbab | 192 | #define CONFIG_SYS_MONITOR_LEN (768 * 1024) |
49f5befa XX |
193 | #define CONFIG_SYS_MALLOC_LEN (1024 * 1024)/* Reserved for malloc */ |
194 | ||
195 | #define CONFIG_SYS_BR0_PRELIM CONFIG_FLASH_BR_PRELIM /* NOR Base Address */ | |
196 | #define CONFIG_SYS_OR0_PRELIM CONFIG_FLASH_OR_PRELIM /* NOR Options */ | |
197 | ||
198 | /* Serial Port | |
199 | * open - index 2 | |
200 | * shorted - index 1 | |
201 | */ | |
202 | #define CONFIG_CONS_INDEX 1 | |
203 | #undef CONFIG_SERIAL_SOFTWARE_FIFO | |
49f5befa XX |
204 | #define CONFIG_SYS_NS16550_SERIAL |
205 | #define CONFIG_SYS_NS16550_REG_SIZE 1 | |
206 | #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) | |
207 | ||
208 | #define CONFIG_SYS_BAUDRATE_TABLE \ | |
209 | {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} | |
210 | ||
211 | #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500) | |
212 | #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600) | |
213 | ||
49f5befa XX |
214 | /* I2C */ |
215 | #define CONFIG_SYS_I2C | |
216 | #define CONFIG_SYS_I2C_FSL /* Use FSL common I2C driver */ | |
217 | #define CONFIG_SYS_FSL_I2C_SPEED 400000 /* I2C spd and slave address */ | |
218 | #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F | |
219 | #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 | |
220 | #define CONFIG_SYS_I2C_EEPROM_ADDR 0x52 | |
221 | ||
222 | /* | |
223 | * I2C2 EEPROM | |
224 | */ | |
225 | #define CONFIG_SYS_FSL_I2C2_SPEED 400000 /* I2C spd and slave address */ | |
226 | #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F | |
227 | #define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100 | |
228 | ||
229 | #define CONFIG_SYS_I2C_PCA9555_ADDR 0x23 | |
230 | ||
231 | /* enable read and write access to EEPROM */ | |
49f5befa XX |
232 | #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 |
233 | #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 | |
234 | #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5 | |
235 | ||
236 | /* | |
237 | * eSPI - Enhanced SPI | |
238 | */ | |
239 | #define CONFIG_HARD_SPI | |
49f5befa XX |
240 | |
241 | #if defined(CONFIG_PCI) | |
242 | /* | |
243 | * General PCI | |
244 | * Memory space is mapped 1-1, but I/O space must start from 0. | |
245 | */ | |
246 | ||
247 | /* controller 2, direct to uli, tgtid 2, Base address 9000 */ | |
248 | #define CONFIG_SYS_PCIE2_NAME "TWR-ELEV PCIe SLOT" | |
249 | #define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000 | |
250 | #define CONFIG_SYS_PCIE2_MEM_BUS 0xa0000000 | |
251 | #define CONFIG_SYS_PCIE2_MEM_PHYS 0xa0000000 | |
252 | #define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */ | |
253 | #define CONFIG_SYS_PCIE2_IO_VIRT 0xffc10000 | |
254 | #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 | |
255 | #define CONFIG_SYS_PCIE2_IO_PHYS 0xffc10000 | |
256 | #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ | |
257 | ||
258 | /* controller 1, tgtid 1, Base address a000 */ | |
259 | #define CONFIG_SYS_PCIE1_NAME "mini PCIe SLOT" | |
260 | #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000 | |
261 | #define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000 | |
262 | #define CONFIG_SYS_PCIE1_MEM_PHYS 0x80000000 | |
263 | #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ | |
264 | #define CONFIG_SYS_PCIE1_IO_VIRT 0xffc00000 | |
265 | #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 | |
266 | #define CONFIG_SYS_PCIE1_IO_PHYS 0xffc00000 | |
267 | #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ | |
268 | ||
49f5befa | 269 | #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ |
49f5befa XX |
270 | #endif /* CONFIG_PCI */ |
271 | ||
272 | #if defined(CONFIG_TSEC_ENET) | |
273 | ||
49f5befa XX |
274 | #define CONFIG_MII /* MII PHY management */ |
275 | #define CONFIG_TSEC1 | |
276 | #define CONFIG_TSEC1_NAME "eTSEC1" | |
277 | #undef CONFIG_TSEC2 | |
278 | #undef CONFIG_TSEC2_NAME | |
279 | #define CONFIG_TSEC3 | |
280 | #define CONFIG_TSEC3_NAME "eTSEC3" | |
281 | ||
282 | #define TSEC1_PHY_ADDR 2 | |
283 | #define TSEC2_PHY_ADDR 0 | |
284 | #define TSEC3_PHY_ADDR 1 | |
285 | ||
286 | #define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) | |
287 | #define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) | |
288 | #define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) | |
289 | ||
290 | #define TSEC1_PHYIDX 0 | |
291 | #define TSEC2_PHYIDX 0 | |
292 | #define TSEC3_PHYIDX 0 | |
293 | ||
294 | #define CONFIG_ETHPRIME "eTSEC1" | |
295 | ||
49f5befa XX |
296 | #define CONFIG_HAS_ETH0 |
297 | #define CONFIG_HAS_ETH1 | |
298 | #undef CONFIG_HAS_ETH2 | |
299 | #endif /* CONFIG_TSEC_ENET */ | |
300 | ||
301 | #ifdef CONFIG_QE | |
302 | /* QE microcode/firmware address */ | |
303 | #define CONFIG_SYS_QE_FMAN_FW_IN_NOR | |
dcf1d774 | 304 | #define CONFIG_SYS_QE_FW_ADDR 0xefec0000 |
49f5befa XX |
305 | #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000 |
306 | #endif /* CONFIG_QE */ | |
307 | ||
308 | #ifdef CONFIG_TWR_P1025 | |
309 | /* | |
310 | * QE UEC ethernet configuration | |
311 | */ | |
312 | #define CONFIG_MIIM_ADDRESS (CONFIG_SYS_CCSRBAR + 0x82120) | |
313 | ||
314 | #undef CONFIG_UEC_ETH | |
315 | #define CONFIG_PHY_MODE_NEED_CHANGE | |
316 | ||
317 | #define CONFIG_UEC_ETH1 /* ETH1 */ | |
318 | #define CONFIG_HAS_ETH0 | |
319 | ||
320 | #ifdef CONFIG_UEC_ETH1 | |
321 | #define CONFIG_SYS_UEC1_UCC_NUM 0 /* UCC1 */ | |
322 | #define CONFIG_SYS_UEC1_RX_CLK QE_CLK12 /* CLK12 for MII */ | |
323 | #define CONFIG_SYS_UEC1_TX_CLK QE_CLK9 /* CLK9 for MII */ | |
324 | #define CONFIG_SYS_UEC1_ETH_TYPE FAST_ETH | |
325 | #define CONFIG_SYS_UEC1_PHY_ADDR 0x18 /* 0x18 for MII */ | |
326 | #define CONFIG_SYS_UEC1_INTERFACE_TYPE PHY_INTERFACE_MODE_MII | |
327 | #define CONFIG_SYS_UEC1_INTERFACE_SPEED 100 | |
328 | #endif /* CONFIG_UEC_ETH1 */ | |
329 | ||
330 | #define CONFIG_UEC_ETH5 /* ETH5 */ | |
331 | #define CONFIG_HAS_ETH1 | |
332 | ||
333 | #ifdef CONFIG_UEC_ETH5 | |
334 | #define CONFIG_SYS_UEC5_UCC_NUM 4 /* UCC5 */ | |
335 | #define CONFIG_SYS_UEC5_RX_CLK QE_CLK_NONE | |
336 | #define CONFIG_SYS_UEC5_TX_CLK QE_CLK13 /* CLK 13 for RMII */ | |
337 | #define CONFIG_SYS_UEC5_ETH_TYPE FAST_ETH | |
338 | #define CONFIG_SYS_UEC5_PHY_ADDR 0x19 /* 0x19 for RMII */ | |
339 | #define CONFIG_SYS_UEC5_INTERFACE_TYPE PHY_INTERFACE_MODE_RMII | |
340 | #define CONFIG_SYS_UEC5_INTERFACE_SPEED 100 | |
341 | #endif /* CONFIG_UEC_ETH5 */ | |
342 | #endif /* CONFIG_TWR-P1025 */ | |
343 | ||
94b383e7 YL |
344 | /* |
345 | * Dynamic MTD Partition support with mtdparts | |
346 | */ | |
347 | #define CONFIG_MTD_DEVICE | |
348 | #define CONFIG_MTD_PARTITIONS | |
94b383e7 | 349 | #define CONFIG_FLASH_CFI_MTD |
94b383e7 | 350 | |
49f5befa XX |
351 | /* |
352 | * Environment | |
353 | */ | |
354 | #ifdef CONFIG_SYS_RAMBOOT | |
355 | #ifdef CONFIG_RAMBOOT_SDCARD | |
49f5befa XX |
356 | #define CONFIG_ENV_SIZE 0x2000 |
357 | #define CONFIG_SYS_MMC_ENV_DEV 0 | |
358 | #else | |
49f5befa XX |
359 | #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000) |
360 | #define CONFIG_ENV_SIZE 0x2000 | |
361 | #endif | |
362 | #else | |
49f5befa | 363 | #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) |
49f5befa XX |
364 | #define CONFIG_ENV_SIZE 0x2000 |
365 | #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ | |
366 | #endif | |
367 | ||
368 | #define CONFIG_LOADS_ECHO /* echo on for serial download */ | |
369 | #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */ | |
370 | ||
49f5befa XX |
371 | /* |
372 | * USB | |
373 | */ | |
374 | #define CONFIG_HAS_FSL_DR_USB | |
375 | ||
376 | #if defined(CONFIG_HAS_FSL_DR_USB) | |
8850c5d5 | 377 | #ifdef CONFIG_USB_EHCI_HCD |
49f5befa XX |
378 | #define CONFIG_EHCI_HCD_INIT_AFTER_RESET |
379 | #define CONFIG_USB_EHCI_FSL | |
49f5befa XX |
380 | #endif |
381 | #endif | |
382 | ||
49f5befa XX |
383 | #ifdef CONFIG_MMC |
384 | #define CONFIG_FSL_ESDHC | |
385 | #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR | |
49f5befa XX |
386 | #endif |
387 | ||
49f5befa XX |
388 | #undef CONFIG_WATCHDOG /* watchdog disabled */ |
389 | ||
390 | /* | |
391 | * Miscellaneous configurable options | |
392 | */ | |
393 | #define CONFIG_SYS_LONGHELP /* undef to save memory */ | |
394 | #define CONFIG_CMDLINE_EDITING /* Command-line editing */ | |
395 | #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ | |
49f5befa XX |
396 | |
397 | /* | |
398 | * For booting Linux, the board info and command line data | |
399 | * have to be in the first 64 MB of memory, since this is | |
400 | * the maximum mapped by the Linux kernel during initialization. | |
401 | */ | |
402 | #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory for Linux*/ | |
403 | #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ | |
404 | ||
405 | /* | |
406 | * Environment Configuration | |
407 | */ | |
408 | #define CONFIG_HOSTNAME unknown | |
409 | #define CONFIG_ROOTPATH "/opt/nfsroot" | |
410 | #define CONFIG_BOOTFILE "uImage" | |
411 | #define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP server */ | |
412 | ||
413 | /* default location for tftp and bootm */ | |
414 | #define CONFIG_LOADADDR 1000000 | |
415 | ||
49f5befa XX |
416 | #define CONFIG_EXTRA_ENV_SETTINGS \ |
417 | "netdev=eth0\0" \ | |
418 | "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ | |
419 | "loadaddr=1000000\0" \ | |
420 | "bootfile=uImage\0" \ | |
421 | "dtbfile=twr-p1025twr.dtb\0" \ | |
422 | "ramdiskfile=rootfs.ext2.gz.uboot\0" \ | |
423 | "qefirmwarefile=fsl_qe_ucode_1021_10_A.bin\0" \ | |
424 | "tftpflash=tftpboot $loadaddr $uboot; " \ | |
425 | "protect off " __stringify(CONFIG_SYS_TEXT_BASE) " +$filesize; " \ | |
426 | "erase " __stringify(CONFIG_SYS_TEXT_BASE) " +$filesize; " \ | |
427 | "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) " $filesize; " \ | |
428 | "protect on " __stringify(CONFIG_SYS_TEXT_BASE) " +$filesize; " \ | |
429 | "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) " $filesize\0" \ | |
430 | "kernelflash=tftpboot $loadaddr $bootfile; " \ | |
431 | "protect off 0xefa80000 +$filesize; " \ | |
432 | "erase 0xefa80000 +$filesize; " \ | |
433 | "cp.b $loadaddr 0xefa80000 $filesize; " \ | |
434 | "protect on 0xefa80000 +$filesize; " \ | |
435 | "cmp.b $loadaddr 0xefa80000 $filesize\0" \ | |
436 | "dtbflash=tftpboot $loadaddr $dtbfile; " \ | |
437 | "protect off 0xefe80000 +$filesize; " \ | |
438 | "erase 0xefe80000 +$filesize; " \ | |
439 | "cp.b $loadaddr 0xefe80000 $filesize; " \ | |
440 | "protect on 0xefe80000 +$filesize; " \ | |
441 | "cmp.b $loadaddr 0xefe80000 $filesize\0" \ | |
442 | "ramdiskflash=tftpboot $loadaddr $ramdiskfile; " \ | |
443 | "protect off 0xeeb80000 +$filesize; " \ | |
444 | "erase 0xeeb80000 +$filesize; " \ | |
445 | "cp.b $loadaddr 0xeeb80000 $filesize; " \ | |
446 | "protect on 0xeeb80000 +$filesize; " \ | |
447 | "cmp.b $loadaddr 0xeeb80000 $filesize\0" \ | |
448 | "qefirmwareflash=tftpboot $loadaddr $qefirmwarefile; " \ | |
449 | "protect off 0xefec0000 +$filesize; " \ | |
450 | "erase 0xefec0000 +$filesize; " \ | |
451 | "cp.b $loadaddr 0xefec0000 $filesize; " \ | |
452 | "protect on 0xefec0000 +$filesize; " \ | |
453 | "cmp.b $loadaddr 0xefec0000 $filesize\0" \ | |
454 | "consoledev=ttyS0\0" \ | |
455 | "ramdiskaddr=2000000\0" \ | |
456 | "ramdiskfile=rootfs.ext2.gz.uboot\0" \ | |
b24a4f62 | 457 | "fdtaddr=1e00000\0" \ |
49f5befa XX |
458 | "bdev=sda1\0" \ |
459 | "norbootaddr=ef080000\0" \ | |
460 | "norfdtaddr=ef040000\0" \ | |
461 | "ramdisk_size=120000\0" \ | |
462 | "usbboot=setenv bootargs root=/dev/sda1 rw rootdelay=5 " \ | |
463 | "console=$consoledev,$baudrate $othbootargs ; bootm 0xefa80000 - 0xefe80000" | |
464 | ||
465 | #define CONFIG_NFSBOOTCOMMAND \ | |
466 | "setenv bootargs root=/dev/nfs rw " \ | |
467 | "nfsroot=$serverip:$rootpath " \ | |
468 | "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ | |
469 | "console=$consoledev,$baudrate $othbootargs;" \ | |
470 | "tftp $loadaddr $bootfile&&" \ | |
471 | "tftp $fdtaddr $fdtfile&&" \ | |
472 | "bootm $loadaddr - $fdtaddr" | |
473 | ||
474 | #define CONFIG_HDBOOT \ | |
475 | "setenv bootargs root=/dev/$bdev rw rootdelay=30 " \ | |
476 | "console=$consoledev,$baudrate $othbootargs;" \ | |
477 | "usb start;" \ | |
478 | "ext2load usb 0:1 $loadaddr /boot/$bootfile;" \ | |
479 | "ext2load usb 0:1 $fdtaddr /boot/$fdtfile;" \ | |
480 | "bootm $loadaddr - $fdtaddr" | |
481 | ||
482 | #define CONFIG_USB_FAT_BOOT \ | |
483 | "setenv bootargs root=/dev/ram rw " \ | |
484 | "console=$consoledev,$baudrate $othbootargs " \ | |
485 | "ramdisk_size=$ramdisk_size;" \ | |
486 | "usb start;" \ | |
487 | "fatload usb 0:2 $loadaddr $bootfile;" \ | |
488 | "fatload usb 0:2 $fdtaddr $fdtfile;" \ | |
489 | "fatload usb 0:2 $ramdiskaddr $ramdiskfile;" \ | |
490 | "bootm $loadaddr $ramdiskaddr $fdtaddr" | |
491 | ||
492 | #define CONFIG_USB_EXT2_BOOT \ | |
493 | "setenv bootargs root=/dev/ram rw " \ | |
494 | "console=$consoledev,$baudrate $othbootargs " \ | |
495 | "ramdisk_size=$ramdisk_size;" \ | |
496 | "usb start;" \ | |
497 | "ext2load usb 0:4 $loadaddr $bootfile;" \ | |
498 | "ext2load usb 0:4 $fdtaddr $fdtfile;" \ | |
499 | "ext2load usb 0:4 $ramdiskaddr $ramdiskfile;" \ | |
500 | "bootm $loadaddr $ramdiskaddr $fdtaddr" | |
501 | ||
502 | #define CONFIG_NORBOOT \ | |
503 | "setenv bootargs root=/dev/mtdblock3 rw " \ | |
504 | "console=$consoledev,$baudrate rootfstype=jffs2 $othbootargs;" \ | |
505 | "bootm $norbootaddr - $norfdtaddr" | |
506 | ||
507 | #define CONFIG_RAMBOOTCOMMAND_TFTP \ | |
508 | "setenv bootargs root=/dev/ram rw " \ | |
509 | "console=$consoledev,$baudrate $othbootargs " \ | |
510 | "ramdisk_size=$ramdisk_size;" \ | |
511 | "tftp $ramdiskaddr $ramdiskfile;" \ | |
512 | "tftp $loadaddr $bootfile;" \ | |
513 | "tftp $fdtaddr $fdtfile;" \ | |
514 | "bootm $loadaddr $ramdiskaddr $fdtaddr" | |
515 | ||
516 | #define CONFIG_RAMBOOTCOMMAND \ | |
517 | "setenv bootargs root=/dev/ram rw " \ | |
518 | "console=$consoledev,$baudrate $othbootargs " \ | |
519 | "ramdisk_size=$ramdisk_size;" \ | |
520 | "bootm 0xefa80000 0xeeb80000 0xefe80000" | |
521 | ||
522 | #define CONFIG_BOOTCOMMAND CONFIG_RAMBOOTCOMMAND | |
523 | ||
524 | #endif /* __CONFIG_H */ |