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931a1d2a AA |
1 | /* |
2 | * Copyright 2013 Freescale Semiconductor, Inc. | |
3 | * | |
4 | * Configuration settings for the phytec PCM-052 SoM. | |
5 | * | |
6 | * SPDX-License-Identifier: GPL-2.0+ | |
7 | */ | |
8 | ||
9 | #ifndef __CONFIG_H | |
10 | #define __CONFIG_H | |
11 | ||
12 | #include <asm/arch/imx-regs.h> | |
13 | ||
931a1d2a AA |
14 | #define CONFIG_SKIP_LOWLEVEL_INIT |
15 | ||
16 | /* Enable passing of ATAGs */ | |
17 | #define CONFIG_CMDLINE_TAG | |
18 | ||
19 | /* Size of malloc() pool */ | |
20 | #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 2 * 1024 * 1024) | |
21 | ||
931a1d2a AA |
22 | /* Allow to overwrite serial and ethaddr */ |
23 | #define CONFIG_ENV_OVERWRITE | |
931a1d2a | 24 | |
931a1d2a | 25 | /* NAND support */ |
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26 | #define CONFIG_SYS_NAND_ONFI_DETECTION |
27 | ||
28 | #ifdef CONFIG_CMD_NAND | |
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29 | #define CONFIG_SYS_MAX_NAND_DEVICE 1 |
30 | #define CONFIG_SYS_NAND_BASE NFC_BASE_ADDR | |
31 | ||
32 | #define CONFIG_JFFS2_NAND | |
33 | ||
931a1d2a | 34 | /* Dynamic MTD partition support */ |
931a1d2a AA |
35 | #define CONFIG_MTD_PARTITIONS |
36 | #define CONFIG_MTD_DEVICE | |
27192d16 | 37 | |
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38 | #endif |
39 | ||
931a1d2a AA |
40 | #define CONFIG_FSL_ESDHC |
41 | #define CONFIG_SYS_FSL_ESDHC_ADDR 0 | |
42 | #define CONFIG_SYS_FSL_ESDHC_NUM 1 | |
43 | ||
44 | /*#define CONFIG_ESDHC_DETECT_USE_EXTERN_IRQ1*/ | |
931a1d2a | 45 | |
931a1d2a AA |
46 | #define CONFIG_FEC_MXC |
47 | #define CONFIG_MII | |
48 | #define IMX_FEC_BASE ENET_BASE_ADDR | |
49 | #define CONFIG_FEC_XCV_TYPE RMII | |
50 | #define CONFIG_FEC_MXC_PHYADDR 0 | |
931a1d2a AA |
51 | |
52 | /* QSPI Configs*/ | |
931a1d2a AA |
53 | |
54 | #ifdef CONFIG_FSL_QSPI | |
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55 | #define FSL_QSPI_FLASH_SIZE (1 << 24) |
56 | #define FSL_QSPI_FLASH_NUM 2 | |
57 | #define CONFIG_SYS_FSL_QSPI_LE | |
58 | #endif | |
59 | ||
60 | /* I2C Configs */ | |
931a1d2a AA |
61 | #define CONFIG_SYS_I2C |
62 | #define CONFIG_SYS_I2C_MXC_I2C3 | |
63 | #define CONFIG_SYS_I2C_MXC | |
64 | ||
65 | /* RTC (actually an RV-4162 but M41T62-compatible) */ | |
931a1d2a AA |
66 | #define CONFIG_RTC_M41T62 |
67 | #define CONFIG_SYS_I2C_RTC_ADDR 0x68 | |
68 | #define CONFIG_SYS_RTC_BUS_NUM 2 | |
69 | ||
70 | /* EEPROM (24FC256) */ | |
931a1d2a AA |
71 | #define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 |
72 | #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 | |
73 | #define CONFIG_SYS_I2C_EEPROM_BUS 2 | |
74 | ||
931a1d2a AA |
75 | |
76 | #define CONFIG_LOADADDR 0x82000000 | |
77 | ||
78 | /* We boot from the gfxRAM area of the OCRAM. */ | |
c0f432c3 SA |
79 | #define CONFIG_SYS_TEXT_BASE 0x3f401000 |
80 | #define CONFIG_BOARD_SIZE_LIMIT 520192 | |
931a1d2a | 81 | |
27192d16 AA |
82 | /* if no target-specific extra environment settings were defined by the |
83 | target, define an empty one */ | |
84 | #ifndef PCM052_EXTRA_ENV_SETTINGS | |
85 | #define PCM052_EXTRA_ENV_SETTINGS | |
86 | #endif | |
87 | ||
88 | /* if no target-specific boot command was defined by the target, | |
89 | define an empty one */ | |
90 | #ifndef PCM052_BOOTCOMMAND | |
91 | #define PCM052_BOOTCOMMAND | |
92 | #endif | |
93 | ||
94 | /* if no target-specific extra environment settings were defined by the | |
95 | target, define an empty one */ | |
96 | #ifndef PCM052_NET_INIT | |
97 | #define PCM052_NET_INIT | |
98 | #endif | |
99 | ||
100 | /* boot command, including the target-defined one if any */ | |
101 | #define CONFIG_BOOTCOMMAND PCM052_BOOTCOMMAND "run bootcmd_nand" | |
102 | ||
103 | /* Extra env settings (including the target-defined ones if any) */ | |
040ef8f5 | 104 | #define CONFIG_EXTRA_ENV_SETTINGS \ |
27192d16 AA |
105 | PCM052_EXTRA_ENV_SETTINGS \ |
106 | "autoload=no\0" \ | |
040ef8f5 AA |
107 | "fdt_high=0xffffffff\0" \ |
108 | "initrd_high=0xffffffff\0" \ | |
ed0c2c0a AA |
109 | "blimg_file=u-boot.vyb\0" \ |
110 | "blimg_addr=0x81000000\0" \ | |
040ef8f5 AA |
111 | "kernel_file=zImage\0" \ |
112 | "kernel_addr=0x82000000\0" \ | |
083e4fd4 | 113 | "fdt_file=zImage.dtb\0" \ |
040ef8f5 AA |
114 | "fdt_addr=0x81000000\0" \ |
115 | "ram_file=uRamdisk\0" \ | |
116 | "ram_addr=0x83000000\0" \ | |
117 | "filesys=rootfs.ubifs\0" \ | |
118 | "sys_addr=0x81000000\0" \ | |
119 | "tftploc=/path/to/tftp/directory/\0" \ | |
120 | "nfs_root=/path/to/nfs/root\0" \ | |
121 | "tftptimeout=1000\0" \ | |
122 | "tftptimeoutcountmax=1000000\0" \ | |
43ede0bc | 123 | "mtdparts=" CONFIG_MTDPARTS_DEFAULT "\0" \ |
a7e5f7f3 AA |
124 | "bootargs_base=setenv bootargs rw " \ |
125 | " mem=" __stringify(CONFIG_PCM052_DDR_SIZE) "M " \ | |
040ef8f5 AA |
126 | "console=ttyLP1,115200n8\0" \ |
127 | "bootargs_sd=setenv bootargs ${bootargs} " \ | |
128 | "root=/dev/mmcblk0p2 rootwait\0" \ | |
931a1d2a | 129 | "bootargs_net=setenv bootargs ${bootargs} root=/dev/nfs ip=dhcp " \ |
040ef8f5 AA |
130 | "nfsroot=${serverip}:${nfs_root},v3,tcp\0" \ |
131 | "bootargs_nand=setenv bootargs ${bootargs} " \ | |
27f7d4f5 | 132 | "ubi.mtd=5 rootfstype=ubifs root=ubi0:rootfs\0" \ |
040ef8f5 AA |
133 | "bootargs_ram=setenv bootargs ${bootargs} " \ |
134 | "root=/dev/ram rw initrd=${ram_addr}\0" \ | |
135 | "bootargs_mtd=setenv bootargs ${bootargs} ${mtdparts}\0" \ | |
136 | "bootcmd_sd=run bootargs_base bootargs_sd bootargs_mtd; " \ | |
137 | "fatload mmc 0:1 ${kernel_addr} ${kernel_file}; " \ | |
138 | "fatload mmc 0:1 ${fdt_addr} ${fdt_file}; " \ | |
139 | "bootz ${kernel_addr} - ${fdt_addr}\0" \ | |
140 | "bootcmd_net=run bootargs_base bootargs_net bootargs_mtd; " \ | |
141 | "tftpboot ${kernel_addr} ${tftpdir}${kernel_file}; " \ | |
142 | "tftpboot ${fdt_addr} ${tftpdir}${fdt_file}; " \ | |
143 | "bootz ${kernel_addr} - ${fdt_addr}\0" \ | |
144 | "bootcmd_nand=run bootargs_base bootargs_nand bootargs_mtd; " \ | |
145 | "nand read ${fdt_addr} dtb; " \ | |
146 | "nand read ${kernel_addr} kernel; " \ | |
147 | "bootz ${kernel_addr} - ${fdt_addr}\0" \ | |
148 | "bootcmd_ram=run bootargs_base bootargs_ram bootargs_mtd; " \ | |
149 | "nand read ${fdt_addr} dtb; " \ | |
150 | "nand read ${kernel_addr} kernel; " \ | |
27f7d4f5 | 151 | "nand read ${ram_addr} root; " \ |
040ef8f5 | 152 | "bootz ${kernel_addr} ${ram_addr} ${fdt_addr}\0" \ |
27192d16 AA |
153 | "update_bootloader_from_tftp=" PCM052_NET_INIT \ |
154 | "if tftp ${blimg_addr} "\ | |
ed0c2c0a AA |
155 | "${tftpdir}${blimg_file}; then " \ |
156 | "mtdparts default; " \ | |
040ef8f5 | 157 | "nand erase.part bootloader; " \ |
ed0c2c0a | 158 | "nand write ${blimg_addr} bootloader ${filesize}; fi\0" \ |
040ef8f5 AA |
159 | "update_kernel_from_sd=if fatload mmc 0:2 ${kernel_addr} " \ |
160 | "${kernel_file}; " \ | |
161 | "then mtdparts default; " \ | |
162 | "nand erase.part kernel; " \ | |
163 | "nand write ${kernel_addr} kernel ${filesize}; " \ | |
164 | "if fatload mmc 0:2 ${fdt_addr} ${fdt_file}; then " \ | |
165 | "nand erase.part dtb; " \ | |
166 | "nand write ${fdt_addr} dtb ${filesize}; fi\0" \ | |
27192d16 AA |
167 | "update_kernel_from_tftp=" PCM052_NET_INIT \ |
168 | "if tftp ${fdt_addr} ${tftpdir}${fdt_file}; " \ | |
040ef8f5 AA |
169 | "then setenv fdtsize ${filesize}; " \ |
170 | "if tftp ${kernel_addr} ${tftpdir}${kernel_file}; then " \ | |
171 | "mtdparts default; " \ | |
172 | "nand erase.part dtb; " \ | |
173 | "nand write ${fdt_addr} dtb ${fdtsize}; " \ | |
174 | "nand erase.part kernel; " \ | |
175 | "nand write ${kernel_addr} kernel ${filesize}; fi; fi\0" \ | |
27192d16 AA |
176 | "update_rootfs_from_tftp=" PCM052_NET_INIT \ |
177 | "if tftp ${sys_addr} ${tftpdir}${filesys}; " \ | |
040ef8f5 AA |
178 | "then mtdparts default; " \ |
179 | "nand erase.part root; " \ | |
180 | "ubi part root; " \ | |
181 | "ubi create rootfs; " \ | |
182 | "ubi write ${sys_addr} rootfs ${filesize}; fi\0" \ | |
27192d16 AA |
183 | "update_ramdisk_from_tftp=" PCM052_NET_INIT \ |
184 | "if tftp ${ram_addr} ${tftpdir}${ram_file}; " \ | |
040ef8f5 | 185 | "then mtdparts default; " \ |
27f7d4f5 AA |
186 | "nand erase.part root; " \ |
187 | "nand write ${ram_addr} root ${filesize}; fi\0" | |
931a1d2a | 188 | |
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189 | /* Miscellaneous configurable options */ |
190 | #define CONFIG_SYS_LONGHELP /* undef to save memory */ | |
931a1d2a AA |
191 | #define CONFIG_AUTO_COMPLETE |
192 | #define CONFIG_CMDLINE_EDITING | |
931a1d2a | 193 | |
931a1d2a AA |
194 | #define CONFIG_SYS_MEMTEST_START 0x80010000 |
195 | #define CONFIG_SYS_MEMTEST_END 0x87C00000 | |
196 | ||
197 | #define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR | |
198 | ||
931a1d2a AA |
199 | /* Physical memory map */ |
200 | #define CONFIG_NR_DRAM_BANKS 1 | |
201 | #define PHYS_SDRAM (0x80000000) | |
a7e5f7f3 | 202 | #define PHYS_SDRAM_SIZE (CONFIG_PCM052_DDR_SIZE * 1024 * 1024) |
931a1d2a AA |
203 | |
204 | #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM | |
205 | #define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR | |
206 | #define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE | |
207 | ||
208 | #define CONFIG_SYS_INIT_SP_OFFSET \ | |
209 | (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) | |
210 | #define CONFIG_SYS_INIT_SP_ADDR \ | |
211 | (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) | |
212 | ||
e856bdcf | 213 | /* environment organization */ |
931a1d2a AA |
214 | #ifdef CONFIG_ENV_IS_IN_MMC |
215 | #define CONFIG_ENV_SIZE (8 * 1024) | |
216 | ||
217 | #define CONFIG_ENV_OFFSET (12 * 64 * 1024) | |
218 | #define CONFIG_SYS_MMC_ENV_DEV 0 | |
219 | #endif | |
220 | ||
221 | #ifdef CONFIG_ENV_IS_IN_NAND | |
222 | #define CONFIG_ENV_SECT_SIZE (128 * 1024) | |
223 | #define CONFIG_ENV_SIZE (8 * 1024) | |
040ef8f5 | 224 | #define CONFIG_ENV_OFFSET 0xA0000 |
931a1d2a | 225 | #define CONFIG_ENV_SIZE_REDUND (8 * 1024) |
040ef8f5 | 226 | #define CONFIG_ENV_OFFSET_REDUND 0xC0000 |
931a1d2a AA |
227 | #endif |
228 | ||
931a1d2a | 229 | #endif |