[people/ms/u-boot.git] / include / configs / porter.h

/*
 * include/configs/porter.h
 *     This file is Porter board configuration.
 *
 * Copyright (C) 2015 Renesas Electronics Corporation
 * Copyright (C) 2015 Cogent Embedded, Inc.
 *
 * SPDX-License-Identifier: GPL-2.0
 */

#ifndef __PORTER_H
#define __PORTER_H

#undef DEBUG
#define CONFIG_ARCH_RMOBILE_BOARD_STRING "Porter"

#include "rcar-gen2-common.h"

#if defined(CONFIG_ARCH_RMOBILE_EXTRAM_BOOT)
#define CONFIG_SYS_TEXT_BASE	0x70000000
#else
#define CONFIG_SYS_TEXT_BASE	0xE6304000
#endif

#if defined(CONFIG_ARCH_RMOBILE_EXTRAM_BOOT)
#define CONFIG_SYS_INIT_SP_ADDR		0x7003FFFC
#else
#define CONFIG_SYS_INIT_SP_ADDR		0xE633fffC
#endif
#define STACK_AREA_SIZE			0xC000
#define LOW_LEVEL_MERAM_STACK \
		(CONFIG_SYS_INIT_SP_ADDR + STACK_AREA_SIZE - 4)

/* MEMORY */
#define RCAR_GEN2_SDRAM_BASE		0x40000000
#define RCAR_GEN2_SDRAM_SIZE		(2048u * 1024 * 1024)
#define RCAR_GEN2_UBOOT_SDRAM_SIZE	(1024u * 1024 * 1024)

/* SCIF */

/* FLASH */
#define CONFIG_SPI
#define CONFIG_SH_QSPI
#define CONFIG_SPI_FLASH_QUAD

/* SH Ether */
#define CONFIG_SH_ETHER_USE_PORT	0
#define CONFIG_SH_ETHER_PHY_ADDR	0x1
#define CONFIG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_RMII
#define CONFIG_SH_ETHER_CACHE_WRITEBACK
#define CONFIG_SH_ETHER_CACHE_INVALIDATE
#define CONFIG_SH_ETHER_ALIGNE_SIZE	64
#define CONFIG_BITBANGMII
#define CONFIG_BITBANGMII_MULTI

/* Board Clock */
#define RMOBILE_XTAL_CLK	20000000u
#define CONFIG_SYS_CLK_FREQ	RMOBILE_XTAL_CLK
#define CONFIG_SH_TMU_CLK_FREQ	(CONFIG_SYS_CLK_FREQ / 2)
#define CONFIG_PLL1_CLK_FREQ	(CONFIG_SYS_CLK_FREQ * 156 / 2)
#define CONFIG_P_CLK_FREQ	(CONFIG_PLL1_CLK_FREQ / 24)

#define CONFIG_SYS_TMU_CLK_DIV	4

/* i2c */
#define CONFIG_SYS_I2C
#define CONFIG_SYS_I2C_SH
#define CONFIG_SYS_I2C_SLAVE		0x7F
#define CONFIG_SYS_I2C_SH_NUM_CONTROLLERS	3
#define CONFIG_SYS_I2C_SH_SPEED0	400000
#define CONFIG_SYS_I2C_SH_SPEED1	400000
#define CONFIG_SYS_I2C_SH_SPEED2	400000
#define CONFIG_SH_I2C_DATA_HIGH		4
#define CONFIG_SH_I2C_DATA_LOW		5
#define CONFIG_SH_I2C_CLOCK		10000000

#define CONFIG_SYS_I2C_POWERIC_ADDR	0x58 /* da9063 */

/* USB */
#define CONFIG_USB_EHCI_RMOBILE
#define CONFIG_USB_MAX_CONTROLLER_COUNT	2

/* SD */
#define CONFIG_SH_SDHI_FREQ	97500000

/* Module stop status bits */
/* INTC-RT */
#define CONFIG_SMSTP0_ENA	0x00400000
/* MSIF */
#define CONFIG_SMSTP2_ENA	0x00002000
/* INTC-SYS, IRQC */
#define CONFIG_SMSTP4_ENA	0x00000180
/* SCIF0 */
#define CONFIG_SMSTP7_ENA	0x00200000

#endif /* __PORTER_H */
Commit	Line	Data
60c0467a VB	1	/*
	2	* include/configs/porter.h
	3	* This file is Porter board configuration.
	4	*
	5	* Copyright (C) 2015 Renesas Electronics Corporation
	6	* Copyright (C) 2015 Cogent Embedded, Inc.
	7	*
	8	* SPDX-License-Identifier: GPL-2.0
	9	*/
	10
	11	#ifndef __PORTER_H
	12	#define __PORTER_H
	13
	14	#undef DEBUG
1cc95f6e	15	#define CONFIG_ARCH_RMOBILE_BOARD_STRING "Porter"
60c0467a VB	16
	17	#include "rcar-gen2-common.h"
	18
1cc95f6e	19	#if defined(CONFIG_ARCH_RMOBILE_EXTRAM_BOOT)
60c0467a VB	20	#define CONFIG_SYS_TEXT_BASE 0x70000000
	21	#else
	22	#define CONFIG_SYS_TEXT_BASE 0xE6304000
	23	#endif
	24
1cc95f6e	25	#if defined(CONFIG_ARCH_RMOBILE_EXTRAM_BOOT)
60c0467a VB	26	#define CONFIG_SYS_INIT_SP_ADDR 0x7003FFFC
	27	#else
	28	#define CONFIG_SYS_INIT_SP_ADDR 0xE633fffC
	29	#endif
	30	#define STACK_AREA_SIZE 0xC000
	31	#define LOW_LEVEL_MERAM_STACK \
	32	(CONFIG_SYS_INIT_SP_ADDR + STACK_AREA_SIZE - 4)
	33
	34	/* MEMORY */
	35	#define RCAR_GEN2_SDRAM_BASE 0x40000000
	36	#define RCAR_GEN2_SDRAM_SIZE (2048u * 1024 * 1024)
	37	#define RCAR_GEN2_UBOOT_SDRAM_SIZE (1024u * 1024 * 1024)
	38
	39	/* SCIF */
60c0467a VB	40
	41	/* FLASH */
	42	#define CONFIG_SPI
60c0467a	43	#define CONFIG_SH_QSPI
60c0467a	44	#define CONFIG_SPI_FLASH_QUAD
60c0467a VB	45
60c0467a VB	46	/* SH Ether */
60c0467a VB	47	#define CONFIG_SH_ETHER_USE_PORT 0
	48	#define CONFIG_SH_ETHER_PHY_ADDR 0x1
	49	#define CONFIG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_RMII
	50	#define CONFIG_SH_ETHER_CACHE_WRITEBACK
	51	#define CONFIG_SH_ETHER_CACHE_INVALIDATE
	52	#define CONFIG_SH_ETHER_ALIGNE_SIZE 64
60c0467a VB	53	#define CONFIG_BITBANGMII
	54	#define CONFIG_BITBANGMII_MULTI
	55
	56	/* Board Clock */
	57	#define RMOBILE_XTAL_CLK 20000000u
	58	#define CONFIG_SYS_CLK_FREQ RMOBILE_XTAL_CLK
	59	#define CONFIG_SH_TMU_CLK_FREQ (CONFIG_SYS_CLK_FREQ / 2)
	60	#define CONFIG_PLL1_CLK_FREQ (CONFIG_SYS_CLK_FREQ * 156 / 2)
	61	#define CONFIG_P_CLK_FREQ (CONFIG_PLL1_CLK_FREQ / 24)
	62
	63	#define CONFIG_SYS_TMU_CLK_DIV 4
	64
	65	/* i2c */
60c0467a VB	66	#define CONFIG_SYS_I2C
	67	#define CONFIG_SYS_I2C_SH
	68	#define CONFIG_SYS_I2C_SLAVE 0x7F
	69	#define CONFIG_SYS_I2C_SH_NUM_CONTROLLERS 3
	70	#define CONFIG_SYS_I2C_SH_SPEED0 400000
	71	#define CONFIG_SYS_I2C_SH_SPEED1 400000
	72	#define CONFIG_SYS_I2C_SH_SPEED2 400000
	73	#define CONFIG_SH_I2C_DATA_HIGH 4
	74	#define CONFIG_SH_I2C_DATA_LOW 5
	75	#define CONFIG_SH_I2C_CLOCK 10000000
	76
	77	#define CONFIG_SYS_I2C_POWERIC_ADDR 0x58 /* da9063 */
	78
	79	/* USB */
60c0467a VB	80	#define CONFIG_USB_EHCI_RMOBILE
60c0467a VB	81	#define CONFIG_USB_MAX_CONTROLLER_COUNT 2
60c0467a VB	82
60c0467a VB	83	/* SD */
60c0467a VB	84	#define CONFIG_SH_SDHI_FREQ 97500000
	85
	86	/* Module stop status bits */
	87	/* INTC-RT */
	88	#define CONFIG_SMSTP0_ENA 0x00400000
	89	/* MSIF */
	90	#define CONFIG_SMSTP2_ENA 0x00002000
	91	/* INTC-SYS, IRQC */
	92	#define CONFIG_SMSTP4_ENA 0x00000180
	93	/* SCIF0 */
	94	#define CONFIG_SMSTP7_ENA 0x00200000
	95
	96	#endif /* __PORTER_H */