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fe8c2806 WD |
1 | /* |
2 | * (C) Copyright 2000 | |
3 | * Murray Jensen <Murray.Jensen@cmst.csiro.au> | |
4 | * | |
5 | * (C) Copyright 2000 | |
6 | * Sysgo Real-Time Solutions, GmbH <www.elinos.com> | |
7 | * Marius Groeger <mgroeger@sysgo.de> | |
8 | * | |
9 | * (C) Copyright 2001 | |
10 | * Advent Networks, Inc. <http://www.adventnetworks.com> | |
11 | * Jay Monkman <jtm@smoothsmoothie.com> | |
12 | * | |
13 | * Configuation settings for the WindRiver PPMC8260 board. | |
14 | * | |
1a459660 | 15 | * SPDX-License-Identifier: GPL-2.0+ |
fe8c2806 WD |
16 | */ |
17 | ||
18 | #ifndef __CONFIG_H | |
19 | #define __CONFIG_H | |
20 | ||
2ae18241 WD |
21 | #define CONFIG_SYS_TEXT_BASE 0xfe000000 |
22 | ||
fe8c2806 WD |
23 | /***************************************************************************** |
24 | * | |
25 | * These settings must match the way _your_ board is set up | |
26 | * | |
27 | *****************************************************************************/ | |
28 | ||
29 | /* What is the oscillator's (UX2) frequency in Hz? */ | |
30 | #define CONFIG_8260_CLKIN (66 * 1000 * 1000) | |
31 | ||
32 | /*----------------------------------------------------------------------- | |
33 | * MODCK_H & MODCLK[1-3] - Ref: Section 9.2 in MPC8206 User Manual | |
34 | *----------------------------------------------------------------------- | |
35 | * What should MODCK_H be? It is dependent on the oscillator | |
36 | * frequency, MODCK[1-3], and desired CPM and core frequencies. | |
37 | * Here are some example values (all frequencies are in MHz): | |
38 | * | |
39 | * MODCK_H MODCK[1-3] Osc CPM Core S2-6 S2-7 S2-8 | |
40 | * ------- ---------- --- --- ---- ----- ----- ----- | |
41 | * 0x2 0x2 33 133 133 Close Open Close | |
42 | * 0x2 0x3 33 133 166 Close Open Open | |
43 | * 0x2 0x4 33 133 200 Open Close Close | |
44 | * 0x2 0x5 33 133 233 Open Close Open | |
45 | * 0x2 0x6 33 133 266 Open Open Close | |
46 | * | |
47 | * 0x5 0x5 66 133 133 Open Close Open | |
48 | * 0x5 0x6 66 133 166 Open Open Close | |
49 | * 0x5 0x7 66 133 200 Open Open Open | |
50 | * 0x6 0x0 66 133 233 Close Close Close | |
51 | * 0x6 0x1 66 133 266 Close Close Open | |
52 | * 0x6 0x2 66 133 300 Close Open Close | |
53 | */ | |
6d0f6bcf | 54 | #define CONFIG_SYS_PPMC_MODCK_H 0x05 |
fe8c2806 WD |
55 | |
56 | /* Define this if you want to boot from 0x00000100. If you don't define | |
57 | * this, you will need to program the bootloader to 0xfff00000, and | |
58 | * get the hardware reset config words at 0xfe000000. The simplest | |
59 | * way to do that is to program the bootloader at both addresses. | |
60 | * It is suggested that you just let U-Boot live at 0x00000000. | |
61 | */ | |
6d0f6bcf | 62 | #define CONFIG_SYS_PPMC_BOOT_LOW 1 |
fe8c2806 WD |
63 | |
64 | /* What should the base address of the main FLASH be and how big is | |
14d0a02a | 65 | * it (in MBytes)? This must contain CONFIG_SYS_TEXT_BASE from board/ppmc8260/config.mk |
fe8c2806 WD |
66 | * The main FLASH is whichever is connected to *CS0. U-Boot expects |
67 | * this to be the SIMM. | |
68 | */ | |
6d0f6bcf JCPV |
69 | #define CONFIG_SYS_FLASH0_BASE 0xFE000000 |
70 | #define CONFIG_SYS_FLASH0_SIZE 16 | |
fe8c2806 WD |
71 | |
72 | /* What should be the base address of the first SDRAM DIMM and how big is | |
73 | * it (in Mbytes)? | |
74 | */ | |
6d0f6bcf JCPV |
75 | #define CONFIG_SYS_SDRAM0_BASE 0x00000000 |
76 | #define CONFIG_SYS_SDRAM0_SIZE 128 | |
fe8c2806 WD |
77 | |
78 | /* What should be the base address of the second SDRAM DIMM and how big is | |
79 | * it (in Mbytes)? | |
80 | */ | |
6d0f6bcf JCPV |
81 | #define CONFIG_SYS_SDRAM1_BASE 0x08000000 |
82 | #define CONFIG_SYS_SDRAM1_SIZE 128 | |
fe8c2806 WD |
83 | |
84 | /* What should be the base address of the on board SDRAM and how big is | |
85 | * it (in Mbytes)? | |
86 | */ | |
6d0f6bcf JCPV |
87 | #define CONFIG_SYS_SDRAM2_BASE 0x38000000 |
88 | #define CONFIG_SYS_SDRAM2_SIZE 16 | |
fe8c2806 WD |
89 | |
90 | /* What should be the base address of the MAILBOX and how big is it | |
91 | * (in Bytes) | |
6d0f6bcf | 92 | * The eeprom lives at CONFIG_SYS_MAILBOX_BASE + 0x80000000 |
fe8c2806 | 93 | */ |
6d0f6bcf JCPV |
94 | #define CONFIG_SYS_MAILBOX_BASE 0x32000000 |
95 | #define CONFIG_SYS_MAILBOX_SIZE 8192 | |
fe8c2806 WD |
96 | |
97 | /* What is the base address of the I/O select lines and how big is it | |
98 | * (In Mbytes)? | |
99 | */ | |
100 | ||
6d0f6bcf JCPV |
101 | #define CONFIG_SYS_IOSELECT_BASE 0xE0000000 |
102 | #define CONFIG_SYS_IOSELECT_SIZE 32 | |
fe8c2806 WD |
103 | |
104 | ||
105 | /* What should be the base address of the LEDs and switch S0? | |
106 | * If you don't want them enabled, don't define this. | |
107 | */ | |
6d0f6bcf | 108 | #define CONFIG_SYS_LED_BASE 0xF1000000 |
fe8c2806 WD |
109 | |
110 | /* | |
111 | * PPMC8260 with 256 16 MB DIMM: | |
112 | * | |
113 | * 0x0000 0000 Exception Vector code, 8k | |
114 | * : | |
115 | * 0x0000 1FFF | |
116 | * 0x0000 2000 Free for Application Use | |
117 | * : | |
118 | * : | |
119 | * | |
120 | * : | |
121 | * : | |
122 | * 0x0FF5 FF30 Monitor Stack (Growing downward) | |
123 | * Monitor Stack Buffer (0x80) | |
124 | * 0x0FF5 FFB0 Board Info Data | |
125 | * 0x0FF6 0000 Malloc Arena | |
0e8d1586 | 126 | * : CONFIG_ENV_SECT_SIZE, 256k |
6d0f6bcf | 127 | * : CONFIG_SYS_MALLOC_LEN, 128k |
fe8c2806 | 128 | * 0x0FFC 0000 RAM Copy of Monitor Code |
6d0f6bcf JCPV |
129 | * : CONFIG_SYS_MONITOR_LEN, 256k |
130 | * 0x0FFF FFFF [End of RAM], CONFIG_SYS_SDRAM_SIZE - 1 | |
fe8c2806 WD |
131 | */ |
132 | ||
133 | ||
134 | /* | |
135 | * select serial console configuration | |
136 | * | |
137 | * if either CONFIG_CONS_ON_SMC or CONFIG_CONS_ON_SCC is selected, then | |
138 | * CONFIG_CONS_INDEX must be set to the channel number (1-2 for SMC, 1-4 | |
139 | * for SCC). | |
140 | * | |
141 | * if CONFIG_CONS_NONE is defined, then the serial console routines must | |
142 | * defined elsewhere. | |
143 | * The console can be on SMC1 or SMC2 | |
144 | */ | |
145 | #define CONFIG_CONS_ON_SMC 1 /* define if console on SMC */ | |
146 | #undef CONFIG_CONS_ON_SCC /* define if console on SCC */ | |
147 | #undef CONFIG_CONS_NONE /* define if console on neither */ | |
148 | #define CONFIG_CONS_INDEX 1 /* which SMC/SCC channel for console */ | |
149 | ||
150 | /* | |
151 | * select ethernet configuration | |
152 | * | |
153 | * if either CONFIG_ETHER_ON_SCC or CONFIG_ETHER_ON_FCC is selected, then | |
154 | * CONFIG_ETHER_INDEX must be set to the channel number (1-4 for SCC, 1-3 | |
155 | * for FCC) | |
156 | * | |
157 | * if CONFIG_ETHER_NONE is defined, then either the ethernet routines must be | |
639221c7 | 158 | * defined elsewhere (as for the console), or CONFIG_CMD_NET must be unset. |
fe8c2806 WD |
159 | */ |
160 | ||
161 | #undef CONFIG_ETHER_ON_SCC /* define if ethernet on SCC */ | |
162 | #define CONFIG_ETHER_ON_FCC /* define if ethernet on FCC */ | |
163 | #undef CONFIG_ETHER_NONE /* define if ethernet on neither */ | |
164 | #define CONFIG_ETHER_INDEX 2 /* which SCC/FCC channel for ethernet */ | |
165 | #define CONFIG_MII /* MII PHY management */ | |
166 | #define CONFIG_BITBANGMII /* bit-bang MII PHY management */ | |
167 | /* | |
168 | * Port pins used for bit-banged MII communictions (if applicable). | |
169 | */ | |
170 | #define MDIO_PORT 2 /* Port C */ | |
be225442 LCM |
171 | #define MDIO_DECLARE volatile ioport_t *iop = ioport_addr ( \ |
172 | (immap_t *) CONFIG_SYS_IMMR, MDIO_PORT ) | |
173 | #define MDC_DECLARE MDIO_DECLARE | |
174 | ||
fe8c2806 WD |
175 | #define MDIO_ACTIVE (iop->pdir |= 0x00400000) |
176 | #define MDIO_TRISTATE (iop->pdir &= ~0x00400000) | |
177 | #define MDIO_READ ((iop->pdat & 0x00400000) != 0) | |
178 | ||
179 | #define MDIO(bit) if(bit) iop->pdat |= 0x00400000; \ | |
180 | else iop->pdat &= ~0x00400000 | |
181 | ||
182 | #define MDC(bit) if(bit) iop->pdat |= 0x00200000; \ | |
183 | else iop->pdat &= ~0x00200000 | |
184 | ||
185 | #define MIIDELAY udelay(1) | |
186 | ||
187 | ||
188 | /* Define this to reserve an entire FLASH sector (256 KB) for | |
189 | * environment variables. Otherwise, the environment will be | |
190 | * put in the same sector as U-Boot, and changing variables | |
191 | * will erase U-Boot temporarily | |
192 | */ | |
0e8d1586 | 193 | #define CONFIG_ENV_IN_OWN_SECT 1 |
fe8c2806 WD |
194 | |
195 | /* Define to allow the user to overwrite serial and ethaddr */ | |
196 | #define CONFIG_ENV_OVERWRITE | |
197 | ||
198 | /* What should the console's baud rate be? */ | |
199 | #define CONFIG_BAUDRATE 9600 | |
200 | ||
201 | /* Ethernet MAC address */ | |
202 | ||
203 | #define CONFIG_ETHADDR 00:a0:1e:90:2b:00 | |
204 | ||
205 | /* Define this to set the last octet of the ethernet address | |
206 | * from the DS0-DS7 switch and light the leds with the result | |
207 | * The DS0-DS7 switch and the leds are backwards with respect | |
208 | * to each other. DS7 is on the board edge side of both the | |
209 | * led strip and the DS0-DS7 switch. | |
210 | */ | |
211 | #define CONFIG_MISC_INIT_R | |
212 | ||
213 | /* Set to a positive value to delay for running BOOTCOMMAND */ | |
214 | #define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ | |
215 | ||
216 | #if 0 | |
217 | /* Be selective on what keys can delay or stop the autoboot process | |
218 | * To stop use: " " | |
219 | */ | |
220 | # define CONFIG_AUTOBOOT_KEYED | |
c37207d7 WD |
221 | # define CONFIG_AUTOBOOT_PROMPT \ |
222 | "Autobooting in %d seconds, press \" \" to stop\n", bootdelay | |
fe8c2806 WD |
223 | # define CONFIG_AUTOBOOT_STOP_STR " " |
224 | # undef CONFIG_AUTOBOOT_DELAY_STR | |
225 | # define DEBUG_BOOTKEYS 0 | |
226 | #endif | |
227 | ||
228 | /* Define a command string that is automatically executed when no character | |
229 | * is read on the console interface withing "Boot Delay" after reset. | |
230 | */ | |
53677ef1 | 231 | #undef CONFIG_BOOT_ROOT_INITRD /* Use ram disk for the root file system */ |
b79a11cc | 232 | #define CONFIG_BOOT_ROOT_NFS /* Use a NFS mounted root file system */ |
fe8c2806 | 233 | |
42dfe7a1 | 234 | #ifdef CONFIG_BOOT_ROOT_INITRD |
fe8c2806 WD |
235 | #define CONFIG_BOOTCOMMAND \ |
236 | "version;" \ | |
237 | "echo;" \ | |
238 | "bootp;" \ | |
239 | "setenv bootargs root=/dev/ram0 rw " \ | |
fe126d8b | 240 | "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off;" \ |
fe8c2806 WD |
241 | "bootm" |
242 | #endif /* CONFIG_BOOT_ROOT_INITRD */ | |
243 | ||
42dfe7a1 | 244 | #ifdef CONFIG_BOOT_ROOT_NFS |
fe8c2806 WD |
245 | #define CONFIG_BOOTCOMMAND \ |
246 | "version;" \ | |
247 | "echo;" \ | |
248 | "bootp;" \ | |
fe126d8b WD |
249 | "setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \ |
250 | "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off;" \ | |
fe8c2806 WD |
251 | "bootm" |
252 | #endif /* CONFIG_BOOT_ROOT_NFS */ | |
253 | ||
d3b8c1a7 JL |
254 | |
255 | /* | |
256 | * BOOTP options | |
fe8c2806 | 257 | */ |
d3b8c1a7 JL |
258 | #define CONFIG_BOOTP_SUBNETMASK |
259 | #define CONFIG_BOOTP_GATEWAY | |
260 | #define CONFIG_BOOTP_HOSTNAME | |
261 | #define CONFIG_BOOTP_BOOTPATH | |
262 | #define CONFIG_BOOTP_BOOTFILESIZE | |
263 | #define CONFIG_BOOTP_DNS | |
264 | ||
fe8c2806 WD |
265 | |
266 | /* undef this to save memory */ | |
6d0f6bcf | 267 | #define CONFIG_SYS_LONGHELP |
fe8c2806 WD |
268 | |
269 | /* Monitor Command Prompt */ | |
6d0f6bcf | 270 | #define CONFIG_SYS_PROMPT "=> " |
fe8c2806 | 271 | |
26a34560 JL |
272 | |
273 | /* | |
274 | * Command line configuration. | |
275 | */ | |
276 | #include <config_cmd_default.h> | |
277 | ||
278 | #define CONFIG_CMD_ELF | |
279 | #define CONFIG_CMD_ASKENV | |
280 | #define CONFIG_CMD_REGINFO | |
281 | #define CONFIG_CMD_MEMTEST | |
282 | #define CONFIG_CMD_MII | |
283 | #define CONFIG_CMD_IMMAP | |
284 | ||
285 | #undef CONFIG_CMD_KGDB | |
fe8c2806 WD |
286 | |
287 | ||
288 | /* Where do the internal registers live? */ | |
6d0f6bcf | 289 | #define CONFIG_SYS_IMMR 0xf0000000 |
fe8c2806 WD |
290 | |
291 | /***************************************************************************** | |
292 | * | |
293 | * You should not have to modify any of the following settings | |
294 | * | |
295 | *****************************************************************************/ | |
296 | ||
297 | #define CONFIG_MPC8260 1 /* This is an MPC8260 CPU */ | |
298 | #define CONFIG_PPMC8260 1 /* on an Wind River PPMC8260 Board */ | |
9c4c5ae3 | 299 | #define CONFIG_CPM2 1 /* Has a CPM2 */ |
fe8c2806 | 300 | |
fe8c2806 WD |
301 | /* |
302 | * Miscellaneous configurable options | |
303 | */ | |
26a34560 | 304 | #if defined(CONFIG_CMD_KGDB) |
6d0f6bcf | 305 | # define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ |
fe8c2806 | 306 | #else |
6d0f6bcf | 307 | # define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ |
fe8c2806 WD |
308 | #endif |
309 | ||
310 | /* Print Buffer Size */ | |
6d0f6bcf | 311 | #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT)+16) |
fe8c2806 | 312 | |
6d0f6bcf | 313 | #define CONFIG_SYS_MAXARGS 32 /* max number of command args */ |
fe8c2806 | 314 | |
6d0f6bcf | 315 | #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ |
fe8c2806 | 316 | |
6d0f6bcf JCPV |
317 | #define CONFIG_SYS_LOAD_ADDR 0x140000 /* default load address */ |
318 | #define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */ | |
fe8c2806 | 319 | |
6d0f6bcf | 320 | #define CONFIG_SYS_MEMTEST_START 0x2000 /* memtest works from the end of */ |
fe8c2806 WD |
321 | /* the exception vector table */ |
322 | /* to the end of the DRAM */ | |
323 | /* less monitor and malloc area */ | |
6d0f6bcf JCPV |
324 | #define CONFIG_SYS_STACK_USAGE 0x10000 /* Reserve 64k for the stack usage */ |
325 | #define CONFIG_SYS_MEM_END_USAGE ( CONFIG_SYS_MONITOR_LEN \ | |
326 | + CONFIG_SYS_MALLOC_LEN \ | |
0e8d1586 | 327 | + CONFIG_ENV_SECT_SIZE \ |
6d0f6bcf | 328 | + CONFIG_SYS_STACK_USAGE ) |
fe8c2806 | 329 | |
6d0f6bcf JCPV |
330 | #define CONFIG_SYS_MEMTEST_END ( CONFIG_SYS_SDRAM_SIZE * 1024 * 1024 \ |
331 | - CONFIG_SYS_MEM_END_USAGE ) | |
fe8c2806 | 332 | |
fe8c2806 WD |
333 | /* |
334 | * Low Level Configuration Settings | |
335 | * (address mappings, register initial values, etc.) | |
336 | * You should know what you are doing if you make changes here. | |
337 | */ | |
338 | ||
339 | #if defined(CONFIG_ETHER_ON_SCC) && (CONFIG_ETHER_INDEX == 1) | |
340 | /* | |
341 | * Attention: This is board specific | |
342 | * - RX clk is CLK11 | |
343 | * - TX clk is CLK12 | |
344 | */ | |
6d0f6bcf | 345 | #define CONFIG_SYS_CMXSCR_VALUE (CMXSCR_RS1CS_CLK11 |\ |
fe8c2806 WD |
346 | CMXSCR_TS1CS_CLK12) |
347 | ||
348 | #elif defined(CONFIG_ETHER_ON_FCC) && (CONFIG_ETHER_INDEX == 2) | |
349 | /* | |
350 | * Attention: this is board-specific | |
351 | * - Rx-CLK is CLK13 | |
352 | * - Tx-CLK is CLK14 | |
353 | * - Select bus for bd/buffers (see 28-13) | |
354 | * - Enable Full Duplex in FSMR | |
355 | */ | |
d4590da4 MF |
356 | #define CONFIG_SYS_CMXFCR_MASK2 (CMXFCR_FC2|CMXFCR_RF2CS_MSK|CMXFCR_TF2CS_MSK) |
357 | #define CONFIG_SYS_CMXFCR_VALUE2 (CMXFCR_RF2CS_CLK13|CMXFCR_TF2CS_CLK14) | |
6d0f6bcf JCPV |
358 | #define CONFIG_SYS_CPMFCR_RAMTYPE 0 |
359 | #define CONFIG_SYS_FCC_PSMR (FCC_PSMR_FDE | FCC_PSMR_LPB) | |
fe8c2806 WD |
360 | #endif /* CONFIG_ETHER_INDEX */ |
361 | ||
6d0f6bcf JCPV |
362 | #define CONFIG_SYS_FLASH_BASE CONFIG_SYS_FLASH0_BASE |
363 | #define CONFIG_SYS_FLASH_SIZE CONFIG_SYS_FLASH0_SIZE | |
364 | #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_SDRAM0_BASE | |
365 | #define CONFIG_SYS_SDRAM_SIZE (CONFIG_SYS_SDRAM0_SIZE + CONFIG_SYS_SDRAM1_SIZE) | |
fe8c2806 WD |
366 | |
367 | /*----------------------------------------------------------------------- | |
368 | * Hard Reset Configuration Words | |
369 | */ | |
6d0f6bcf JCPV |
370 | #if defined(CONFIG_SYS_PPMC_BOOT_LOW) |
371 | # define CONFIG_SYS_PPMC_HRCW_BOOT_FLAGS (HRCW_CIP | HRCW_BMS) | |
fe8c2806 | 372 | #else |
6d0f6bcf JCPV |
373 | # define CONFIG_SYS_PPMC_HRCW_BOOT_FLAGS (0) |
374 | #endif /* defined(CONFIG_SYS_PPMC_BOOT_LOW) */ | |
fe8c2806 | 375 | |
6d0f6bcf JCPV |
376 | /* get the HRCW ISB field from CONFIG_SYS_IMMR */ |
377 | #define CONFIG_SYS_PPMC_HRCW_IMMR ( ((CONFIG_SYS_IMMR & 0x10000000) >> 10) | \ | |
378 | ((CONFIG_SYS_IMMR & 0x01000000) >> 7) | \ | |
379 | ((CONFIG_SYS_IMMR & 0x00100000) >> 4) ) | |
fe8c2806 | 380 | |
6d0f6bcf | 381 | #define CONFIG_SYS_HRCW_MASTER ( HRCW_EBM | \ |
fe8c2806 WD |
382 | HRCW_BPS11 | \ |
383 | HRCW_L2CPC10 | \ | |
384 | HRCW_DPPC00 | \ | |
6d0f6bcf | 385 | CONFIG_SYS_PPMC_HRCW_IMMR | \ |
fe8c2806 WD |
386 | HRCW_MMR00 | \ |
387 | HRCW_LBPC00 | \ | |
388 | HRCW_APPC10 | \ | |
389 | HRCW_CS10PC00 | \ | |
6d0f6bcf JCPV |
390 | (CONFIG_SYS_PPMC_MODCK_H & HRCW_MODCK_H1111) | \ |
391 | CONFIG_SYS_PPMC_HRCW_BOOT_FLAGS ) | |
fe8c2806 WD |
392 | |
393 | /* no slaves */ | |
6d0f6bcf JCPV |
394 | #define CONFIG_SYS_HRCW_SLAVE1 0 |
395 | #define CONFIG_SYS_HRCW_SLAVE2 0 | |
396 | #define CONFIG_SYS_HRCW_SLAVE3 0 | |
397 | #define CONFIG_SYS_HRCW_SLAVE4 0 | |
398 | #define CONFIG_SYS_HRCW_SLAVE5 0 | |
399 | #define CONFIG_SYS_HRCW_SLAVE6 0 | |
400 | #define CONFIG_SYS_HRCW_SLAVE7 0 | |
fe8c2806 WD |
401 | |
402 | /*----------------------------------------------------------------------- | |
403 | * Definitions for initial stack pointer and data area (in DPRAM) | |
404 | */ | |
6d0f6bcf | 405 | #define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR |
553f0982 | 406 | #define CONFIG_SYS_INIT_RAM_SIZE 0x4000 /* Size of used area in DPRAM */ |
25ddd1fb | 407 | #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) |
6d0f6bcf | 408 | #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET |
fe8c2806 WD |
409 | |
410 | /*----------------------------------------------------------------------- | |
411 | * Start addresses for the final memory configuration | |
412 | * (Set up by the startup code) | |
6d0f6bcf JCPV |
413 | * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 |
414 | * Note also that the logic that sets CONFIG_SYS_RAMBOOT is platform dependent. | |
fe8c2806 | 415 | */ |
6d0f6bcf | 416 | #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH0_BASE |
fe8c2806 | 417 | |
6d0f6bcf JCPV |
418 | #ifndef CONFIG_SYS_MONITOR_BASE |
419 | #define CONFIG_SYS_MONITOR_BASE 0x0ff80000 | |
fe8c2806 WD |
420 | #endif |
421 | ||
6d0f6bcf JCPV |
422 | #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE) |
423 | # define CONFIG_SYS_RAMBOOT | |
fe8c2806 WD |
424 | #endif |
425 | ||
6d0f6bcf JCPV |
426 | #define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 374 kB for Monitor */ |
427 | #define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ | |
fe8c2806 WD |
428 | |
429 | /* | |
430 | * For booting Linux, the board info and command line data | |
431 | * have to be in the first 8 MB of memory, since this is | |
432 | * the maximum mapped by the Linux kernel during initialization. | |
433 | */ | |
6d0f6bcf | 434 | #define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ |
fe8c2806 WD |
435 | |
436 | /*----------------------------------------------------------------------- | |
437 | * FLASH and environment organization | |
438 | */ | |
439 | ||
6d0f6bcf | 440 | #define CONFIG_SYS_FLASH_CFI 1 /* Flash is CFI conformant */ |
00b1883a | 441 | #define CONFIG_FLASH_CFI_DRIVER 1 /* Use the common driver */ |
6d0f6bcf JCPV |
442 | #define CONFIG_SYS_MAX_FLASH_SECT 128 /* max number of sectors on one chip */ |
443 | #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ | |
444 | #define CONFIG_SYS_FLASH_INCREMENT 0 /* there is only one bank */ | |
445 | #define CONFIG_SYS_FLASH_PROTECTION 1 /* use hardware protection */ | |
446 | #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 /* use buffered writes (20x faster) */ | |
fe8c2806 WD |
447 | |
448 | ||
6d0f6bcf | 449 | #ifndef CONFIG_SYS_RAMBOOT |
fe8c2806 | 450 | |
5a1aceb0 | 451 | # define CONFIG_ENV_IS_IN_FLASH 1 |
0e8d1586 | 452 | # ifdef CONFIG_ENV_IN_OWN_SECT |
6d0f6bcf | 453 | # define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + 0x40000) |
0e8d1586 | 454 | # define CONFIG_ENV_SECT_SIZE 0x40000 |
fe8c2806 | 455 | # else |
6d0f6bcf | 456 | # define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_SYS_MONITOR_LEN - CONFIG_ENV_SECT_SIZE) |
0e8d1586 JCPV |
457 | # define CONFIG_ENV_SIZE 0x1000 /* Total Size of Environment Sector */ |
458 | # define CONFIG_ENV_SECT_SIZE 0x40000 /* see README - env sect real size */ | |
459 | # endif /* CONFIG_ENV_IN_OWN_SECT */ | |
fe8c2806 WD |
460 | |
461 | #else | |
5a1aceb0 | 462 | # define CONFIG_ENV_IS_IN_FLASH 1 |
6d0f6bcf | 463 | # define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x40000) |
0e8d1586 JCPV |
464 | #define CONFIG_ENV_SIZE 0x1000 |
465 | # define CONFIG_ENV_SECT_SIZE 0x40000 | |
6d0f6bcf | 466 | #endif /* CONFIG_SYS_RAMBOOT */ |
fe8c2806 WD |
467 | |
468 | /*----------------------------------------------------------------------- | |
469 | * Cache Configuration | |
470 | */ | |
6d0f6bcf | 471 | #define CONFIG_SYS_CACHELINE_SIZE 32 /* For MPC8260 CPU */ |
fe8c2806 | 472 | |
26a34560 | 473 | #if defined(CONFIG_CMD_KGDB) |
6d0f6bcf | 474 | # define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */ |
fe8c2806 WD |
475 | #endif |
476 | ||
477 | /*----------------------------------------------------------------------- | |
478 | * HIDx - Hardware Implementation-dependent Registers 2-11 | |
479 | *----------------------------------------------------------------------- | |
480 | * HID0 also contains cache control - initially enable both caches and | |
481 | * invalidate contents, then the final state leaves only the instruction | |
482 | * cache enabled. Note that Power-On and Hard reset invalidate the caches, | |
483 | * but Soft reset does not. | |
484 | * | |
485 | * HID1 has only read-only information - nothing to set. | |
486 | */ | |
6d0f6bcf | 487 | #define CONFIG_SYS_HID0_INIT (HID0_ICE |\ |
fe8c2806 WD |
488 | HID0_DCE |\ |
489 | HID0_ICFI |\ | |
490 | HID0_DCI |\ | |
491 | HID0_IFEM |\ | |
492 | HID0_ABE) | |
493 | ||
6d0f6bcf | 494 | #define CONFIG_SYS_HID0_FINAL (HID0_ICE |\ |
fe8c2806 WD |
495 | HID0_IFEM |\ |
496 | HID0_ABE |\ | |
497 | HID0_EMCP) | |
6d0f6bcf | 498 | #define CONFIG_SYS_HID2 0 |
fe8c2806 WD |
499 | |
500 | /*----------------------------------------------------------------------- | |
501 | * RMR - Reset Mode Register | |
502 | *----------------------------------------------------------------------- | |
503 | */ | |
6d0f6bcf | 504 | #define CONFIG_SYS_RMR 0 |
fe8c2806 WD |
505 | |
506 | /*----------------------------------------------------------------------- | |
507 | * BCR - Bus Configuration 4-25 | |
508 | *----------------------------------------------------------------------- | |
509 | */ | |
6d0f6bcf | 510 | #define CONFIG_SYS_BCR (BCR_EBM |\ |
fe8c2806 WD |
511 | 0x30000000) |
512 | ||
513 | /*----------------------------------------------------------------------- | |
514 | * SIUMCR - SIU Module Configuration 4-31 | |
515 | * Ref Section 4.3.2.6 page 4-31 | |
516 | *----------------------------------------------------------------------- | |
517 | */ | |
518 | ||
6d0f6bcf | 519 | #define CONFIG_SYS_SIUMCR (SIUMCR_ESE |\ |
fe8c2806 WD |
520 | SIUMCR_DPPC00 |\ |
521 | SIUMCR_L2CPC10 |\ | |
522 | SIUMCR_LBPC00 |\ | |
523 | SIUMCR_APPC10 |\ | |
524 | SIUMCR_CS10PC00 |\ | |
525 | SIUMCR_BCTLC00 |\ | |
526 | SIUMCR_MMR00) | |
527 | ||
528 | ||
529 | /*----------------------------------------------------------------------- | |
530 | * SYPCR - System Protection Control 11-9 | |
531 | * SYPCR can only be written once after reset! | |
532 | *----------------------------------------------------------------------- | |
533 | * Watchdog & Bus Monitor Timer max, 60x Bus Monitor enable | |
534 | */ | |
6d0f6bcf | 535 | #define CONFIG_SYS_SYPCR (SYPCR_SWTC |\ |
fe8c2806 WD |
536 | SYPCR_BMT |\ |
537 | SYPCR_PBME |\ | |
538 | SYPCR_LBME |\ | |
539 | SYPCR_SWRI |\ | |
540 | SYPCR_SWP) | |
541 | ||
542 | /*----------------------------------------------------------------------- | |
543 | * TMCNTSC - Time Counter Status and Control 4-40 | |
544 | *----------------------------------------------------------------------- | |
545 | * Clear once per Second and Alarm Interrupt Status, Set 32KHz timersclk, | |
546 | * and enable Time Counter | |
547 | */ | |
6d0f6bcf | 548 | #define CONFIG_SYS_TMCNTSC (TMCNTSC_SEC |\ |
fe8c2806 WD |
549 | TMCNTSC_ALR |\ |
550 | TMCNTSC_TCF |\ | |
551 | TMCNTSC_TCE) | |
552 | ||
553 | /*----------------------------------------------------------------------- | |
554 | * PISCR - Periodic Interrupt Status and Control 4-42 | |
555 | *----------------------------------------------------------------------- | |
556 | * Clear Periodic Interrupt Status, Set 32KHz timersclk, and enable | |
557 | * Periodic timer | |
558 | */ | |
6d0f6bcf | 559 | #define CONFIG_SYS_PISCR (PISCR_PS |\ |
fe8c2806 WD |
560 | PISCR_PTF |\ |
561 | PISCR_PTE) | |
562 | ||
563 | /*----------------------------------------------------------------------- | |
564 | * SCCR - System Clock Control 9-8 | |
565 | *----------------------------------------------------------------------- | |
566 | */ | |
6d0f6bcf | 567 | #define CONFIG_SYS_SCCR 0 |
fe8c2806 WD |
568 | |
569 | /*----------------------------------------------------------------------- | |
570 | * RCCR - RISC Controller Configuration 13-7 | |
571 | *----------------------------------------------------------------------- | |
572 | */ | |
6d0f6bcf | 573 | #define CONFIG_SYS_RCCR 0 |
fe8c2806 WD |
574 | |
575 | /* | |
576 | * Initialize Memory Controller: | |
577 | * | |
578 | * Bank Bus Machine PortSz Device | |
579 | * ---- --- ------- ------ ------ | |
580 | * 0 60x GPCM 32 bit FLASH (SIMM - 32MB) * | |
581 | * 1 unused | |
582 | * 2 60x SDRAM 64 bit SDRAM (DIMM - 128MB) | |
583 | * 3 60x SDRAM 64 bit SDRAM (DIMM - 128MB) | |
584 | * 4 Local SDRAM 32 bit SDRAM (on board - 16MB) | |
585 | * 5 60x GPCM 8 bit Mailbox/EEPROM (8KB) | |
586 | * 6 60x GPCM 8 bit FLASH (on board - 2MB) * | |
587 | * 7 60x GPCM 8 bit LEDs, switches | |
588 | * | |
589 | * (*) This configuration requires the PPMC8260 be configured | |
590 | * so that *CS0 goes to the FLASH SIMM, and *CS6 goes to | |
591 | * the on board FLASH. In other words, JP24 should have | |
592 | * pins 1 and 2 jumpered and pins 3 and 4 jumpered. | |
593 | * | |
594 | */ | |
595 | ||
596 | /*----------------------------------------------------------------------- | |
597 | * BR0,BR1 - Base Register | |
598 | * Ref: Section 10.3.1 on page 10-14 | |
599 | * OR0,OR1 - Option Register | |
600 | * Ref: Section 10.3.2 on page 10-18 | |
601 | *----------------------------------------------------------------------- | |
602 | */ | |
603 | ||
604 | /* Bank 0,1 - FLASH SIMM | |
605 | * | |
606 | * This expects the FLASH SIMM to be connected to *CS0 | |
607 | * It consists of 4 AM29F080B parts. | |
608 | * | |
609 | * Note: For the 4 MB SIMM, *CS1 is unused. | |
610 | */ | |
611 | ||
612 | /* BR0 is configured as follows: | |
613 | * | |
614 | * - Base address of 0xFE000000 | |
615 | * - 32 bit port size | |
616 | * - Data errors checking is disabled | |
617 | * - Read and write access | |
618 | * - GPCM 60x bus | |
619 | * - Access are handled by the memory controller according to MSEL | |
620 | * - Not used for atomic operations | |
621 | * - No data pipelining is done | |
622 | * - Valid | |
623 | */ | |
6d0f6bcf | 624 | #define CONFIG_SYS_BR0_PRELIM ((CONFIG_SYS_FLASH0_BASE & BRx_BA_MSK) |\ |
fe8c2806 WD |
625 | BRx_PS_32 |\ |
626 | BRx_MS_GPCM_P |\ | |
627 | BRx_V) | |
628 | ||
629 | /* OR0 is configured as follows: | |
630 | * | |
631 | * - 32 MB | |
632 | * - *BCTL0 is asserted upon access to the current memory bank | |
633 | * - *CW / *WE are negated a quarter of a clock earlier | |
634 | * - *CS is output at the same time as the address lines | |
635 | * - Uses a clock cycle length of 5 | |
636 | * - *PSDVAL is generated internally by the memory controller | |
637 | * unless *GTA is asserted earlier externally. | |
638 | * - Relaxed timing is generated by the GPCM for accesses | |
639 | * initiated to this memory region. | |
640 | * - One idle clock is inserted between a read access from the | |
641 | * current bank and the next access. | |
642 | */ | |
6d0f6bcf | 643 | #define CONFIG_SYS_OR0_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH0_SIZE) |\ |
fe8c2806 WD |
644 | ORxG_CSNT |\ |
645 | ORxG_ACS_DIV1 |\ | |
646 | ORxG_SCY_5_CLK |\ | |
647 | ORxG_TRLX |\ | |
648 | ORxG_EHTR) | |
649 | ||
650 | /*----------------------------------------------------------------------- | |
651 | * BR2,BR3 - Base Register | |
652 | * Ref: Section 10.3.1 on page 10-14 | |
653 | * OR2,OR3 - Option Register | |
654 | * Ref: Section 10.3.2 on page 10-16 | |
655 | *----------------------------------------------------------------------- | |
656 | */ | |
657 | ||
658 | /* | |
659 | * Bank 2,3 - 128 MB SDRAM DIMM | |
660 | */ | |
661 | ||
662 | /* With a 128 MB DIMM, the BR2 is configured as follows: | |
663 | * | |
664 | * - Base address of 0x00000000/0x08000000 | |
665 | * - 64 bit port size (60x bus only) | |
666 | * - Data errors checking is disabled | |
667 | * - Read and write access | |
668 | * - SDRAM 60x bus | |
669 | * - Access are handled by the memory controller according to MSEL | |
670 | * - Not used for atomic operations | |
671 | * - No data pipelining is done | |
672 | * - Valid | |
673 | */ | |
6d0f6bcf | 674 | #define CONFIG_SYS_BR2_PRELIM ((CONFIG_SYS_SDRAM0_BASE & BRx_BA_MSK) |\ |
fe8c2806 WD |
675 | BRx_PS_64 |\ |
676 | BRx_MS_SDRAM_P |\ | |
677 | BRx_V) | |
678 | ||
6d0f6bcf | 679 | #define CONFIG_SYS_BR3_PRELIM ((CONFIG_SYS_SDRAM1_BASE & BRx_BA_MSK) |\ |
fe8c2806 WD |
680 | BRx_PS_64 |\ |
681 | BRx_MS_SDRAM_P |\ | |
682 | BRx_V) | |
683 | ||
684 | /* With a 128 MB DIMM, the OR2 is configured as follows: | |
685 | * | |
686 | * - 128 MB | |
687 | * - 4 internal banks per device | |
688 | * - Row start address bit is A8 with PSDMR[PBI] = 0 | |
689 | * - 13 row address lines | |
690 | * - Back-to-back page mode | |
691 | * - Internal bank interleaving within save device enabled | |
692 | */ | |
693 | ||
6d0f6bcf | 694 | #define CONFIG_SYS_OR2_PRELIM (MEG_TO_AM(CONFIG_SYS_SDRAM0_SIZE) |\ |
fe8c2806 WD |
695 | ORxS_BPD_4 |\ |
696 | ORxS_ROWST_PBI0_A7 |\ | |
697 | ORxS_NUMR_13) | |
698 | ||
6d0f6bcf | 699 | #define CONFIG_SYS_OR3_PRELIM (MEG_TO_AM(CONFIG_SYS_SDRAM1_SIZE) |\ |
fe8c2806 WD |
700 | ORxS_BPD_4 |\ |
701 | ORxS_ROWST_PBI0_A7 |\ | |
702 | ORxS_NUMR_13) | |
703 | ||
704 | ||
705 | /*----------------------------------------------------------------------- | |
706 | * PSDMR - 60x Bus SDRAM Mode Register | |
707 | * Ref: Section 10.3.3 on page 10-21 | |
708 | *----------------------------------------------------------------------- | |
709 | */ | |
710 | ||
711 | /* With a 128 MB DIMM, the PSDMR is configured as follows: | |
712 | * | |
713 | * - Page Based Interleaving, | |
714 | * - Refresh Enable, | |
715 | * - Normal Operation | |
716 | * - Address Multiplexing where A5 is output on A14 pin | |
717 | * (A6 on A15, and so on), | |
718 | * - use address pins A13-A15 as bank select, | |
719 | * - A9 is output on SDA10 during an ACTIVATE command, | |
720 | * - earliest timing for ACTIVATE command after REFRESH command is 7 clocks, | |
721 | * - earliest timing for ACTIVATE or REFRESH command after PRECHARGE command | |
722 | * is 3 clocks, | |
723 | * - earliest timing for READ/WRITE command after ACTIVATE command is | |
724 | * 2 clocks, | |
725 | * - earliest timing for PRECHARGE after last data was read is 1 clock, | |
726 | * - earliest timing for PRECHARGE after last data was written is 1 clock, | |
727 | * - External Address Multiplexing enabled | |
728 | * - CAS Latency is 2. | |
729 | */ | |
6d0f6bcf | 730 | #define CONFIG_SYS_PSDMR (PSDMR_RFEN |\ |
fe8c2806 WD |
731 | PSDMR_SDAM_A14_IS_A5 |\ |
732 | PSDMR_BSMA_A13_A15 |\ | |
733 | PSDMR_SDA10_PBI0_A9 |\ | |
734 | PSDMR_RFRC_7_CLK |\ | |
735 | PSDMR_PRETOACT_3W |\ | |
736 | PSDMR_ACTTORW_2W |\ | |
737 | PSDMR_LDOTOPRE_1C |\ | |
738 | PSDMR_WRC_1C |\ | |
739 | PSDMR_EAMUX |\ | |
740 | PSDMR_CL_2) | |
741 | ||
742 | ||
6d0f6bcf JCPV |
743 | #define CONFIG_SYS_PSRT 0x0e |
744 | #define CONFIG_SYS_MPTPR MPTPR_PTP_DIV32 | |
fe8c2806 WD |
745 | |
746 | ||
747 | /*----------------------------------------------------------------------- | |
748 | * BR4 - Base Register | |
749 | * Ref: Section 10.3.1 on page 10-14 | |
750 | * OR4 - Option Register | |
751 | * Ref: Section 10.3.2 on page 10-16 | |
752 | *----------------------------------------------------------------------- | |
753 | */ | |
754 | ||
755 | /* | |
756 | * Bank 4 - On board SDRAM | |
757 | * | |
758 | */ | |
759 | /* With 16 MB of onboard SDRAM BR4 is configured as follows | |
760 | * | |
761 | * - Base address 0x38000000 | |
762 | * - 32 bit port size | |
763 | * - Data error checking disabled | |
764 | * - Read/Write access | |
765 | * - SDRAM local bus | |
766 | * - Not used for atomic operations | |
767 | * - No data pipelining is done | |
768 | * - Valid | |
769 | * | |
770 | */ | |
771 | ||
6d0f6bcf | 772 | #define CONFIG_SYS_BR4_PRELIM ((CONFIG_SYS_SDRAM2_BASE & BRx_BA_MSK) |\ |
fe8c2806 WD |
773 | BRx_PS_32 |\ |
774 | BRx_DECC_NONE |\ | |
775 | BRx_MS_SDRAM_L |\ | |
776 | BRx_V) | |
777 | ||
778 | /* | |
779 | * With 16MB SDRAM, OR4 is configured as follows | |
780 | * - 4 internal banks per device | |
781 | * - Row start address bit is A10 with LSDMR[PBI] = 0 | |
782 | * - 12 row address lines | |
783 | * - Back-to-back page mode | |
784 | * - Internal bank interleaving within save device enabled | |
785 | */ | |
786 | ||
6d0f6bcf | 787 | #define CONFIG_SYS_OR4_PRELIM (MEG_TO_AM(CONFIG_SYS_SDRAM2_SIZE) |\ |
fe8c2806 WD |
788 | ORxS_BPD_4 |\ |
789 | ORxS_ROWST_PBI0_A10 |\ | |
790 | ORxS_NUMR_12) | |
791 | ||
792 | ||
793 | /*----------------------------------------------------------------------- | |
794 | * LSDMR - Local Bus SDRAM Mode Register | |
795 | * Ref: Section 10.3.4 on page 10-24 | |
796 | *----------------------------------------------------------------------- | |
797 | */ | |
798 | ||
799 | /* With a 16 MB onboard SDRAM, the LSDMR is configured as follows: | |
800 | * | |
801 | * - Page Based Interleaving, | |
802 | * - Refresh Enable, | |
803 | * - Normal Operation | |
804 | * - Address Multiplexing where A5 is output on A13 pin | |
805 | * (A6 on A15, and so on), | |
806 | * - use address pins A15-A17 as bank select, | |
807 | * - A11 is output on SDA10 during an ACTIVATE command, | |
808 | * - earliest timing for ACTIVATE command after REFRESH command is 7 clocks, | |
809 | * - earliest timing for ACTIVATE or REFRESH command after PRECHARGE command | |
810 | * is 2 clocks, | |
811 | * - earliest timing for READ/WRITE command after ACTIVATE command is | |
812 | * 2 clocks, | |
813 | * - SDRAM burst length is 8 | |
814 | * - earliest timing for PRECHARGE after last data was read is 1 clock, | |
815 | * - earliest timing for PRECHARGE after last data was written is 1 clock, | |
816 | * - External Address Multiplexing disabled | |
817 | * - CAS Latency is 2. | |
818 | */ | |
6d0f6bcf | 819 | #define CONFIG_SYS_LSDMR (PSDMR_RFEN |\ |
fe8c2806 WD |
820 | PSDMR_SDAM_A13_IS_A5 |\ |
821 | PSDMR_BSMA_A15_A17 |\ | |
822 | PSDMR_SDA10_PBI0_A11 |\ | |
823 | PSDMR_RFRC_7_CLK |\ | |
824 | PSDMR_PRETOACT_2W |\ | |
825 | PSDMR_ACTTORW_2W |\ | |
826 | PSDMR_BL |\ | |
827 | PSDMR_LDOTOPRE_1C |\ | |
828 | PSDMR_WRC_1C |\ | |
829 | PSDMR_CL_2) | |
830 | ||
6d0f6bcf | 831 | #define CONFIG_SYS_LSRT 0x0e |
fe8c2806 WD |
832 | |
833 | /*----------------------------------------------------------------------- | |
834 | * BR5 - Base Register | |
835 | * Ref: Section 10.3.1 on page 10-14 | |
836 | * OR5 - Option Register | |
837 | * Ref: Section 10.3.2 on page 10-16 | |
838 | *----------------------------------------------------------------------- | |
839 | */ | |
840 | ||
841 | /* | |
842 | * Bank 5 EEProm and Mailbox | |
843 | * | |
844 | * The EEPROM and mailbox live on the same chip select. | |
845 | * the eeprom is selected if the MSb of the address is set and the mailbox is | |
846 | * selected if the MSb of the address is clear. | |
847 | * | |
848 | */ | |
849 | ||
850 | /* BR5 is configured as follows: | |
851 | * | |
852 | * - Base address of 0x32000000/0xF2000000 | |
853 | * - 8 bit | |
854 | * - Data error checking disabled | |
855 | * - Read/Write access | |
856 | * - GPCM 60x Bus | |
857 | * - SDRAM local bus | |
858 | * - No data pipelining is done | |
859 | * - Valid | |
860 | */ | |
861 | ||
6d0f6bcf | 862 | #define CONFIG_SYS_BR5_PRELIM ((CONFIG_SYS_MAILBOX_BASE & BRx_BA_MSK) |\ |
fe8c2806 WD |
863 | BRx_PS_8 |\ |
864 | BRx_DECC_NONE |\ | |
865 | BRx_MS_GPCM_P |\ | |
866 | BRx_V) | |
867 | /* OR5 is configured as follows | |
868 | * - buffer control enabled | |
869 | * - chip select negated normally | |
870 | * - CS output 1/2 clock after address | |
871 | * - 15 wait states | |
872 | * - *PSDVAL is generated internally by the memory controller | |
873 | * unless *GTA is asserted earlier externally. | |
874 | * - Relaxed timing is generated by the GPCM for accesses | |
875 | * initiated to this memory region. | |
876 | * - One idle clock is inserted between a read access from the | |
877 | * current bank and the next access. | |
878 | */ | |
879 | ||
6d0f6bcf | 880 | #define CONFIG_SYS_OR5_PRELIM ((P2SZ_TO_AM(CONFIG_SYS_MAILBOX_SIZE) & ~0x80000000) |\ |
fe8c2806 WD |
881 | ORxG_ACS_DIV2 |\ |
882 | ORxG_SCY_15_CLK |\ | |
883 | ORxG_TRLX |\ | |
884 | ORxG_EHTR) | |
885 | ||
886 | /*----------------------------------------------------------------------- | |
887 | * BR6 - Base Register | |
888 | * Ref: Section 10.3.1 on page 10-14 | |
889 | * OR6 - Option Register | |
890 | * Ref: Section 10.3.2 on page 10-18 | |
891 | *----------------------------------------------------------------------- | |
892 | */ | |
893 | ||
894 | /* Bank 6 - I/O select | |
895 | * | |
896 | */ | |
897 | ||
898 | /* BR6 is configured as follows: | |
899 | * | |
900 | * - Base address of 0xE0000000 | |
901 | * - 16 bit port size | |
902 | * - Data errors checking is disabled | |
903 | * - Read and write access | |
904 | * - GPCM 60x bus | |
905 | * - Access are handled by the memory controller according to MSEL | |
906 | * - Not used for atomic operations | |
907 | * - No data pipelining is done | |
908 | * - Valid | |
909 | */ | |
6d0f6bcf | 910 | #define CONFIG_SYS_BR6_PRELIM ((CONFIG_SYS_IOSELECT_BASE & BRx_BA_MSK) |\ |
fe8c2806 WD |
911 | BRx_PS_16 |\ |
912 | BRx_MS_GPCM_P |\ | |
913 | BRx_V) | |
914 | ||
915 | /* OR6 is configured as follows | |
916 | * - buffer control enabled | |
917 | * - chip select negated normally | |
918 | * - CS output 1/2 clock after address | |
919 | * - 15 wait states | |
920 | * - *PSDVAL is generated internally by the memory controller | |
921 | * unless *GTA is asserted earlier externally. | |
922 | * - Relaxed timing is generated by the GPCM for accesses | |
923 | * initiated to this memory region. | |
924 | * - One idle clock is inserted between a read access from the | |
925 | * current bank and the next access. | |
926 | */ | |
927 | ||
6d0f6bcf | 928 | #define CONFIG_SYS_OR6_PRELIM (MEG_TO_AM(CONFIG_SYS_IOSELECT_SIZE) |\ |
fe8c2806 WD |
929 | ORxG_ACS_DIV2 |\ |
930 | ORxG_SCY_15_CLK |\ | |
931 | ORxG_TRLX |\ | |
932 | ORxG_EHTR) | |
933 | ||
934 | ||
935 | /*----------------------------------------------------------------------- | |
936 | * BR7 - Base Register | |
937 | * Ref: Section 10.3.1 on page 10-14 | |
938 | * OR7 - Option Register | |
939 | * Ref: Section 10.3.2 on page 10-18 | |
940 | *----------------------------------------------------------------------- | |
941 | */ | |
942 | ||
943 | /* Bank 7 - LEDs and switches | |
944 | * | |
945 | * LEDs are at 0x00001 (write only) | |
946 | * switches are at 0x00001 (read only) | |
947 | */ | |
6d0f6bcf | 948 | #ifdef CONFIG_SYS_LED_BASE |
fe8c2806 WD |
949 | |
950 | /* BR7 is configured as follows: | |
951 | * | |
952 | * - Base address of 0xA0000000 | |
953 | * - 8 bit port size | |
954 | * - Data errors checking is disabled | |
955 | * - Read and write access | |
956 | * - GPCM 60x bus | |
957 | * - Access are handled by the memory controller according to MSEL | |
958 | * - Not used for atomic operations | |
959 | * - No data pipelining is done | |
960 | * - Valid | |
961 | */ | |
6d0f6bcf | 962 | #define CONFIG_SYS_BR7_PRELIM ((CONFIG_SYS_LED_BASE & BRx_BA_MSK) |\ |
fe8c2806 WD |
963 | BRx_PS_8 |\ |
964 | BRx_DECC_NONE |\ | |
965 | BRx_MS_GPCM_P |\ | |
966 | BRx_V) | |
967 | ||
968 | /* OR7 is configured as follows: | |
969 | * | |
970 | * - 1 byte | |
971 | * - *BCTL0 is asserted upon access to the current memory bank | |
972 | * - *CW / *WE are negated a quarter of a clock earlier | |
973 | * - *CS is output at the same time as the address lines | |
974 | * - Uses a clock cycle length of 15 | |
975 | * - *PSDVAL is generated internally by the memory controller | |
976 | * unless *GTA is asserted earlier externally. | |
977 | * - Relaxed timing is generated by the GPCM for accesses | |
978 | * initiated to this memory region. | |
979 | * - One idle clock is inserted between a read access from the | |
980 | * current bank and the next access. | |
981 | */ | |
6d0f6bcf | 982 | #define CONFIG_SYS_OR7_PRELIM (ORxG_AM_MSK |\ |
fe8c2806 WD |
983 | ORxG_CSNT |\ |
984 | ORxG_ACS_DIV1 |\ | |
985 | ORxG_SCY_15_CLK |\ | |
986 | ORxG_TRLX |\ | |
987 | ORxG_EHTR) | |
6d0f6bcf | 988 | #endif /* CONFIG_SYS_LED_BASE */ |
fe8c2806 | 989 | #endif /* __CONFIG_H */ |