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70a2047f WD |
1 | /* |
2 | * (C) Copyright 2002 | |
3 | * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net | |
4 | * | |
5 | * (C) Copyright 2002 | |
6 | * Sysgo Real-Time Solutions, GmbH <www.elinos.com> | |
7 | * Marius Groeger <mgroeger@sysgo.de> | |
8 | * | |
9 | * Copied from lubbock.h | |
10 | * | |
11 | * (C) Copyright 2004 | |
12 | * BEC Systems <http://bec-systems.com> | |
13 | * Cliff Brake <cliff.brake@gmail.com> | |
14 | * Configuation settings for the Accelent/Vibren PXA255 IDP | |
15 | * | |
16 | * See file CREDITS for list of people who contributed to this | |
17 | * project. | |
18 | * | |
19 | * This program is free software; you can redistribute it and/or | |
20 | * modify it under the terms of the GNU General Public License as | |
21 | * published by the Free Software Foundation; either version 2 of | |
22 | * the License, or (at your option) any later version. | |
23 | * | |
24 | * This program is distributed in the hope that it will be useful, | |
25 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
26 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
27 | * GNU General Public License for more details. | |
28 | * | |
29 | * You should have received a copy of the GNU General Public License | |
30 | * along with this program; if not, write to the Free Software | |
31 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | |
32 | * MA 02111-1307 USA | |
33 | */ | |
34 | ||
35 | #ifndef __CONFIG_H | |
36 | #define __CONFIG_H | |
37 | ||
38 | #include <asm/arch/pxa-regs.h> | |
39 | ||
40 | /* | |
2a4741d9 | 41 | * If we are developing, we might want to start U-Boot from RAM |
70a2047f WD |
42 | * so we MUST NOT initialize critical regs like mem-timing ... |
43 | */ | |
2a4741d9 MZ |
44 | #undef CONFIG_SKIP_LOWLEVEL_INIT /* define for developing */ |
45 | #undef CONFIG_SKIP_RELOCATE_UBOOT /* define for developing */ | |
70a2047f WD |
46 | |
47 | /* | |
48 | * define the following to enable debug blinks. A debug blink function | |
49 | * must be defined in memsetup.S | |
50 | */ | |
51 | #undef DEBUG_BLINK_ENABLE | |
52 | #undef DEBUG_BLINKC_ENABLE | |
53 | ||
54 | /* | |
55 | * High Level Configuration Options | |
56 | * (easy to change) | |
57 | */ | |
58 | #define CONFIG_PXA250 1 /* This is an PXA250 CPU */ | |
59 | ||
60 | #undef CONFIG_LCD | |
61 | #ifdef CONFIG_LCD | |
62 | #define CONFIG_SHARP_LM8V31 | |
63 | #endif | |
64 | ||
65 | #define CONFIG_MMC 1 | |
2a4741d9 | 66 | #define CONFIG_DOS_PARTITION 1 |
70a2047f WD |
67 | #define BOARD_LATE_INIT 1 |
68 | ||
69 | #undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */ | |
70 | ||
71 | /* | |
72 | * Size of malloc() pool | |
73 | */ | |
6d0f6bcf JCPV |
74 | #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 128*1024) |
75 | #define CONFIG_SYS_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */ | |
70a2047f WD |
76 | |
77 | /* | |
78 | * PXA250 IDP memory map information | |
79 | */ | |
80 | ||
81 | #define IDP_CS5_ETH_OFFSET 0x03400000 | |
82 | ||
83 | ||
84 | /* | |
85 | * Hardware drivers | |
86 | */ | |
87 | #define CONFIG_DRIVER_SMC91111 | |
88 | #define CONFIG_SMC91111_BASE (PXA_CS5_PHYS + IDP_CS5_ETH_OFFSET + 0x300) | |
89 | #define CONFIG_SMC_USE_32_BIT 1 | |
90 | /* #define CONFIG_SMC_USE_IOFUNCS */ | |
91 | ||
92 | /* the following has to be set high -- suspect something is wrong with | |
93 | * with the tftp timeout routines. FIXME!!! | |
94 | */ | |
95 | #define CONFIG_NET_RETRY_COUNT 100 | |
96 | ||
97 | /* | |
98 | * select serial console configuration | |
99 | */ | |
100 | #define CONFIG_FFUART 1 /* we use FFUART on LUBBOCK */ | |
101 | ||
102 | /* allow to overwrite serial and ethaddr */ | |
103 | #define CONFIG_ENV_OVERWRITE | |
104 | ||
105 | #define CONFIG_BAUDRATE 115200 | |
106 | ||
70a2047f | 107 | |
079a136c JL |
108 | /* |
109 | * BOOTP options | |
110 | */ | |
111 | #define CONFIG_BOOTP_BOOTFILESIZE | |
112 | #define CONFIG_BOOTP_BOOTPATH | |
113 | #define CONFIG_BOOTP_GATEWAY | |
114 | #define CONFIG_BOOTP_HOSTNAME | |
115 | ||
116 | ||
26a34560 JL |
117 | /* |
118 | * Command line configuration. | |
119 | */ | |
120 | #include <config_cmd_default.h> | |
121 | ||
122 | #define CONFIG_CMD_MMC | |
123 | #define CONFIG_CMD_FAT | |
124 | #define CONFIG_CMD_DHCP | |
125 | ||
70a2047f WD |
126 | #define CONFIG_BOOTDELAY 3 |
127 | #define CONFIG_BOOTCOMMAND "bootm 40000" | |
128 | #define CONFIG_BOOTARGS "root=/dev/mtdblock2 rootfstype=cramfs console=ttyS0,115200" | |
25dbe98a WD |
129 | |
130 | #define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ | |
131 | #define CONFIG_SETUP_MEMORY_TAGS 1 | |
132 | /* #define CONFIG_INITRD_TAG 1 */ | |
70a2047f WD |
133 | |
134 | /* | |
135 | * Current memory map for Vibren supplied Linux images: | |
136 | * | |
137 | * Flash: | |
138 | * 0 - 0x3ffff (size = 0x40000): bootloader | |
139 | * 0x40000 - 0x13ffff (size = 0x100000): kernel | |
140 | * 0x140000 - 0x1f3ffff (size = 0x1e00000): jffs | |
141 | * | |
142 | * RAM: | |
143 | * 0xa0008000 - kernel is loaded | |
144 | * 0xa3000000 - Uboot runs (48MB into RAM) | |
145 | * | |
146 | */ | |
147 | ||
148 | #define CONFIG_EXTRA_ENV_SETTINGS \ | |
149 | "prog_boot_mmc=" \ | |
150 | "mw.b 0xa0000000 0xff 0x40000; " \ | |
151 | "if mmcinit && " \ | |
152 | "fatload mmc 0 0xa0000000 u-boot.bin; " \ | |
153 | "then " \ | |
154 | "protect off 0x0 0x3ffff; " \ | |
155 | "erase 0x0 0x3ffff; " \ | |
156 | "cp.b 0xa0000000 0x0 0x40000; " \ | |
157 | "reset;" \ | |
158 | "fi\0" \ | |
159 | "prog_uzImage_mmc=" \ | |
160 | "mw.b 0xa0000000 0xff 0x100000; " \ | |
161 | "if mmcinit && " \ | |
162 | "fatload mmc 0 0xa0000000 uzImage; " \ | |
163 | "then " \ | |
164 | "protect off 0x40000 0xfffff; " \ | |
165 | "erase 0x40000 0xfffff; " \ | |
166 | "cp.b 0xa0000000 0x40000 0x100000; " \ | |
167 | "fi\0" \ | |
168 | "prog_jffs_mmc=" \ | |
169 | "mw.b 0xa0000000 0xff 0x1e00000; " \ | |
170 | "if mmcinit && " \ | |
171 | "fatload mmc 0 0xa0000000 root.jffs; " \ | |
172 | "then " \ | |
173 | "protect off 0x140000 0x1f3ffff; " \ | |
174 | "erase 0x140000 0x1f3ffff; " \ | |
175 | "cp.b 0xa0000000 0x140000 0x1e00000; " \ | |
176 | "fi\0" \ | |
177 | "boot_mmc=" \ | |
178 | "if mmcinit && " \ | |
179 | "fatload mmc 0 0xa1000000 uzImage && " \ | |
180 | "then " \ | |
181 | "bootm 0xa1000000; " \ | |
182 | "fi\0" \ | |
183 | "prog_boot_net=" \ | |
184 | "mw.b 0xa0000000 0xff 0x100000; " \ | |
185 | "if bootp 0xa0000000 u-boot.bin; " \ | |
186 | "then " \ | |
187 | "protect off 0x0 0x3ffff; " \ | |
188 | "erase 0x0 0x3ffff; " \ | |
189 | "cp.b 0xa0000000 0x0 0x40000; " \ | |
190 | "reset; " \ | |
191 | "fi\0" \ | |
192 | "prog_uzImage_net=" \ | |
193 | "mw.b 0xa0000000 0xff 0x100000; " \ | |
194 | "if bootp 0xa0000000 uzImage; " \ | |
195 | "then " \ | |
196 | "protect off 0x40000 0xfffff; " \ | |
197 | "erase 0x40000 0xfffff; " \ | |
198 | "cp.b 0xa0000000 0x40000 0x100000; " \ | |
199 | "fi\0" \ | |
200 | "prog_jffs_net=" \ | |
201 | "mw.b 0xa0000000 0xff 0x1e00000; " \ | |
202 | "if bootp 0xa0000000 root.jffs; " \ | |
203 | "then " \ | |
204 | "protect off 0x140000 0x1f3ffff; " \ | |
205 | "erase 0x140000 0x1f3ffff; " \ | |
206 | "cp.b 0xa0000000 0x140000 0x1e00000; " \ | |
207 | "fi\0" | |
208 | ||
209 | ||
210 | /* "erase_env=" */ | |
211 | /* "protect off" */ | |
212 | ||
213 | ||
26a34560 | 214 | #if defined(CONFIG_CMD_KGDB) |
70a2047f WD |
215 | #define CONFIG_KGDB_BAUDRATE 115200 /* speed to run kgdb serial port */ |
216 | #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ | |
217 | #endif | |
218 | ||
219 | /* | |
220 | * Miscellaneous configurable options | |
221 | */ | |
6d0f6bcf JCPV |
222 | #define CONFIG_SYS_HUSH_PARSER 1 |
223 | #define CONFIG_SYS_PROMPT_HUSH_PS2 "> " | |
70a2047f | 224 | |
6d0f6bcf JCPV |
225 | #define CONFIG_SYS_LONGHELP /* undef to save memory */ |
226 | #ifdef CONFIG_SYS_HUSH_PARSER | |
227 | #define CONFIG_SYS_PROMPT "$ " /* Monitor Command Prompt */ | |
70a2047f | 228 | #else |
6d0f6bcf | 229 | #define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ |
70a2047f | 230 | #endif |
6d0f6bcf JCPV |
231 | #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ |
232 | #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ | |
233 | #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ | |
234 | #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ | |
235 | #define CONFIG_SYS_DEVICE_NULLDEV 1 | |
70a2047f | 236 | |
6d0f6bcf JCPV |
237 | #define CONFIG_SYS_MEMTEST_START 0xa0400000 /* memtest works on */ |
238 | #define CONFIG_SYS_MEMTEST_END 0xa0800000 /* 4 ... 8 MB in DRAM */ | |
70a2047f | 239 | |
6d0f6bcf | 240 | #undef CONFIG_SYS_CLKS_IN_HZ /* everything, incl board info, in Hz */ |
70a2047f | 241 | |
6d0f6bcf | 242 | #define CONFIG_SYS_LOAD_ADDR 0xa0800000 /* default load address */ |
70a2047f | 243 | |
6d0f6bcf JCPV |
244 | #define CONFIG_SYS_HZ 3686400 /* incrementer freq: 3.6864 MHz */ |
245 | #define CONFIG_SYS_CPUSPEED 0x161 /* set core clock to 400/200/100 MHz */ | |
70a2047f WD |
246 | |
247 | #define RTC 1 /* enable 32KHz osc */ | |
248 | ||
249 | /* valid baudrates */ | |
6d0f6bcf | 250 | #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } |
70a2047f | 251 | |
6d0f6bcf | 252 | #define CONFIG_SYS_MMC_BASE 0xF0000000 |
70a2047f WD |
253 | |
254 | /* | |
255 | * Stack sizes | |
256 | * | |
257 | * The stack sizes are set up in start.S using the settings below | |
258 | */ | |
259 | #define CONFIG_STACKSIZE (128*1024) /* regular stack */ | |
260 | #ifdef CONFIG_USE_IRQ | |
261 | #define CONFIG_STACKSIZE_IRQ (4*1024) /* IRQ stack */ | |
262 | #define CONFIG_STACKSIZE_FIQ (4*1024) /* FIQ stack */ | |
263 | #endif | |
264 | ||
265 | /* | |
266 | * Physical Memory Map | |
267 | */ | |
268 | #define CONFIG_NR_DRAM_BANKS 4 /* we have 1 banks of DRAM */ | |
269 | #define PHYS_SDRAM_1 0xa0000000 /* SDRAM Bank #1 */ | |
270 | #define PHYS_SDRAM_1_SIZE 0x04000000 /* 64 MB */ | |
271 | #define PHYS_SDRAM_2 0xa4000000 /* SDRAM Bank #2 */ | |
272 | #define PHYS_SDRAM_2_SIZE 0x00000000 /* 0 MB */ | |
273 | #define PHYS_SDRAM_3 0xa8000000 /* SDRAM Bank #3 */ | |
274 | #define PHYS_SDRAM_3_SIZE 0x00000000 /* 0 MB */ | |
275 | #define PHYS_SDRAM_4 0xac000000 /* SDRAM Bank #4 */ | |
276 | #define PHYS_SDRAM_4_SIZE 0x00000000 /* 0 MB */ | |
277 | ||
278 | #define PHYS_FLASH_1 0x00000000 /* Flash Bank #1 */ | |
279 | #define PHYS_FLASH_2 0x04000000 /* Flash Bank #2 */ | |
280 | #define PHYS_FLASH_SIZE 0x02000000 /* 32 MB */ | |
281 | #define PHYS_FLASH_BANK_SIZE 0x02000000 /* 32 MB Banks */ | |
282 | #define PHYS_FLASH_SECT_SIZE 0x00040000 /* 256 KB sectors (x2) */ | |
283 | ||
6d0f6bcf JCPV |
284 | #define CONFIG_SYS_DRAM_BASE 0xa0000000 |
285 | #define CONFIG_SYS_DRAM_SIZE 0x04000000 | |
70a2047f | 286 | |
6d0f6bcf | 287 | #define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1 |
70a2047f WD |
288 | |
289 | /* | |
290 | * GPIO settings | |
291 | */ | |
292 | ||
6d0f6bcf JCPV |
293 | #define CONFIG_SYS_GAFR0_L_VAL 0x80001005 |
294 | #define CONFIG_SYS_GAFR0_U_VAL 0xa5128012 | |
295 | #define CONFIG_SYS_GAFR1_L_VAL 0x699a9558 | |
296 | #define CONFIG_SYS_GAFR1_U_VAL 0xaaa5aa6a | |
297 | #define CONFIG_SYS_GAFR2_L_VAL 0xaaaaaaaa | |
298 | #define CONFIG_SYS_GAFR2_U_VAL 0x2 | |
299 | #define CONFIG_SYS_GPCR0_VAL 0x1800400 | |
300 | #define CONFIG_SYS_GPCR1_VAL 0x0 | |
301 | #define CONFIG_SYS_GPCR2_VAL 0x0 | |
302 | #define CONFIG_SYS_GPDR0_VAL 0xc1818440 | |
303 | #define CONFIG_SYS_GPDR1_VAL 0xfcffab82 | |
304 | #define CONFIG_SYS_GPDR2_VAL 0x1ffff | |
305 | #define CONFIG_SYS_GPSR0_VAL 0x8000 | |
306 | #define CONFIG_SYS_GPSR1_VAL 0x3f0002 | |
307 | #define CONFIG_SYS_GPSR2_VAL 0x1c000 | |
308 | ||
309 | #define CONFIG_SYS_PSSR_VAL 0x20 | |
70a2047f WD |
310 | |
311 | /* | |
312 | * Memory settings | |
313 | */ | |
6d0f6bcf JCPV |
314 | #define CONFIG_SYS_MSC0_VAL 0x29DCA4D2 |
315 | #define CONFIG_SYS_MSC1_VAL 0x43AC494C | |
316 | #define CONFIG_SYS_MSC2_VAL 0x39D449D4 | |
317 | #define CONFIG_SYS_MDCNFG_VAL 0x090009C9 | |
318 | #define CONFIG_SYS_MDREFR_VAL 0x0085C017 | |
319 | #define CONFIG_SYS_MDMRS_VAL 0x00220022 | |
70a2047f WD |
320 | |
321 | /* | |
322 | * PCMCIA and CF Interfaces | |
323 | */ | |
6d0f6bcf JCPV |
324 | #define CONFIG_SYS_MECR_VAL 0x00000003 |
325 | #define CONFIG_SYS_MCMEM0_VAL 0x00014405 | |
326 | #define CONFIG_SYS_MCMEM1_VAL 0x00014405 | |
327 | #define CONFIG_SYS_MCATT0_VAL 0x00014405 | |
328 | #define CONFIG_SYS_MCATT1_VAL 0x00014405 | |
329 | #define CONFIG_SYS_MCIO0_VAL 0x00014405 | |
330 | #define CONFIG_SYS_MCIO1_VAL 0x00014405 | |
70a2047f WD |
331 | |
332 | /* | |
333 | * FLASH and environment organization | |
334 | */ | |
6d0f6bcf | 335 | #define CONFIG_SYS_FLASH_CFI |
00b1883a | 336 | #define CONFIG_FLASH_CFI_DRIVER 1 |
70a2047f | 337 | |
6d0f6bcf JCPV |
338 | #define CONFIG_SYS_MONITOR_BASE 0 |
339 | #define CONFIG_SYS_MONITOR_LEN PHYS_FLASH_SECT_SIZE | |
70a2047f | 340 | |
6d0f6bcf JCPV |
341 | #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ |
342 | #define CONFIG_SYS_MAX_FLASH_SECT 128 /* max number of sectors on one chip */ | |
70a2047f | 343 | |
6d0f6bcf | 344 | #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 |
70a2047f WD |
345 | |
346 | /* timeout values are in ticks */ | |
6d0f6bcf JCPV |
347 | #define CONFIG_SYS_FLASH_ERASE_TOUT (25*CONFIG_SYS_HZ) /* Timeout for Flash Erase */ |
348 | #define CONFIG_SYS_FLASH_WRITE_TOUT (25*CONFIG_SYS_HZ) /* Timeout for Flash Write */ | |
70a2047f WD |
349 | |
350 | /* put cfg at end of flash for now */ | |
5a1aceb0 | 351 | #define CONFIG_ENV_IS_IN_FLASH 1 |
70a2047f | 352 | /* Addr of Environment Sector */ |
0e8d1586 JCPV |
353 | #define CONFIG_ENV_ADDR (PHYS_FLASH_1 + PHYS_FLASH_SIZE - 0x40000) |
354 | #define CONFIG_ENV_SIZE PHYS_FLASH_SECT_SIZE /* Total Size of Environment Sector */ | |
355 | #define CONFIG_ENV_SECT_SIZE (PHYS_FLASH_SECT_SIZE / 16) | |
70a2047f WD |
356 | |
357 | #endif /* __CONFIG_H */ |