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0d19f6c8 IY |
1 | /* |
2 | * Copyright (C) 2009, Ilya Yanok, Emcraft Systems, <yanok@emcraft.com> | |
3 | * | |
4 | * Configuration settings for the Dave/DENX QongEVB-LITE board. | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or | |
7 | * modify it under the terms of the GNU General Public License as | |
8 | * published by the Free Software Foundation; either version 2 of | |
9 | * the License, or (at your option) any later version. | |
10 | * | |
11 | * This program is distributed in the hope that it will be useful, | |
12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
14 | * GNU General Public License for more details. | |
15 | * | |
16 | * You should have received a copy of the GNU General Public License | |
17 | * along with this program; if not, write to the Free Software | |
18 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | |
19 | * MA 02111-1307 USA | |
20 | */ | |
21 | ||
22 | #ifndef __CONFIG_H | |
23 | #define __CONFIG_H | |
24 | ||
86271115 | 25 | #include <asm/arch/imx-regs.h> |
0d19f6c8 | 26 | |
22a9ea97 | 27 | /* High Level Configuration Options */ |
8a508e30 FE |
28 | #define CONFIG_ARM1136 /* This is an arm1136 CPU core */ |
29 | #define CONFIG_MX31 /* in a mx31 */ | |
30 | #define CONFIG_QONG | |
0d19f6c8 IY |
31 | #define CONFIG_MX31_HCLK_FREQ 26000000 /* 26MHz */ |
32 | #define CONFIG_MX31_CLK32 32768 | |
33 | ||
34 | #define CONFIG_DISPLAY_CPUINFO | |
35 | #define CONFIG_DISPLAY_BOARDINFO | |
36 | ||
22a9ea97 SB |
37 | #define CONFIG_SYS_TEXT_BASE 0xa0000000 |
38 | ||
8a508e30 FE |
39 | #define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */ |
40 | #define CONFIG_SETUP_MEMORY_TAGS | |
41 | #define CONFIG_INITRD_TAG | |
0d19f6c8 IY |
42 | |
43 | /* | |
44 | * Size of malloc() pool | |
45 | */ | |
544aa66a | 46 | #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 1536 * 1024) |
0d19f6c8 IY |
47 | |
48 | /* | |
49 | * Hardware drivers | |
50 | */ | |
51 | ||
40f6fffe SB |
52 | #define CONFIG_MXC_UART |
53 | #define CONFIG_MXC_UART_BASE UART1_BASE | |
0d19f6c8 | 54 | |
c4ea1424 | 55 | #define CONFIG_MXC_GPIO |
8640c984 | 56 | #define CONFIG_HW_WATCHDOG |
45997e0a | 57 | |
e98ecd71 SB |
58 | #define CONFIG_MXC_SPI |
59 | #define CONFIG_DEFAULT_SPI_BUS 1 | |
9f481e95 | 60 | #define CONFIG_DEFAULT_SPI_MODE (SPI_MODE_0 | SPI_CS_HIGH) |
4e8b7544 | 61 | #define CONFIG_RTC_MC13XXX |
e98ecd71 | 62 | |
f33bd087 SB |
63 | #define CONFIG_PMIC |
64 | #define CONFIG_PMIC_SPI | |
65 | #define CONFIG_PMIC_FSL | |
e98ecd71 SB |
66 | #define CONFIG_FSL_PMIC_BUS 1 |
67 | #define CONFIG_FSL_PMIC_CS 0 | |
68 | #define CONFIG_FSL_PMIC_CLK 100000 | |
9f481e95 | 69 | #define CONFIG_FSL_PMIC_MODE (SPI_MODE_0 | SPI_CS_HIGH) |
f33bd087 | 70 | #define CONFIG_FSL_PMIC_BITLEN 32 |
e98ecd71 | 71 | |
0d19f6c8 | 72 | /* FPGA */ |
b9eb3fdf | 73 | #define CONFIG_FPGA |
8a508e30 | 74 | #define CONFIG_QONG_FPGA |
0d19f6c8 | 75 | #define CONFIG_FPGA_BASE (CS1_BASE) |
b9eb3fdf SB |
76 | #define CONFIG_FPGA_LATTICE |
77 | #define CONFIG_FPGA_COUNT 1 | |
0d19f6c8 IY |
78 | |
79 | #ifdef CONFIG_QONG_FPGA | |
80 | /* Ethernet */ | |
8a508e30 | 81 | #define CONFIG_DNET |
0d19f6c8 | 82 | #define CONFIG_DNET_BASE (CS1_BASE + QONG_FPGA_PERIPH_SIZE) |
0d19f6c8 | 83 | |
7c8cf0d0 | 84 | /* Framebuffer and LCD */ |
62a22dca HR |
85 | #define CONFIG_VIDEO |
86 | #define CONFIG_CFB_CONSOLE | |
7c8cf0d0 | 87 | #define CONFIG_VIDEO_MX3 |
62a22dca HR |
88 | #define CONFIG_VIDEO_LOGO |
89 | #define CONFIG_VIDEO_SW_CURSOR | |
90 | #define CONFIG_VGA_AS_SINGLE_DEVICE | |
7c8cf0d0 | 91 | #define CONFIG_SYS_CONSOLE_IS_IN_ENV |
62a22dca | 92 | #define CONFIG_SPLASH_SCREEN |
7c8cf0d0 SB |
93 | #define CONFIG_CMD_BMP |
94 | #define CONFIG_BMP_16BPP | |
544aa66a WD |
95 | #define CONFIG_VIDEO_BMP_GZIP |
96 | #define CONFIG_SYS_VIDEO_LOGO_MAX_SIZE (512 << 10) | |
7c8cf0d0 | 97 | |
d7dc464b SB |
98 | /* USB */ |
99 | #define CONFIG_CMD_USB | |
100 | #ifdef CONFIG_CMD_USB | |
101 | #define CONFIG_USB_EHCI /* Enable EHCI USB support */ | |
102 | #define CONFIG_USB_EHCI_MXC | |
103 | #define CONFIG_EHCI_HCD_INIT_AFTER_RESET | |
104 | #define CONFIG_MXC_USB_PORT 2 | |
105 | #define CONFIG_MXC_USB_PORTSC (MXC_EHCI_MODE_ULPI | MXC_EHCI_UTMI_8BIT) | |
106 | #define CONFIG_MXC_USB_FLAGS MXC_EHCI_POWER_PINS_ENABLED | |
107 | #define CONFIG_EHCI_IS_TDI | |
108 | #define CONFIG_USB_STORAGE | |
109 | #define CONFIG_DOS_PARTITION | |
110 | #define CONFIG_SUPPORT_VFAT | |
b952c24a | 111 | #define CONFIG_CMD_EXT2 |
d7dc464b SB |
112 | #define CONFIG_CMD_FAT |
113 | #endif /* CONFIG_CMD_USB */ | |
114 | ||
0d19f6c8 IY |
115 | /* |
116 | * Reducing the ARP timeout from default 5 seconds to 200ms we speed up the | |
117 | * initial TFTP transfer, should the user wish one, significantly. | |
118 | */ | |
119 | #define CONFIG_ARP_TIMEOUT 200UL | |
120 | ||
121 | #endif /* CONFIG_QONG_FPGA */ | |
122 | ||
123 | #define CONFIG_CONS_INDEX 1 | |
124 | #define CONFIG_BAUDRATE 115200 | |
125 | #define CONFIG_SYS_BAUDRATE_TABLE {9600, 19200, 38400, 57600, 115200} | |
126 | ||
127 | /*********************************************************** | |
128 | * Command definition | |
129 | ***********************************************************/ | |
130 | ||
131 | #include <config_cmd_default.h> | |
132 | ||
7e4a9e6d | 133 | #define CONFIG_CMD_CACHE |
b952c24a | 134 | #define CONFIG_CMD_DATE |
0d19f6c8 | 135 | #define CONFIG_CMD_DHCP |
0d19f6c8 | 136 | #define CONFIG_CMD_MII |
45997e0a | 137 | #define CONFIG_CMD_NAND |
b952c24a WD |
138 | #define CONFIG_CMD_NET |
139 | #define CONFIG_CMD_PING | |
140 | #define CONFIG_CMD_SETEXPR | |
e98ecd71 | 141 | #define CONFIG_CMD_SPI |
544aa66a | 142 | #define CONFIG_CMD_UNZIP |
0d19f6c8 | 143 | |
9660e442 | 144 | #define CONFIG_BOARD_LATE_INIT |
0d19f6c8 IY |
145 | |
146 | #define CONFIG_BOOTDELAY 5 | |
147 | ||
148 | #define CONFIG_LOADADDR 0x80800000 /* loadaddr env var */ | |
149 | ||
150 | #define xstr(s) str(s) | |
151 | #define str(s) #s | |
152 | ||
153 | #define CONFIG_EXTRA_ENV_SETTINGS \ | |
154 | "netdev=eth0\0" \ | |
155 | "nfsargs=setenv bootargs root=/dev/nfs rw " \ | |
156 | "nfsroot=${serverip}:${rootpath}\0" \ | |
157 | "ramargs=setenv bootargs root=/dev/ram rw\0" \ | |
158 | "addip=setenv bootargs ${bootargs} " \ | |
159 | "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ | |
160 | ":${hostname}:${netdev}:off panic=1\0" \ | |
161 | "addtty=setenv bootargs ${bootargs}" \ | |
162 | " console=ttymxc0,${baudrate}\0" \ | |
b4e85d0f | 163 | "addmtd=setenv bootargs ${bootargs} ${mtdparts}\0" \ |
0d19f6c8 | 164 | "addmisc=setenv bootargs ${bootargs}\0" \ |
8a1cdaa9 | 165 | "uboot_addr=A0000000\0" \ |
b952c24a | 166 | "kernel_addr=A00C0000\0" \ |
8a1cdaa9 | 167 | "ramdisk_addr=A0300000\0" \ |
b4e85d0f | 168 | "u-boot=qong/u-boot.bin\0" \ |
0d19f6c8 IY |
169 | "kernel_addr_r=80800000\0" \ |
170 | "hostname=qong\0" \ | |
171 | "bootfile=qong/uImage\0" \ | |
172 | "rootpath=/opt/eldk-4.2-arm/armVFP\0" \ | |
b4e85d0f | 173 | "flash_self=run ramargs addip addtty addmtd addmisc;" \ |
0d19f6c8 | 174 | "bootm ${kernel_addr} ${ramdisk_addr}\0" \ |
b4e85d0f | 175 | "flash_nfs=run nfsargs addip addtty addmtd addmisc;" \ |
0d19f6c8 IY |
176 | "bootm ${kernel_addr}\0" \ |
177 | "net_nfs=tftp ${kernel_addr_r} ${bootfile};" \ | |
b4e85d0f | 178 | "run nfsargs addip addtty addmtd addmisc;" \ |
0d19f6c8 | 179 | "bootm\0" \ |
b4e85d0f IY |
180 | "bootcmd=run flash_self\0" \ |
181 | "load=tftp ${loadaddr} ${u-boot}\0" \ | |
0d19f6c8 IY |
182 | "update=protect off " xstr(CONFIG_SYS_MONITOR_BASE) \ |
183 | " +${filesize};era " xstr(CONFIG_SYS_MONITOR_BASE) \ | |
184 | " +${filesize};cp.b ${fileaddr} " \ | |
b4e85d0f | 185 | xstr(CONFIG_SYS_MONITOR_BASE) " ${filesize}\0" \ |
0d19f6c8 | 186 | "upd=run load update\0" \ |
62a22dca HR |
187 | "videomode=video=ctfb:x:640,y:480,depth:16,mode:0,pclk:40000," \ |
188 | "le:120,ri:40,up:35,lo:10,hs:30,vs:3,sync:100663296," \ | |
189 | "vmode:0\0" \ | |
0d19f6c8 IY |
190 | |
191 | /* | |
192 | * Miscellaneous configurable options | |
193 | */ | |
194 | #define CONFIG_SYS_LONGHELP /* undef to save memory */ | |
195 | #define CONFIG_SYS_PROMPT "=> " | |
b4e85d0f | 196 | #define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */ |
0d19f6c8 IY |
197 | /* Print Buffer Size */ |
198 | #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ | |
199 | sizeof(CONFIG_SYS_PROMPT) + 16) | |
200 | #define CONFIG_SYS_MAXARGS 32 /* max number of command args */ | |
201 | /* Boot Argument Buffer Size */ | |
202 | #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE | |
203 | ||
204 | /* memtest works on first 255MB of RAM */ | |
205 | #define CONFIG_SYS_MEMTEST_START PHYS_SDRAM_1 | |
206 | #define CONFIG_SYS_MEMTEST_END (PHYS_SDRAM_1 + 0xff000000) | |
207 | ||
208 | #define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR | |
209 | ||
210 | #define CONFIG_SYS_HZ 1000 | |
211 | ||
8a508e30 FE |
212 | #define CONFIG_CMDLINE_EDITING |
213 | #define CONFIG_SYS_HUSH_PARSER /* Use the HUSH parser */ | |
8a1cdaa9 WD |
214 | #ifdef CONFIG_SYS_HUSH_PARSER |
215 | #define CONFIG_SYS_PROMPT_HUSH_PS2 "> " | |
216 | #endif | |
0d19f6c8 | 217 | |
8a508e30 | 218 | #define CONFIG_MISC_INIT_R |
0d19f6c8 IY |
219 | /*----------------------------------------------------------------------- |
220 | * Stack sizes | |
221 | * | |
222 | * The stack sizes are set up in start.S using the settings below | |
223 | */ | |
224 | #define CONFIG_STACKSIZE (128 * 1024) /* regular stack */ | |
225 | ||
226 | /*----------------------------------------------------------------------- | |
227 | * Physical Memory Map | |
228 | */ | |
229 | #define CONFIG_NR_DRAM_BANKS 1 | |
230 | #define PHYS_SDRAM_1 CSD0_BASE | |
231 | #define PHYS_SDRAM_1_SIZE 0x10000000 /* 256 MB */ | |
232 | ||
45997e0a SB |
233 | /* |
234 | * NAND driver | |
235 | */ | |
236 | ||
237 | #ifndef __ASSEMBLY__ | |
238 | extern void qong_nand_plat_init(void *chip); | |
239 | extern int qong_nand_rdy(void *chip); | |
240 | #endif | |
241 | #define CONFIG_NAND_PLAT | |
242 | #define CONFIG_SYS_MAX_NAND_DEVICE 1 | |
243 | #define CONFIG_SYS_NAND_BASE CS3_BASE | |
244 | #define NAND_PLAT_INIT() qong_nand_plat_init(nand) | |
245 | ||
246 | #define QONG_NAND_CLE(chip) ((unsigned long)(chip)->IO_ADDR_W | (1 << 24)) | |
247 | #define QONG_NAND_ALE(chip) ((unsigned long)(chip)->IO_ADDR_W | (1 << 23)) | |
248 | #define QONG_NAND_WRITE(addr, cmd) \ | |
249 | do { \ | |
250 | __REG8(addr) = cmd; \ | |
251 | } while (0) | |
252 | ||
253 | #define NAND_PLAT_WRITE_CMD(chip, cmd) QONG_NAND_WRITE(QONG_NAND_CLE(chip), cmd) | |
254 | #define NAND_PLAT_WRITE_ADR(chip, cmd) QONG_NAND_WRITE(QONG_NAND_ALE(chip), cmd) | |
255 | #define NAND_PLAT_DEV_READY(chip) (qong_nand_rdy(chip)) | |
256 | ||
0d19f6c8 IY |
257 | /*----------------------------------------------------------------------- |
258 | * FLASH and environment organization | |
259 | */ | |
260 | #define CONFIG_SYS_FLASH_BASE CS0_BASE | |
261 | #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ | |
262 | /* max number of sectors on one chip */ | |
263 | #define CONFIG_SYS_MAX_FLASH_SECT 1024 | |
264 | /* Monitor at beginning of flash */ | |
265 | #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE | |
266 | #define CONFIG_SYS_MONITOR_LEN 0x40000 /* Reserve 256KiB */ | |
267 | ||
8a508e30 | 268 | #define CONFIG_ENV_IS_IN_FLASH |
0d19f6c8 IY |
269 | #define CONFIG_ENV_SECT_SIZE 0x20000 |
270 | #define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE | |
d7dc464b | 271 | #define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x80000) |
0d19f6c8 IY |
272 | |
273 | /* Address and size of Redundant Environment Sector */ | |
274 | #define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE) | |
275 | #define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE | |
276 | ||
277 | /*----------------------------------------------------------------------- | |
278 | * CFI FLASH driver setup | |
279 | */ | |
280 | /* Flash memory is CFI compliant */ | |
8a508e30 | 281 | #define CONFIG_SYS_FLASH_CFI |
0d19f6c8 | 282 | /* Use drivers/cfi_flash.c */ |
8a508e30 | 283 | #define CONFIG_FLASH_CFI_DRIVER |
0d19f6c8 | 284 | /* Use buffered writes (~10x faster) */ |
8a508e30 | 285 | #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE |
0d19f6c8 | 286 | /* Use hardware sector protection */ |
8a508e30 | 287 | #define CONFIG_SYS_FLASH_PROTECTION |
0d19f6c8 IY |
288 | |
289 | /* | |
c9d944d3 | 290 | * Filesystem |
0d19f6c8 | 291 | */ |
c9d944d3 SB |
292 | #define CONFIG_CMD_JFFS2 |
293 | #define CONFIG_CMD_UBI | |
294 | #define CONFIG_CMD_UBIFS | |
295 | #define CONFIG_RBTREE | |
296 | #define CONFIG_MTD_PARTITIONS | |
68d7d651 | 297 | #define CONFIG_CMD_MTDPARTS |
c9d944d3 | 298 | #define CONFIG_LZO |
942556a9 SR |
299 | #define CONFIG_MTD_DEVICE /* needed for mtdparts commands */ |
300 | #define CONFIG_FLASH_CFI_MTD | |
b952c24a WD |
301 | #define MTDIDS_DEFAULT "nor0=physmap-flash.0," \ |
302 | "nand0=gen_nand" | |
b4e85d0f | 303 | #define MTDPARTS_DEFAULT \ |
b952c24a WD |
304 | "mtdparts=physmap-flash.0:" \ |
305 | "512k(U-Boot),128k(env1),128k(env2)," \ | |
306 | "2304k(kernel),13m(ramdisk),-(user);" \ | |
307 | "gen_nand:" \ | |
308 | "128m(nand)" | |
0d19f6c8 | 309 | |
a784c01a | 310 | /* additions for new relocation code, must be added to all boards */ |
e48b7c0a HS |
311 | #define CONFIG_SYS_SDRAM_BASE 0x80000000 |
312 | #define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR | |
553f0982 | 313 | #define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE |
25ddd1fb | 314 | #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) |
e48b7c0a HS |
315 | #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_GBL_DATA_OFFSET) |
316 | ||
8a508e30 | 317 | #define CONFIG_BOARD_EARLY_INIT_F |
e48b7c0a | 318 | |
0d19f6c8 | 319 | #endif /* __CONFIG_H */ |