[people/ms/u-boot.git] / include / configs / rmu.h

/*
 * (C) Copyright 2003-2005
 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */

/*
 * board/config.h - configuration options, board specific
 */

#ifndef __CONFIG_H
#define __CONFIG_H


/*
 * High Level Configuration Options
 * (easy to change)
 */

#undef CONFIG_MPC860
#define CONFIG_MPC850		1	/* This is a MPC850 CPU		*/
#define CONFIG_RPXLITE		1	/* RMU is the RPXlite clone */
#define CONFIG_RMU			1

#define	CONFIG_8xx_CONS_SMC1	1	/* Console is on SMC1		*/
#undef	CONFIG_8xx_CONS_SMC2
#undef	CONFIG_8xx_CONS_NONE
#define CONFIG_BAUDRATE		9600	/* console baudrate = 9600bps	*/
#if 0
#define CONFIG_BOOTDELAY	-1	/* autoboot disabled		*/
#else
#define CONFIG_BOOTDELAY	5	/* autoboot after 5 seconds	*/
#endif

#undef	CONFIG_BOOTARGS
#define CONFIG_BOOTCOMMAND							\
	"bootp; "								\
	"setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} "	\
	"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; "	\
	"bootm"

#define CONFIG_LOADS_ECHO	1	/* echo on for serial download	*/
#undef	CONFIG_SYS_LOADS_BAUD_CHANGE		/* don't allow baudrate change	*/

/* enable I2C and select the hardware/software driver */
#undef	CONFIG_HARD_I2C			/* I2C with hardware support	*/
#define CONFIG_SOFT_I2C		1	/* I2C bit-banged		*/

#define CONFIG_SYS_I2C_SPEED		40000	/* 40 kHz is supposed to work	*/
#define CONFIG_SYS_I2C_SLAVE		0xFE

/* Software (bit-bang) I2C driver configuration */
#define PB_SCL		0x00000020	/* PB 26 */
#define PB_SDA		0x00000010	/* PB 27 */

#define I2C_INIT	(immr->im_cpm.cp_pbdir |=  PB_SCL)
#define I2C_ACTIVE	(immr->im_cpm.cp_pbdir |=  PB_SDA)
#define I2C_TRISTATE	(immr->im_cpm.cp_pbdir &= ~PB_SDA)
#define I2C_READ	((immr->im_cpm.cp_pbdat & PB_SDA) != 0)
#define I2C_SDA(bit)	if(bit) immr->im_cpm.cp_pbdat |=  PB_SDA; \
			else    immr->im_cpm.cp_pbdat &= ~PB_SDA
#define I2C_SCL(bit)	if(bit) immr->im_cpm.cp_pbdat |=  PB_SCL; \
			else    immr->im_cpm.cp_pbdat &= ~PB_SCL
#define I2C_DELAY	udelay(5)	/* 1/4 I2C clock duration */

/* M41T11 Serial Access Timekeeper(R) SRAM */
#define CONFIG_RTC_M41T11 1
#define CONFIG_SYS_I2C_RTC_ADDR 0x68
#define CONFIG_SYS_M41T11_BASE_YEAR 1900	/* play along with the linux driver */

#undef	CONFIG_WATCHDOG			/* watchdog disabled		*/


/*
 * Command line configuration.
 */
#include <config_cmd_default.h>

#define CONFIG_CMD_DATE
#define CONFIG_CMD_DHCP
#define CONFIG_CMD_I2C
#define CONFIG_CMD_NFS
#define CONFIG_CMD_SNTP


/*
 * BOOTP options
 */
#define CONFIG_BOOTP_SUBNETMASK
#define CONFIG_BOOTP_GATEWAY
#define CONFIG_BOOTP_HOSTNAME
#define CONFIG_BOOTP_BOOTPATH
#define CONFIG_BOOTP_BOOTFILESIZE


#define	CONFIG_AUTOBOOT_KEYED		/* Enable password protection */
#define	CONFIG_AUTOBOOT_PROMPT		\
	"\nEnter password - autoboot in %d sec...\n", bootdelay
#define	CONFIG_AUTOBOOT_DELAY_STR	"system"

/*
 * Miscellaneous configurable options
 */
#define	CONFIG_SYS_LONGHELP			/* undef to save memory		*/
#define	CONFIG_SYS_PROMPT	"=> "		/* Monitor Command Prompt	*/
#if defined(CONFIG_CMD_KGDB)
#define	CONFIG_SYS_CBSIZE	1024		/* Console I/O Buffer Size	*/
#else
#define	CONFIG_SYS_CBSIZE	256		/* Console I/O Buffer Size	*/
#endif
#define	CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
#define	CONFIG_SYS_MAXARGS	16		/* max number of command args	*/
#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size	*/

#define CONFIG_SYS_MEMTEST_START	0x0040000	/* memtest works on	*/
#define CONFIG_SYS_MEMTEST_END		0x00C0000	/* 4 ... 12 MB in DRAM	*/

#define	CONFIG_SYS_LOAD_ADDR		0x100000	/* default load address	*/

#define	CONFIG_SYS_HZ		1000		/* decrementer freq: 1 ms ticks	*/

#define CONFIG_SYS_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }

/*
 * Low Level Configuration Settings
 * (address mappings, register initial values, etc.)
 * You should know what you are doing if you make changes here.
 */
/*-----------------------------------------------------------------------
 * Internal Memory Mapped Register
 */
#define CONFIG_SYS_IMMR		0xFA200000

/*-----------------------------------------------------------------------
 * Definitions for initial stack pointer and data area (in DPRAM)
 */
#define CONFIG_SYS_INIT_RAM_ADDR	CONFIG_SYS_IMMR
#define	CONFIG_SYS_INIT_RAM_END	0x2F00	/* End of used area in DPRAM	*/
#define	CONFIG_SYS_GBL_DATA_SIZE	64  /* size in bytes reserved for initial data */
#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
#define	CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET

/*-----------------------------------------------------------------------
 * Start addresses for the final memory configuration
 * (Set up by the startup code)
 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
 */
#define	CONFIG_SYS_SDRAM_BASE		0x00000000
#define CONFIG_SYS_FLASH_BASE		(0-flash_info[0].size)	/* Put flash at end	*/
#if defined(DEBUG) || defined(CONFIG_CMD_IDE)
#define	CONFIG_SYS_MONITOR_LEN		(256 << 10)	/* Reserve 256 kB for Monitor	*/
#else
#define	CONFIG_SYS_MONITOR_LEN		(128 << 10)	/* Reserve 128 kB for Monitor	*/
#endif
#define CONFIG_SYS_MONITOR_BASE	TEXT_BASE
#define	CONFIG_SYS_MALLOC_LEN		(128 << 10)	/* Reserve 128 kB for malloc()	*/

/*
 * For booting Linux, the board info and command line data
 * have to be in the first 8 MB of memory, since this is
 * the maximum mapped by the Linux kernel during initialization.
 */
#define	CONFIG_SYS_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux	*/

/*-----------------------------------------------------------------------
 * FLASH organization
 */
#define CONFIG_SYS_MAX_FLASH_BANKS	1	/* max number of memory banks		*/
#define CONFIG_SYS_MAX_FLASH_SECT	67	/* max number of sectors on one chip	*/

#define CONFIG_SYS_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)	*/

#define	CONFIG_ENV_IS_IN_FLASH	1
#define CONFIG_ENV_ADDR		((TEXT_BASE) + 0x40000)
#define	CONFIG_ENV_SIZE		0x40000	/* Total Size of Environment Sector	*/

/* Address and size of Redundant Environment Sector	*/
#define CONFIG_ENV_ADDR_REDUND	(CONFIG_ENV_ADDR+CONFIG_ENV_SIZE)
#define CONFIG_ENV_SIZE_REDUND	(CONFIG_ENV_SIZE)

/*-----------------------------------------------------------------------
 * Reset address
 */
#define	CONFIG_SYS_RESET_ADDRESS	((ulong)((((immap_t *)CONFIG_SYS_IMMR)->im_clkrst.res)))

/*-----------------------------------------------------------------------
 * Cache Configuration
 */
#define CONFIG_SYS_CACHELINE_SIZE	16	/* For all MPC8xx CPUs			*/
#if defined(CONFIG_CMD_KGDB)
#define CONFIG_SYS_CACHELINE_SHIFT	4	/* log base 2 of the above value	*/
#endif

/*-----------------------------------------------------------------------
 * SYPCR - System Protection Control				11-9
 * SYPCR can only be written once after reset!
 *-----------------------------------------------------------------------
 * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
 */
#if defined(CONFIG_WATCHDOG)
#define CONFIG_SYS_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
			 SYPCR_SWE  | SYPCR_SWRI| SYPCR_SWP)
#else
#define CONFIG_SYS_SYPCR	(SYPCR_SWTC | 0x00000600 | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
#endif

/*-----------------------------------------------------------------------
 * SIUMCR - SIU Module Configuration				11-6
 *-----------------------------------------------------------------------
 * PCMCIA config., multi-function pin tri-state
 */
#define CONFIG_SYS_SIUMCR	(SIUMCR_MLRC10)

/*-----------------------------------------------------------------------
 * TBSCR - Time Base Status and Control				11-26
 *-----------------------------------------------------------------------
 * Clear Reference Interrupt Status, Timebase freezing enabled
 */
#define CONFIG_SYS_TBSCR	(TBSCR_REFA | TBSCR_REFB | TBSCR_TBF | TBSCR_TBE)

/*-----------------------------------------------------------------------
 * RTCSC - Real-Time Clock Status and Control Register		11-27
 *-----------------------------------------------------------------------
 */
/*%%%#define CONFIG_SYS_RTCSC	(RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE) */
#define CONFIG_SYS_RTCSC	(RTCSC_SEC | RTCSC_RTE)

/*-----------------------------------------------------------------------
 * PISCR - Periodic Interrupt Status and Control		11-31
 *-----------------------------------------------------------------------
 * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
 */
#define CONFIG_SYS_PISCR (PISCR_PS | PISCR_PITF)

/*-----------------------------------------------------------------------
 * PLPRCR - PLL, Low-Power, and Reset Control Register		15-30
 *-----------------------------------------------------------------------
 * Reset PLL lock status sticky bit, timer expired status bit and timer
 * interrupt status bit
 *
 * If this is a 80 MHz CPU, set PLL multiplication factor to 5 (5*16=80)!
 */
/* up to 50 MHz we use a 1:1 clock */
#define CONFIG_SYS_PLPRCR	( (5 << PLPRCR_MF_SHIFT) | PLPRCR_TEXPS )

/*-----------------------------------------------------------------------
 * SCCR - System Clock and reset Control Register		15-27
 *-----------------------------------------------------------------------
 * Set clock output, timebase and RTC source and divider,
 * power management and some other internal clocks
 */
#define SCCR_MASK	SCCR_EBDF00
/* up to 50 MHz we use a 1:1 clock */
#define CONFIG_SYS_SCCR	(SCCR_COM00 | SCCR_TBS)

/*-----------------------------------------------------------------------
 * PCMCIA stuff
 *-----------------------------------------------------------------------
 *
 */
#define CONFIG_SYS_PCMCIA_MEM_ADDR	(0xE0000000)
#define CONFIG_SYS_PCMCIA_MEM_SIZE	( 64 << 20 )
#define CONFIG_SYS_PCMCIA_DMA_ADDR	(0xE4000000)
#define CONFIG_SYS_PCMCIA_DMA_SIZE	( 64 << 20 )
#define CONFIG_SYS_PCMCIA_ATTRB_ADDR	(0xE8000000)
#define CONFIG_SYS_PCMCIA_ATTRB_SIZE	( 64 << 20 )
#define CONFIG_SYS_PCMCIA_IO_ADDR	(0xEC000000)
#define CONFIG_SYS_PCMCIA_IO_SIZE	( 64 << 20 )

/*-----------------------------------------------------------------------
 * IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter)
 *-----------------------------------------------------------------------
 */

#define	CONFIG_IDE_8xx_PCCARD	1	/* Use IDE with PC Card	Adapter	*/

#undef	CONFIG_IDE_8xx_DIRECT		/* Direct IDE    not supported	*/
#undef	CONFIG_IDE_LED			/* LED   for ide not supported	*/
#undef	CONFIG_IDE_RESET		/* reset for ide not supported	*/

#define CONFIG_SYS_IDE_MAXBUS		1	/* max. 1 IDE bus		*/
#define CONFIG_SYS_IDE_MAXDEVICE	1	/* max. 1 drive per IDE bus	*/

#define CONFIG_SYS_ATA_IDE0_OFFSET	0x0000

#define CONFIG_SYS_ATA_BASE_ADDR	CONFIG_SYS_PCMCIA_MEM_ADDR

/* Offset for data I/O			*/
#define CONFIG_SYS_ATA_DATA_OFFSET	(CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320)

/* Offset for normal register accesses	*/
#define CONFIG_SYS_ATA_REG_OFFSET	(2 * CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320)

/* Offset for alternate registers	*/
#define CONFIG_SYS_ATA_ALT_OFFSET	0x0100

/*-----------------------------------------------------------------------
 *
 *-----------------------------------------------------------------------
 *
 */
/*#define	CONFIG_SYS_DER	0x2002000F*/
#define CONFIG_SYS_DER	0

/*
 * Init Memory Controller:
 *
 * BR0 and OR0 (FLASH)
 */

#define FLASH_BASE_PRELIM	0xFC000000	/* FLASH base - up to 64 MB of flash */
#define CONFIG_SYS_PRELIM_OR_AM	0xFC000000	/* OR addr mask - map 64 MB */

/* FLASH timing: ACS = 0, TRLX = 0, CSNT = 0, SCY = 4, ETHR = 0, BIH = 1 */
#define CONFIG_SYS_OR_TIMING_FLASH (OR_SCY_4_CLK | OR_BI)

#define CONFIG_SYS_OR0_PRELIM	(CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_FLASH)
#define CONFIG_SYS_BR0_PRELIM	((FLASH_BASE_PRELIM & BR_BA_MSK) | BR_V)

/*
 * BR1 and OR1 (SDRAM)
 *
 */
#define SDRAM_BASE_PRELIM	0x00000000	/* SDRAM base	*/
#define	SDRAM_MAX_SIZE		0x08000000	/* max 128 MB */

/* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care)	*/
#define CONFIG_SYS_OR_TIMING_SDRAM	0x00000E00

#define CONFIG_SYS_OR1_PRELIM	(0xF0000000 | CONFIG_SYS_OR_TIMING_SDRAM ) /* map 256 MB */
#define CONFIG_SYS_BR1_PRELIM	((SDRAM_BASE_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )

/* RPXLITE mem setting */
#define CONFIG_SYS_NVRAM_BASE	0xFA000000		/* NVRAM & SRAM base */
/*      IMMR:		0xFA200000		   IMMR base address - see above */
#define	CONFIG_SYS_BCSR_BASE	0xFA400000		/* BCSR base address */

#define	CONFIG_SYS_BR3_PRELIM	(CONFIG_SYS_BCSR_BASE | BR_V)			/* BCSR */
#define CONFIG_SYS_OR3_PRELIM	0xFFFF8910
#define CONFIG_SYS_BR4_PRELIM  (CONFIG_SYS_NVRAM_BASE | BR_PS_8 | BR_V)	/* NVRAM & SRAM */
#define CONFIG_SYS_OR4_PRELIM	0xFFFE0970

/*
 * Memory Periodic Timer Prescaler
 */

/* periodic timer for refresh */
#define CONFIG_SYS_MAMR_PTA	20

/*
 * Refresh clock Prescalar
 */
#define CONFIG_SYS_MPTPR	MPTPR_PTP_DIV2

/*
 * MAMR settings for SDRAM
 */

/* 9 column SDRAM */
#define CONFIG_SYS_MAMR_9COL	((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT)  | MAMR_PTAE	    |	\
			 MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 |	\
			 MAMR_RLFA_16X | MAMR_WLFA_16X | MAMR_TLFA_16X)

/*
 * Internal Definitions
 *
 * Boot Flags
 */
#define	BOOTFLAG_COLD	0x01	/* Normal Power-On: Boot from FLASH	*/
#define BOOTFLAG_WARM	0x02	/* Software reboot			*/

/*
 * BCSRx
 *
 * Board Status and Control Registers
 *
 */

#define BCSR0	(CONFIG_SYS_BCSR_BASE + 0)
#define BCSR1	(CONFIG_SYS_BCSR_BASE + 1)
#define BCSR2	(CONFIG_SYS_BCSR_BASE + 2)
#define BCSR3	(CONFIG_SYS_BCSR_BASE + 3)

#define BCSR0_ENMONXCVR	0x01	/* Monitor XVCR Control */
#define BCSR0_ENNVRAM	0x02	/* CS4# Control */
#define BCSR0_LED5	0x04	/* LED5 control 0='on' 1='off' */
#define BCSR0_LED4	0x08	/* LED4 control 0='on' 1='off' */
#define BCSR0_FULLDPLX	0x10	/* Ethernet XCVR Control */
#define BCSR0_COLTEST	0x20
#define BCSR0_ETHLPBK	0x40
#define BCSR0_ETHEN	0x80

#define BCSR1_PCVCTL7	0x01	/* PC Slot B Control */
#define BCSR1_PCVCTL6	0x02
#define BCSR1_PCVCTL5	0x04
#define BCSR1_PCVCTL4	0x08
#define BCSR1_IPB5SEL	0x10

#define BCSR2_ENPA5HDR	0x08	/* USB Control */
#define BCSR2_ENUSBCLK	0x10
#define BCSR2_USBPWREN	0x20
#define BCSR2_USBSPD	0x40
#define BCSR2_USBSUSP	0x80

#define BCSR3_BWRTC	0x01	/* Real Time Clock Battery */
#define BCSR3_BWNVR	0x02	/* NVRAM Battery */
#define BCSR3_RDY_BSY	0x04	/* Flash Operation */
#define BCSR3_RPXL	0x08	/* Reserved (reads back '1') */
#define BCSR3_D27	0x10	/* Dip Switch settings */
#define BCSR3_D26	0x20
#define BCSR3_D25	0x40
#define BCSR3_D24	0x80

#endif	/* __CONFIG_H */
Commit	Line	Data
73a8b27c	1	/*
414eec35	2	* (C) Copyright 2003-2005
73a8b27c WD	3	* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
	4	*
	5	* See file CREDITS for list of people who contributed to this
	6	* project.
	7	*
	8	* This program is free software; you can redistribute it and/or
	9	* modify it under the terms of the GNU General Public License as
	10	* published by the Free Software Foundation; either version 2 of
	11	* the License, or (at your option) any later version.
	12	*
	13	* This program is distributed in the hope that it will be useful,
	14	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	15	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	16	* GNU General Public License for more details.
	17	*
	18	* You should have received a copy of the GNU General Public License
	19	* along with this program; if not, write to the Free Software
	20	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	21	* MA 02111-1307 USA
	22	*/
	23
	24	/*
	25	* board/config.h - configuration options, board specific
	26	*/
	27
	28	#ifndef __CONFIG_H
	29	#define __CONFIG_H
	30
	31
	32	/*
	33	* High Level Configuration Options
	34	* (easy to change)
	35	*/
	36
	37	#undef CONFIG_MPC860
	38	#define CONFIG_MPC850 1 /* This is a MPC850 CPU */
	39	#define CONFIG_RPXLITE 1 /* RMU is the RPXlite clone */
	40	#define CONFIG_RMU 1
	41
	42	#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */
	43	#undef CONFIG_8xx_CONS_SMC2
	44	#undef CONFIG_8xx_CONS_NONE
	45	#define CONFIG_BAUDRATE 9600 /* console baudrate = 9600bps */
	46	#if 0
	47	#define CONFIG_BOOTDELAY -1 /* autoboot disabled */
	48	#else
	49	#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
	50	#endif
	51
73a8b27c WD	52	#undef CONFIG_BOOTARGS
73a8b27c WD	53	#define CONFIG_BOOTCOMMAND \
53677ef1 WD	54	"bootp; " \
	55	"setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \
	56	"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; " \
73a8b27c WD	57	"bootm"
	58
	59	#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
6d0f6bcf	60	#undef CONFIG_SYS_LOADS_BAUD_CHANGE /* don't allow baudrate change */
73a8b27c	61
ca75adde WD	62	/* enable I2C and select the hardware/software driver */
	63	#undef CONFIG_HARD_I2C /* I2C with hardware support */
	64	#define CONFIG_SOFT_I2C 1 /* I2C bit-banged */
	65
6d0f6bcf JCPV	66	#define CONFIG_SYS_I2C_SPEED 40000 /* 40 kHz is supposed to work */
6d0f6bcf JCPV	67	#define CONFIG_SYS_I2C_SLAVE 0xFE
ca75adde WD	68
	69	/* Software (bit-bang) I2C driver configuration */
	70	#define PB_SCL 0x00000020 /* PB 26 */
	71	#define PB_SDA 0x00000010 /* PB 27 */
	72
	73	#define I2C_INIT (immr->im_cpm.cp_pbdir \|= PB_SCL)
	74	#define I2C_ACTIVE (immr->im_cpm.cp_pbdir \|= PB_SDA)
	75	#define I2C_TRISTATE (immr->im_cpm.cp_pbdir &= ~PB_SDA)
	76	#define I2C_READ ((immr->im_cpm.cp_pbdat & PB_SDA) != 0)
	77	#define I2C_SDA(bit) if(bit) immr->im_cpm.cp_pbdat \|= PB_SDA; \
	78	else immr->im_cpm.cp_pbdat &= ~PB_SDA
	79	#define I2C_SCL(bit) if(bit) immr->im_cpm.cp_pbdat \|= PB_SCL; \
	80	else immr->im_cpm.cp_pbdat &= ~PB_SCL
	81	#define I2C_DELAY udelay(5) /* 1/4 I2C clock duration */
	82
	83	/* M41T11 Serial Access Timekeeper(R) SRAM */
	84	#define CONFIG_RTC_M41T11 1
6d0f6bcf JCPV	85	#define CONFIG_SYS_I2C_RTC_ADDR 0x68
6d0f6bcf JCPV	86	#define CONFIG_SYS_M41T11_BASE_YEAR 1900 /* play along with the linux driver */
ca75adde	87
73a8b27c WD	88	#undef CONFIG_WATCHDOG /* watchdog disabled */
73a8b27c WD	89
ca75adde	90
90cc3eb6 JL	91	/*
	92	* Command line configuration.
	93	*/
	94	#include <config_cmd_default.h>
73a8b27c	95
90cc3eb6 JL	96	#define CONFIG_CMD_DATE
	97	#define CONFIG_CMD_DHCP
	98	#define CONFIG_CMD_I2C
	99	#define CONFIG_CMD_NFS
	100	#define CONFIG_CMD_SNTP
	101
	102
d3b8c1a7 JL	103	/*
	104	* BOOTP options
	105	*/
	106	#define CONFIG_BOOTP_SUBNETMASK
	107	#define CONFIG_BOOTP_GATEWAY
	108	#define CONFIG_BOOTP_HOSTNAME
	109	#define CONFIG_BOOTP_BOOTPATH
	110	#define CONFIG_BOOTP_BOOTFILESIZE
	111
73a8b27c	112
af6d1dfc	113	#define CONFIG_AUTOBOOT_KEYED /* Enable password protection */
f2302d44 SR	114	#define CONFIG_AUTOBOOT_PROMPT \
f2302d44 SR	115	"\nEnter password - autoboot in %d sec...\n", bootdelay
af6d1dfc WD	116	#define CONFIG_AUTOBOOT_DELAY_STR "system"
af6d1dfc WD	117
73a8b27c WD	118	/*
	119	* Miscellaneous configurable options
	120	*/
6d0f6bcf JCPV	121	#define CONFIG_SYS_LONGHELP /* undef to save memory */
6d0f6bcf JCPV	122	#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
90cc3eb6	123	#if defined(CONFIG_CMD_KGDB)
6d0f6bcf	124	#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
73a8b27c	125	#else
6d0f6bcf	126	#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
73a8b27c	127	#endif
6d0f6bcf JCPV	128	#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
	129	#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
	130	#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
73a8b27c	131
6d0f6bcf JCPV	132	#define CONFIG_SYS_MEMTEST_START 0x0040000 /* memtest works on */
6d0f6bcf JCPV	133	#define CONFIG_SYS_MEMTEST_END 0x00C0000 /* 4 ... 12 MB in DRAM */
73a8b27c	134
6d0f6bcf	135	#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
73a8b27c	136
6d0f6bcf	137	#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */
73a8b27c	138
6d0f6bcf	139	#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
73a8b27c WD	140
	141	/*
	142	* Low Level Configuration Settings
	143	* (address mappings, register initial values, etc.)
	144	* You should know what you are doing if you make changes here.
	145	*/
	146	/*-----------------------------------------------------------------------
	147	* Internal Memory Mapped Register
	148	*/
6d0f6bcf	149	#define CONFIG_SYS_IMMR 0xFA200000
73a8b27c WD	150
	151	/*-----------------------------------------------------------------------
	152	* Definitions for initial stack pointer and data area (in DPRAM)
	153	*/
6d0f6bcf JCPV	154	#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR
	155	#define CONFIG_SYS_INIT_RAM_END 0x2F00 /* End of used area in DPRAM */
	156	#define CONFIG_SYS_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */
	157	#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
	158	#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
73a8b27c WD	159
	160	/*-----------------------------------------------------------------------
	161	* Start addresses for the final memory configuration
	162	* (Set up by the startup code)
6d0f6bcf	163	* Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
73a8b27c	164	*/
6d0f6bcf JCPV	165	#define CONFIG_SYS_SDRAM_BASE 0x00000000
6d0f6bcf JCPV	166	#define CONFIG_SYS_FLASH_BASE (0-flash_info[0].size) /* Put flash at end */
90cc3eb6	167	#if defined(DEBUG) \|\| defined(CONFIG_CMD_IDE)
6d0f6bcf	168	#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
73a8b27c	169	#else
6d0f6bcf	170	#define CONFIG_SYS_MONITOR_LEN (128 << 10) /* Reserve 128 kB for Monitor */
73a8b27c	171	#endif
6d0f6bcf JCPV	172	#define CONFIG_SYS_MONITOR_BASE TEXT_BASE
6d0f6bcf JCPV	173	#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
73a8b27c WD	174
	175	/*
	176	* For booting Linux, the board info and command line data
	177	* have to be in the first 8 MB of memory, since this is
	178	* the maximum mapped by the Linux kernel during initialization.
	179	*/
6d0f6bcf	180	#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
73a8b27c WD	181
	182	/*-----------------------------------------------------------------------
	183	* FLASH organization
	184	*/
6d0f6bcf JCPV	185	#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
6d0f6bcf JCPV	186	#define CONFIG_SYS_MAX_FLASH_SECT 67 /* max number of sectors on one chip */
73a8b27c	187
6d0f6bcf JCPV	188	#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
6d0f6bcf JCPV	189	#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
73a8b27c	190
5a1aceb0	191	#define CONFIG_ENV_IS_IN_FLASH 1
0e8d1586 JCPV	192	#define CONFIG_ENV_ADDR ((TEXT_BASE) + 0x40000)
0e8d1586 JCPV	193	#define CONFIG_ENV_SIZE 0x40000 /* Total Size of Environment Sector */
73a8b27c WD	194
73a8b27c WD	195	/* Address and size of Redundant Environment Sector */
0e8d1586 JCPV	196	#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR+CONFIG_ENV_SIZE)
0e8d1586 JCPV	197	#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
73a8b27c	198
ca75adde WD	199	/*-----------------------------------------------------------------------
	200	* Reset address
	201	*/
6d0f6bcf	202	#define CONFIG_SYS_RESET_ADDRESS ((ulong)((((immap_t *)CONFIG_SYS_IMMR)->im_clkrst.res)))
ca75adde	203
73a8b27c WD	204	/*-----------------------------------------------------------------------
	205	* Cache Configuration
	206	*/
6d0f6bcf	207	#define CONFIG_SYS_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */
90cc3eb6	208	#if defined(CONFIG_CMD_KGDB)
6d0f6bcf	209	#define CONFIG_SYS_CACHELINE_SHIFT 4 /* log base 2 of the above value */
73a8b27c WD	210	#endif
	211
	212	/*-----------------------------------------------------------------------
	213	* SYPCR - System Protection Control 11-9
	214	* SYPCR can only be written once after reset!
	215	*-----------------------------------------------------------------------
	216	* Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
	217	*/
	218	#if defined(CONFIG_WATCHDOG)
6d0f6bcf	219	#define CONFIG_SYS_SYPCR (SYPCR_SWTC \| SYPCR_BMT \| SYPCR_BME \| SYPCR_SWF \| \
73a8b27c WD	220	SYPCR_SWE \| SYPCR_SWRI\| SYPCR_SWP)
73a8b27c WD	221	#else
6d0f6bcf	222	#define CONFIG_SYS_SYPCR (SYPCR_SWTC \| 0x00000600 \| SYPCR_BME \| SYPCR_SWF \| SYPCR_SWP)
73a8b27c WD	223	#endif
	224
	225	/*-----------------------------------------------------------------------
	226	* SIUMCR - SIU Module Configuration 11-6
	227	*-----------------------------------------------------------------------
	228	* PCMCIA config., multi-function pin tri-state
	229	*/
6d0f6bcf	230	#define CONFIG_SYS_SIUMCR (SIUMCR_MLRC10)
73a8b27c WD	231
	232	/*-----------------------------------------------------------------------
	233	* TBSCR - Time Base Status and Control 11-26
	234	*-----------------------------------------------------------------------
	235	* Clear Reference Interrupt Status, Timebase freezing enabled
	236	*/
6d0f6bcf	237	#define CONFIG_SYS_TBSCR (TBSCR_REFA \| TBSCR_REFB \| TBSCR_TBF \| TBSCR_TBE)
73a8b27c WD	238
	239	/*-----------------------------------------------------------------------
	240	* RTCSC - Real-Time Clock Status and Control Register 11-27
	241	*-----------------------------------------------------------------------
	242	*/
6d0f6bcf JCPV	243	/%%%#define CONFIG_SYS_RTCSC (RTCSC_SEC \| RTCSC_ALR \| RTCSC_RTF\| RTCSC_RTE) /
6d0f6bcf JCPV	244	#define CONFIG_SYS_RTCSC (RTCSC_SEC \| RTCSC_RTE)
73a8b27c WD	245
	246	/*-----------------------------------------------------------------------
	247	* PISCR - Periodic Interrupt Status and Control 11-31
	248	*-----------------------------------------------------------------------
	249	* Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
	250	*/
6d0f6bcf	251	#define CONFIG_SYS_PISCR (PISCR_PS \| PISCR_PITF)
73a8b27c WD	252
	253	/*-----------------------------------------------------------------------
	254	* PLPRCR - PLL, Low-Power, and Reset Control Register 15-30
	255	*-----------------------------------------------------------------------
	256	* Reset PLL lock status sticky bit, timer expired status bit and timer
	257	* interrupt status bit
	258	*
	259	* If this is a 80 MHz CPU, set PLL multiplication factor to 5 (5*16=80)!
	260	*/
	261	/* up to 50 MHz we use a 1:1 clock */
6d0f6bcf	262	#define CONFIG_SYS_PLPRCR ( (5 << PLPRCR_MF_SHIFT) \| PLPRCR_TEXPS )
73a8b27c WD	263
	264	/*-----------------------------------------------------------------------
	265	* SCCR - System Clock and reset Control Register 15-27
	266	*-----------------------------------------------------------------------
	267	* Set clock output, timebase and RTC source and divider,
	268	* power management and some other internal clocks
	269	*/
	270	#define SCCR_MASK SCCR_EBDF00
	271	/* up to 50 MHz we use a 1:1 clock */
6d0f6bcf	272	#define CONFIG_SYS_SCCR (SCCR_COM00 \| SCCR_TBS)
73a8b27c WD	273
	274	/*-----------------------------------------------------------------------
	275	* PCMCIA stuff
	276	*-----------------------------------------------------------------------
	277	*
	278	*/
6d0f6bcf JCPV	279	#define CONFIG_SYS_PCMCIA_MEM_ADDR (0xE0000000)
	280	#define CONFIG_SYS_PCMCIA_MEM_SIZE ( 64 << 20 )
	281	#define CONFIG_SYS_PCMCIA_DMA_ADDR (0xE4000000)
	282	#define CONFIG_SYS_PCMCIA_DMA_SIZE ( 64 << 20 )
	283	#define CONFIG_SYS_PCMCIA_ATTRB_ADDR (0xE8000000)
	284	#define CONFIG_SYS_PCMCIA_ATTRB_SIZE ( 64 << 20 )
	285	#define CONFIG_SYS_PCMCIA_IO_ADDR (0xEC000000)
	286	#define CONFIG_SYS_PCMCIA_IO_SIZE ( 64 << 20 )
73a8b27c WD	287
	288	/*-----------------------------------------------------------------------
	289	* IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter)
	290	*-----------------------------------------------------------------------
	291	*/
	292
	293	#define CONFIG_IDE_8xx_PCCARD 1 /* Use IDE with PC Card Adapter */
	294
	295	#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */
	296	#undef CONFIG_IDE_LED /* LED for ide not supported */
	297	#undef CONFIG_IDE_RESET /* reset for ide not supported */
	298
6d0f6bcf JCPV	299	#define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE bus */
6d0f6bcf JCPV	300	#define CONFIG_SYS_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */
73a8b27c	301
6d0f6bcf	302	#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000
73a8b27c	303
6d0f6bcf	304	#define CONFIG_SYS_ATA_BASE_ADDR CONFIG_SYS_PCMCIA_MEM_ADDR
73a8b27c WD	305
73a8b27c WD	306	/* Offset for data I/O */
6d0f6bcf	307	#define CONFIG_SYS_ATA_DATA_OFFSET (CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320)
73a8b27c WD	308
73a8b27c WD	309	/* Offset for normal register accesses */
6d0f6bcf	310	#define CONFIG_SYS_ATA_REG_OFFSET (2 * CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320)
73a8b27c WD	311
73a8b27c WD	312	/* Offset for alternate registers */
6d0f6bcf	313	#define CONFIG_SYS_ATA_ALT_OFFSET 0x0100
73a8b27c WD	314
	315	/*-----------------------------------------------------------------------
	316	*
	317	*-----------------------------------------------------------------------
	318	*
	319	*/
6d0f6bcf JCPV	320	/#define CONFIG_SYS_DER 0x2002000F/
6d0f6bcf JCPV	321	#define CONFIG_SYS_DER 0
73a8b27c WD	322
	323	/*
	324	* Init Memory Controller:
	325	*
	326	* BR0 and OR0 (FLASH)
	327	*/
	328
7e780369	329	#define FLASH_BASE_PRELIM 0xFC000000 /* FLASH base - up to 64 MB of flash */
6d0f6bcf	330	#define CONFIG_SYS_PRELIM_OR_AM 0xFC000000 /* OR addr mask - map 64 MB */
73a8b27c WD	331
73a8b27c WD	332	/* FLASH timing: ACS = 0, TRLX = 0, CSNT = 0, SCY = 4, ETHR = 0, BIH = 1 */
6d0f6bcf	333	#define CONFIG_SYS_OR_TIMING_FLASH (OR_SCY_4_CLK \| OR_BI)
73a8b27c	334
6d0f6bcf JCPV	335	#define CONFIG_SYS_OR0_PRELIM (CONFIG_SYS_PRELIM_OR_AM \| CONFIG_SYS_OR_TIMING_FLASH)
6d0f6bcf JCPV	336	#define CONFIG_SYS_BR0_PRELIM ((FLASH_BASE_PRELIM & BR_BA_MSK) \| BR_V)
73a8b27c WD	337
	338	/*
	339	* BR1 and OR1 (SDRAM)
	340	*
	341	*/
	342	#define SDRAM_BASE_PRELIM 0x00000000 /* SDRAM base */
d94f92cb	343	#define SDRAM_MAX_SIZE 0x08000000 /* max 128 MB */
73a8b27c WD	344
73a8b27c WD	345	/* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care) */
6d0f6bcf	346	#define CONFIG_SYS_OR_TIMING_SDRAM 0x00000E00
73a8b27c	347
6d0f6bcf JCPV	348	#define CONFIG_SYS_OR1_PRELIM (0xF0000000 \| CONFIG_SYS_OR_TIMING_SDRAM ) /* map 256 MB */
6d0f6bcf JCPV	349	#define CONFIG_SYS_BR1_PRELIM ((SDRAM_BASE_PRELIM & BR_BA_MSK) \| BR_MS_UPMA \| BR_V )
73a8b27c WD	350
73a8b27c WD	351	/* RPXLITE mem setting */
6d0f6bcf	352	#define CONFIG_SYS_NVRAM_BASE 0xFA000000 /* NVRAM & SRAM base */
7e780369	353	/* IMMR: 0xFA200000 IMMR base address - see above */
6d0f6bcf	354	#define CONFIG_SYS_BCSR_BASE 0xFA400000 /* BCSR base address */
7e780369	355
6d0f6bcf JCPV	356	#define CONFIG_SYS_BR3_PRELIM (CONFIG_SYS_BCSR_BASE \| BR_V) /* BCSR */
	357	#define CONFIG_SYS_OR3_PRELIM 0xFFFF8910
	358	#define CONFIG_SYS_BR4_PRELIM (CONFIG_SYS_NVRAM_BASE \| BR_PS_8 \| BR_V) /* NVRAM & SRAM */
	359	#define CONFIG_SYS_OR4_PRELIM 0xFFFE0970
73a8b27c WD	360
	361	/*
	362	* Memory Periodic Timer Prescaler
	363	*/
	364
	365	/* periodic timer for refresh */
6d0f6bcf	366	#define CONFIG_SYS_MAMR_PTA 20
73a8b27c WD	367
	368	/*
	369	* Refresh clock Prescalar
	370	*/
6d0f6bcf	371	#define CONFIG_SYS_MPTPR MPTPR_PTP_DIV2
73a8b27c WD	372
	373	/*
	374	* MAMR settings for SDRAM
	375	*/
	376
d94f92cb	377	/* 9 column SDRAM */
6d0f6bcf	378	#define CONFIG_SYS_MAMR_9COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) \| MAMR_PTAE \| \
73a8b27c WD	379	MAMR_AMA_TYPE_1 \| MAMR_DSA_1_CYCL \| MAMR_G0CLA_A10 \| \
	380	MAMR_RLFA_16X \| MAMR_WLFA_16X \| MAMR_TLFA_16X)
	381
	382	/*
	383	* Internal Definitions
	384	*
	385	* Boot Flags
	386	*/
	387	#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
	388	#define BOOTFLAG_WARM 0x02 /* Software reboot */
	389
	390	/*
	391	* BCSRx
	392	*
	393	* Board Status and Control Registers
	394	*
	395	*/
	396
6d0f6bcf JCPV	397	#define BCSR0 (CONFIG_SYS_BCSR_BASE + 0)
	398	#define BCSR1 (CONFIG_SYS_BCSR_BASE + 1)
	399	#define BCSR2 (CONFIG_SYS_BCSR_BASE + 2)
	400	#define BCSR3 (CONFIG_SYS_BCSR_BASE + 3)
73a8b27c WD	401
73a8b27c WD	402	#define BCSR0_ENMONXCVR 0x01 /* Monitor XVCR Control */
53677ef1	403	#define BCSR0_ENNVRAM 0x02 /* CS4# Control */
73a8b27c WD	404	#define BCSR0_LED5 0x04 /* LED5 control 0='on' 1='off' */
	405	#define BCSR0_LED4 0x08 /* LED4 control 0='on' 1='off' */
	406	#define BCSR0_FULLDPLX 0x10 /* Ethernet XCVR Control */
	407	#define BCSR0_COLTEST 0x20
	408	#define BCSR0_ETHLPBK 0x40
	409	#define BCSR0_ETHEN 0x80
	410
	411	#define BCSR1_PCVCTL7 0x01 /* PC Slot B Control */
	412	#define BCSR1_PCVCTL6 0x02
	413	#define BCSR1_PCVCTL5 0x04
	414	#define BCSR1_PCVCTL4 0x08
	415	#define BCSR1_IPB5SEL 0x10
	416
	417	#define BCSR2_ENPA5HDR 0x08 /* USB Control */
	418	#define BCSR2_ENUSBCLK 0x10
	419	#define BCSR2_USBPWREN 0x20
	420	#define BCSR2_USBSPD 0x40
	421	#define BCSR2_USBSUSP 0x80
	422
	423	#define BCSR3_BWRTC 0x01 /* Real Time Clock Battery */
	424	#define BCSR3_BWNVR 0x02 /* NVRAM Battery */
	425	#define BCSR3_RDY_BSY 0x04 /* Flash Operation */
	426	#define BCSR3_RPXL 0x08 /* Reserved (reads back '1') */
	427	#define BCSR3_D27 0x10 /* Dip Switch settings */
	428	#define BCSR3_D26 0x20
	429	#define BCSR3_D25 0x40
	430	#define BCSR3_D24 0x80
	431
	432	#endif /* __CONFIG_H */