[people/ms/u-boot.git] / include / configs / rsdproto.h

/*
 * (C) Copyright 2000
 * Murray Jensen <Murray.Jensen@cmst.csiro.au>
 *
 * (C) Copyright 2000
 * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
 * Marius Groeger <mgroeger@sysgo.de>
 *
 * Configuation settings for the R&S Protocol Board board.
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

#ifndef __CONFIG_H
#define __CONFIG_H

/*
 * High Level Configuration Options
 * (easy to change)
 */

#define CONFIG_MPC8260		1	/* This is an MPC8260 CPU	*/
#define CONFIG_RSD_PROTO	1	/* on a R&S Protocol Board      */
#define CONFIG_CPM2		1	/* Has a CPM2 */

#define	CONFIG_SYS_TEXT_BASE	0xff000000
#define	CONFIG_SYS_LDSCRIPT	"board/rsdproto/u-boot.lds"

#define	CONFIG_MISC_INIT_F	1	/* Use misc_init_f()		*/

/*
 * select serial console configuration
 *
 * if either CONFIG_CONS_ON_SMC or CONFIG_CONS_ON_SCC is selected, then
 * CONFIG_CONS_INDEX must be set to the channel number (1-2 for SMC, 1-4
 * for SCC).
 *
 * if CONFIG_CONS_NONE is defined, then the serial console routines must
 * defined elsewhere.
 */
#undef	CONFIG_CONS_ON_SMC		/* define if console on SMC */
#define	CONFIG_CONS_ON_SCC		/* define if console on SCC */
#undef	CONFIG_CONS_NONE		/* define if console on neither */
#define CONFIG_CONS_INDEX	1	/* which SMC/SCC channel for console */

/*
 * select ethernet configuration
 *
 * if either CONFIG_ETHER_ON_SCC or CONFIG_ETHER_ON_FCC is selected, then
 * CONFIG_ETHER_INDEX must be set to the channel number (1-4 for SCC, 1-3
 * for FCC)
 *
 * if CONFIG_ETHER_NONE is defined, then either the ethernet routines must be
 * defined elsewhere (as for the console), or CONFIG_CMD_NET must be unset.
 */
#undef	CONFIG_ETHER_ON_SCC		/* define if ethernet on SCC	*/
#define	CONFIG_ETHER_ON_FCC		/* define if ethernet on FCC	*/
#undef	CONFIG_ETHER_NONE		/* define if ethernet on neither */
#define CONFIG_ETHER_INDEX	2	/* which SCC/FCC channel for ethernet */

#if (CONFIG_ETHER_INDEX == 2)

/*
 * - Rx-CLK is CLK13
 * - Tx-CLK is CLK14
 * - Select bus for bd/buffers (see 28-13)
 * - Enable Full Duplex in FSMR
 */
# define CONFIG_SYS_CMXFCR_MASK2	(CMXFCR_FC2 | CMXFCR_RF2CS_MSK | CMXFCR_TF2CS_MSK)
# define CONFIG_SYS_CMXFCR_VALUE2	(CMXFCR_RF2CS_CLK13 | CMXFCR_TF2CS_CLK14)
# define CONFIG_SYS_CPMFCR_RAMTYPE	(0)
# define CONFIG_SYS_FCC_PSMR		(FCC_PSMR_FDE | FCC_PSMR_LPB)

#endif /* CONFIG_ETHER_INDEX */


/* allow to overwrite serial and ethaddr */
#define CONFIG_ENV_OVERWRITE

/* enable I2C */
#define CONFIG_HARD_I2C		1	/* I2C with hardware support */
#define CONFIG_SYS_I2C_SPEED		50000	/* I2C speed and slave address */
#define CONFIG_SYS_I2C_SLAVE		0x30


/* system clock rate (CLKIN) - equal to the 60x and local bus speed */
#define CONFIG_8260_CLKIN	50000000	/* in Hz */

#define CONFIG_BAUDRATE		115200


/*
 * BOOTP options
 */
#define CONFIG_BOOTP_BOOTFILESIZE
#define CONFIG_BOOTP_BOOTPATH
#define CONFIG_BOOTP_GATEWAY
#define CONFIG_BOOTP_HOSTNAME


/*
 * Command line configuration.
 */
#include <config_cmd_default.h>

#undef CONFIG_CMD_KGDB


/* Define this if you want to boot from 0x00000100. If you don't define
 * this, you will need to program the bootloader to 0xfff00000, and
 * get the hardware reset config words at 0xfe000000. The simplest
 * way to do that is to program the bootloader at both addresses.
 * It is suggested that you just let U-Boot live at 0x00000000.
 */
#define CONFIG_SYS_RSD_BOOT_LOW 1

#define CONFIG_BOOTDELAY	5
#define CONFIG_BOOTARGS		"devfs=mount root=ramfs"
#define CONFIG_ETHADDR		08:00:3e:26:0a:5a
#define CONFIG_NETMASK          255.255.0.0

#if defined(CONFIG_CMD_KGDB)
#define CONFIG_KGDB_BAUDRATE	230400		/* speed to run kgdb serial port */
#define CONFIG_KGDB_SER_INDEX	2		/* which serial port to use */
#endif

/*
 * Miscellaneous configurable options
 */
#define	CONFIG_SYS_LONGHELP				/* undef to save memory		*/
#define	CONFIG_SYS_PROMPT		"=> "		/* Monitor Command Prompt	*/
#if defined(CONFIG_CMD_KGDB)
#define	CONFIG_SYS_CBSIZE		1024		/* Console I/O Buffer Size	*/
#else
#define	CONFIG_SYS_CBSIZE		256		/* Console I/O Buffer Size	*/
#endif
#define	CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
#define	CONFIG_SYS_MAXARGS		16		/* max number of command args	*/
#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size	*/

#define CONFIG_SYS_MEMTEST_START	0x00400000	/* memtest works on	*/
#define CONFIG_SYS_MEMTEST_END		0x01c00000	/* 4 ... 28 MB in DRAM	*/

#define	CONFIG_SYS_LOAD_ADDR		0x100000	/* default load address	*/

#define	CONFIG_SYS_HZ			1000		/* decrementer freq: 1 ms ticks	*/

/*
 * Low Level Configuration Settings
 * (address mappings, register initial values, etc.)
 * You should know what you are doing if you make changes here.
 */

/*-----------------------------------------------------------------------
 * Physical Memory Map
 */
#define PHYS_SDRAM_60X		0x00000000 /* SDRAM (60x Bus) */
#define PHYS_SDRAM_60X_SIZE	0x08000000 /* 128 MB */

#define PHYS_SDRAM_LOCAL	0x40000000 /* SDRAM (Local Bus) */
#define PHYS_SDRAM_LOCAL_SIZE	0x04000000 /* 64 MB */

#define PHYS_DPRAM_PCI		0xE8000000 /* DPRAM PPC/PCI */
#define PHYS_DPRAM_PCI_SIZE	0x00020000 /* 128 KB */

/*#define PHYS_DPRAM_PCI_SEM	0x04020000 / * DPRAM PPC/PCI Semaphore */
/*#define PHYS_DPRAM_PCI_SEM_SIZE	0x00000001 / * 1 Byte */

#define PHYS_DPRAM_SHARC	0xE8100000 /* DPRAM PPC/Sharc */
#define PHYS_DPRAM_SHARC_SIZE	0x00040000 /* 256 KB */

/*#define PHYS_DPRAM_SHARC_SEM	0x04140000 / * DPRAM PPC/Sharc Semaphore */
/*#define PHYS_DPRAM_SHARC_SEM_SIZE 0x00000001 / * 1 Byte */

#define PHYS_VIRTEX_REGISTER    0xE8300000 /* FPGA implemented register */
#define PHYS_VIRTEX_REGISTER_SIZE 0x00000100

#define PHYS_USB		0x04200000 /* USB Controller (60x Bus) */
#define PHYS_USB_SIZE		0x00000002 /* 2 Bytes */

#define PHYS_IMMR		0xF0000000 /* Internal Memory Mapped Reg. */

#define PHYS_FLASH		0xFF000000 /* Flash (60x Bus) */
#define PHYS_FLASH_SIZE		0x01000000 /* 16 MB */

#define CONFIG_SYS_IMMR		PHYS_IMMR

/*-----------------------------------------------------------------------
 * Reset Address
 *
 * In order to reset the CPU, U-Boot jumps to a special address which
 * causes a machine check exception. The default address for this is
 * CONFIG_SYS_MONITOR_BASE - sizeof (ulong), which might not always work, eg. when
 * testing the monitor in RAM using a JTAG debugger.
 *
 * Just set CONFIG_SYS_RESET_ADDRESS to an address that you know is sure to
 * cause a bus error on your hardware.
 */
#define CONFIG_SYS_RESET_ADDRESS	0x20000000

/*-----------------------------------------------------------------------
 * Hard Reset Configuration Words
 */

#if defined(CONFIG_SYS_RSD_BOOT_LOW)
#  define  CONFIG_SYS_RSD_HRCW_BOOT_FLAGS  (HRCW_CIP | HRCW_BMS)
#else
#  define  CONFIG_SYS_RSD_HRCW_BOOT_FLAGS  (0)
#endif /* defined(CONFIG_SYS_RSD_BOOT_LOW) */

/* get the HRCW ISB field from CONFIG_SYS_IMMR */
#define CONFIG_SYS_RSD_HRCW_IMMR ( ((CONFIG_SYS_IMMR & 0x10000000) >> 10) |\
			    ((CONFIG_SYS_IMMR & 0x01000000) >> 7)  |\
			    ((CONFIG_SYS_IMMR & 0x00100000) >> 4) )

#define CONFIG_SYS_HRCW_MASTER	(HRCW_L2CPC10 | \
			 HRCW_DPPC11 | \
			 CONFIG_SYS_RSD_HRCW_IMMR |\
			 HRCW_MMR00 | \
			 HRCW_APPC10 | \
			 HRCW_CS10PC00 | \
			 HRCW_MODCK_H0000 |\
			 CONFIG_SYS_RSD_HRCW_BOOT_FLAGS)

/* no slaves */
#define CONFIG_SYS_HRCW_SLAVE1	0
#define CONFIG_SYS_HRCW_SLAVE2	0
#define CONFIG_SYS_HRCW_SLAVE3	0
#define CONFIG_SYS_HRCW_SLAVE4	0
#define CONFIG_SYS_HRCW_SLAVE5	0
#define CONFIG_SYS_HRCW_SLAVE6	0
#define CONFIG_SYS_HRCW_SLAVE7	0

/*-----------------------------------------------------------------------
 * Definitions for initial stack pointer and data area (in DPRAM)
 */
#define CONFIG_SYS_INIT_RAM_ADDR	CONFIG_SYS_IMMR
#define	CONFIG_SYS_INIT_RAM_SIZE	0x4000	/* Size of used area in DPRAM	*/
#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
#define	CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET

/*-----------------------------------------------------------------------
 * Start addresses for the final memory configuration
 * (Set up by the startup code)
 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
 * Note also that the logic that sets CONFIG_SYS_RAMBOOT is platform dependend.
 */
#define	CONFIG_SYS_SDRAM_BASE		PHYS_SDRAM_60X
#define CONFIG_SYS_FLASH_BASE		PHYS_FLASH
/*#define	CONFIG_SYS_MONITOR_BASE	0x200000 */
#define	CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_FLASH_BASE
#if CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE
#define CONFIG_SYS_RAMBOOT
#endif
#define	CONFIG_SYS_MONITOR_LEN		(160 << 10)	/* Reserve 160 kB for Monitor	*/
#define	CONFIG_SYS_MALLOC_LEN		(128 << 10)	/* Reserve 128 kB for malloc()	*/

/*
 * For booting Linux, the board info and command line data
 * have to be in the first 8 MB of memory, since this is
 * the maximum mapped by the Linux kernel during initialization.
 */
#define	CONFIG_SYS_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux	*/

/*-----------------------------------------------------------------------
 * FLASH and environment organization
 */
#define CONFIG_SYS_MAX_FLASH_BANKS	2	/* max number of memory banks		*/
#define CONFIG_SYS_MAX_FLASH_SECT	63	/* max number of sectors on one chip	*/

#define CONFIG_SYS_FLASH_ERASE_TOUT	12000	/* Timeout for Flash Erase (in ms)	*/
#define CONFIG_SYS_FLASH_WRITE_TOUT	3000	/* Timeout for Flash Write (in ms)	*/

/* turn off NVRAM env feature */
#undef CONFIG_NVRAM_ENV

#define	CONFIG_ENV_IS_IN_FLASH	1
#define CONFIG_ENV_ADDR	(PHYS_FLASH + 0x28000)	/* Addr of Environment Sector	*/
#define CONFIG_ENV_SECT_SIZE	0x8000	/* Total Size of Environment Sector	*/

/*-----------------------------------------------------------------------
 * Cache Configuration
 */
#define CONFIG_SYS_CACHELINE_SIZE	32	/* For MPC8260 CPU			*/
#if defined(CONFIG_CMD_KGDB)
#define CONFIG_SYS_CACHELINE_SHIFT	5	/* log base 2 of the above value	*/
#endif

/*-----------------------------------------------------------------------
 * HIDx - Hardware Implementation-dependent Registers			 2-11
 *-----------------------------------------------------------------------
 * HID0 also contains cache control - initially enable both caches and
 * invalidate contents, then the final state leaves only the instruction
 * cache enabled. Note that Power-On and Hard reset invalidate the caches,
 * but Soft reset does not.
 *
 * HID1 has only read-only information - nothing to set.
 */
#define CONFIG_SYS_HID0_INIT	(HID0_ICE|HID0_DCE|HID0_ICFI|HID0_DCI|HID0_IFEM|HID0_ABE)
#define CONFIG_SYS_HID0_FINAL	(HID0_ICE|HID0_IFEM|HID0_ABE|HID0_EMCP)
#define CONFIG_SYS_HID2	0

/*-----------------------------------------------------------------------
 * RMR - Reset Mode Register
 *-----------------------------------------------------------------------
 */
#define CONFIG_SYS_RMR		0

/*-----------------------------------------------------------------------
 * BCR - Bus Configuration					 4-25
 *-----------------------------------------------------------------------
 */
#define CONFIG_SYS_BCR		0x100c0000

/*-----------------------------------------------------------------------
 * SIUMCR - SIU Module Configuration				 4-31
 *-----------------------------------------------------------------------
 */

#define CONFIG_SYS_SIUMCR	(SIUMCR_DPPC11 | SIUMCR_L2CPC10 | SIUMCR_APPC10 | \
					 SIUMCR_CS10PC01 | SIUMCR_BCTLC01)

/*-----------------------------------------------------------------------
 * SYPCR - System Protection Control				11-9
 * SYPCR can only be written once after reset!
 *-----------------------------------------------------------------------
 * Watchdog & Bus Monitor Timer max, 60x Bus Monitor enable
 */
#define CONFIG_SYS_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_PBME | SYPCR_LBME | \
			 SYPCR_SWRI | SYPCR_SWP)

/*-----------------------------------------------------------------------
 * TMCNTSC - Time Counter Status and Control			 4-40
 *-----------------------------------------------------------------------
 * Clear once per Second and Alarm Interrupt Status, Set 32KHz timersclk,
 * and enable Time Counter
 */
#define CONFIG_SYS_TMCNTSC	(TMCNTSC_SEC | TMCNTSC_ALR | TMCNTSC_TCF | TMCNTSC_TCE)

/*-----------------------------------------------------------------------
 * PISCR - Periodic Interrupt Status and Control		 4-42
 *-----------------------------------------------------------------------
 * Clear Periodic Interrupt Status, Set 32KHz timersclk, and enable
 * Periodic timer
 */
#define CONFIG_SYS_PISCR	(PISCR_PS|PISCR_PTF|PISCR_PTE)

/*-----------------------------------------------------------------------
 * SCCR - System Clock Control					 9-8
 *-----------------------------------------------------------------------
 */
#define CONFIG_SYS_SCCR	0x00000000

/*-----------------------------------------------------------------------
 * RCCR - RISC Controller Configuration				13-7
 *-----------------------------------------------------------------------
 */
#define CONFIG_SYS_RCCR	0

/*
 * Init Memory Controller:
 */

#define CONFIG_SYS_PSDMR	0x494D2452
#define CONFIG_SYS_LSDMR	0x49492552

/* Flash */
#define CONFIG_SYS_BR0_PRELIM	(PHYS_FLASH | BRx_V)
#define CONFIG_SYS_OR0_PRELIM	(P2SZ_TO_AM(PHYS_FLASH_SIZE) | \
			 ORxG_BCTLD | \
			 ORxG_SCY_5_CLK)

/* DPRAM to the PCI BUS on the protocol board */
#define CONFIG_SYS_BR1_PRELIM	(PHYS_DPRAM_PCI | BRx_V)
#define CONFIG_SYS_OR1_PRELIM	(P2SZ_TO_AM(PHYS_DPRAM_PCI_SIZE) | \
			 ORxG_ACS_DIV4)

/* 60x Bus SDRAM */
#define CONFIG_SYS_BR2_PRELIM	(PHYS_SDRAM_60X | BRx_MS_SDRAM_P | BRx_V)
#define CONFIG_SYS_OR2_PRELIM	(ORxS_SIZE_TO_AM(PHYS_SDRAM_60X_SIZE) | \
			 ORxS_BPD_4 | \
			 ORxS_ROWST_PBI1_A2 | \
			 ORxS_NUMR_13 | \
			 ORxS_IBID)

/* Virtex-FPGA - Register */
#define CONFIG_SYS_BR3_PRELIM  (PHYS_VIRTEX_REGISTER | BRx_V)
#define CONFIG_SYS_OR3_PRELIM  (ORxS_SIZE_TO_AM(PHYS_VIRTEX_REGISTER_SIZE) | \
			 ORxG_SCY_1_CLK | \
			 ORxG_ACS_DIV2 | \
			 ORxG_CSNT )

/* local bus SDRAM */
#define CONFIG_SYS_BR4_PRELIM	(PHYS_SDRAM_LOCAL | BRx_PS_32 | BRx_MS_SDRAM_L | BRx_V)
#define CONFIG_SYS_OR4_PRELIM	(ORxS_SIZE_TO_AM(PHYS_SDRAM_LOCAL_SIZE) | \
			 ORxS_BPD_4 | \
			 ORxS_ROWST_PBI1_A4 | \
			 ORxS_NUMR_13)

/* DPRAM to the Sharc-Bus on the protocol board */
#define CONFIG_SYS_BR5_PRELIM	(PHYS_DPRAM_SHARC | BRx_V)
#define CONFIG_SYS_OR5_PRELIM	(P2SZ_TO_AM(PHYS_DPRAM_SHARC_SIZE) | \
			 ORxG_ACS_DIV4)

#endif	/* __CONFIG_H */
Commit	Line	Data
e2211743 WD	1	/*
	2	* (C) Copyright 2000
	3	* Murray Jensen <Murray.Jensen@cmst.csiro.au>
	4	*
	5	* (C) Copyright 2000
	6	* Sysgo Real-Time Solutions, GmbH <www.elinos.com>
	7	* Marius Groeger <mgroeger@sysgo.de>
	8	*
	9	* Configuation settings for the R&S Protocol Board board.
	10	*
1a459660	11	* SPDX-License-Identifier: GPL-2.0+
e2211743 WD	12	*/
	13
	14	#ifndef __CONFIG_H
	15	#define __CONFIG_H
	16
	17	/*
	18	* High Level Configuration Options
	19	* (easy to change)
	20	*/
	21
	22	#define CONFIG_MPC8260 1 /* This is an MPC8260 CPU */
	23	#define CONFIG_RSD_PROTO 1 /* on a R&S Protocol Board */
9c4c5ae3	24	#define CONFIG_CPM2 1 /* Has a CPM2 */
e2211743	25
2ae18241	26	#define CONFIG_SYS_TEXT_BASE 0xff000000
2ced53e1	27	#define CONFIG_SYS_LDSCRIPT "board/rsdproto/u-boot.lds"
2ae18241	28
c837dcb1 WD	29	#define CONFIG_MISC_INIT_F 1 /* Use misc_init_f() */
c837dcb1 WD	30
e2211743 WD	31	/*
	32	* select serial console configuration
	33	*
	34	* if either CONFIG_CONS_ON_SMC or CONFIG_CONS_ON_SCC is selected, then
	35	* CONFIG_CONS_INDEX must be set to the channel number (1-2 for SMC, 1-4
	36	* for SCC).
	37	*
	38	* if CONFIG_CONS_NONE is defined, then the serial console routines must
	39	* defined elsewhere.
	40	*/
	41	#undef CONFIG_CONS_ON_SMC /* define if console on SMC */
	42	#define CONFIG_CONS_ON_SCC /* define if console on SCC */
53677ef1	43	#undef CONFIG_CONS_NONE /* define if console on neither */
e2211743 WD	44	#define CONFIG_CONS_INDEX 1 /* which SMC/SCC channel for console */
	45
	46	/*
	47	* select ethernet configuration
	48	*
	49	* if either CONFIG_ETHER_ON_SCC or CONFIG_ETHER_ON_FCC is selected, then
	50	* CONFIG_ETHER_INDEX must be set to the channel number (1-4 for SCC, 1-3
	51	* for FCC)
	52	*
	53	* if CONFIG_ETHER_NONE is defined, then either the ethernet routines must be
639221c7	54	* defined elsewhere (as for the console), or CONFIG_CMD_NET must be unset.
e2211743 WD	55	*/
	56	#undef CONFIG_ETHER_ON_SCC /* define if ethernet on SCC */
	57	#define CONFIG_ETHER_ON_FCC /* define if ethernet on FCC */
	58	#undef CONFIG_ETHER_NONE /* define if ethernet on neither */
	59	#define CONFIG_ETHER_INDEX 2 /* which SCC/FCC channel for ethernet */
	60
	61	#if (CONFIG_ETHER_INDEX == 2)
	62
	63	/*
	64	* - Rx-CLK is CLK13
	65	* - Tx-CLK is CLK14
	66	* - Select bus for bd/buffers (see 28-13)
	67	* - Enable Full Duplex in FSMR
	68	*/
d4590da4 MF	69	# define CONFIG_SYS_CMXFCR_MASK2 (CMXFCR_FC2 \| CMXFCR_RF2CS_MSK \| CMXFCR_TF2CS_MSK)
d4590da4 MF	70	# define CONFIG_SYS_CMXFCR_VALUE2 (CMXFCR_RF2CS_CLK13 \| CMXFCR_TF2CS_CLK14)
6d0f6bcf JCPV	71	# define CONFIG_SYS_CPMFCR_RAMTYPE (0)
6d0f6bcf JCPV	72	# define CONFIG_SYS_FCC_PSMR (FCC_PSMR_FDE \| FCC_PSMR_LPB)
e2211743 WD	73
	74	#endif /* CONFIG_ETHER_INDEX */
	75
	76
	77	/* allow to overwrite serial and ethaddr */
	78	#define CONFIG_ENV_OVERWRITE
	79
	80	/* enable I2C */
53677ef1	81	#define CONFIG_HARD_I2C 1 /* I2C with hardware support */
6d0f6bcf JCPV	82	#define CONFIG_SYS_I2C_SPEED 50000 /* I2C speed and slave address */
6d0f6bcf JCPV	83	#define CONFIG_SYS_I2C_SLAVE 0x30
e2211743 WD	84
	85
	86	/* system clock rate (CLKIN) - equal to the 60x and local bus speed */
	87	#define CONFIG_8260_CLKIN 50000000 /* in Hz */
	88
	89	#define CONFIG_BAUDRATE 115200
	90
90cc3eb6	91
079a136c JL	92	/*
	93	* BOOTP options
	94	*/
	95	#define CONFIG_BOOTP_BOOTFILESIZE
	96	#define CONFIG_BOOTP_BOOTPATH
	97	#define CONFIG_BOOTP_GATEWAY
	98	#define CONFIG_BOOTP_HOSTNAME
	99
	100
90cc3eb6 JL	101	/*
	102	* Command line configuration.
	103	*/
	104	#include <config_cmd_default.h>
	105
	106	#undef CONFIG_CMD_KGDB
	107
e2211743 WD	108
	109	/* Define this if you want to boot from 0x00000100. If you don't define
	110	* this, you will need to program the bootloader to 0xfff00000, and
	111	* get the hardware reset config words at 0xfe000000. The simplest
	112	* way to do that is to program the bootloader at both addresses.
	113	* It is suggested that you just let U-Boot live at 0x00000000.
	114	*/
6d0f6bcf	115	#define CONFIG_SYS_RSD_BOOT_LOW 1
e2211743	116
e2211743	117	#define CONFIG_BOOTDELAY 5
53677ef1	118	#define CONFIG_BOOTARGS "devfs=mount root=ramfs"
e2211743 WD	119	#define CONFIG_ETHADDR 08:00:3e:26:0a:5a
	120	#define CONFIG_NETMASK 255.255.0.0
	121
90cc3eb6	122	#if defined(CONFIG_CMD_KGDB)
e2211743 WD	123	#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
	124	#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
	125	#endif
	126
	127	/*
	128	* Miscellaneous configurable options
	129	*/
6d0f6bcf JCPV	130	#define CONFIG_SYS_LONGHELP /* undef to save memory */
6d0f6bcf JCPV	131	#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
90cc3eb6	132	#if defined(CONFIG_CMD_KGDB)
6d0f6bcf	133	#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
e2211743	134	#else
6d0f6bcf	135	#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
e2211743	136	#endif
6d0f6bcf JCPV	137	#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
	138	#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
	139	#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
e2211743	140
6d0f6bcf JCPV	141	#define CONFIG_SYS_MEMTEST_START 0x00400000 /* memtest works on */
6d0f6bcf JCPV	142	#define CONFIG_SYS_MEMTEST_END 0x01c00000 /* 4 ... 28 MB in DRAM */
e2211743	143
6d0f6bcf	144	#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
e2211743	145
6d0f6bcf	146	#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */
e2211743	147
e2211743 WD	148	/*
	149	* Low Level Configuration Settings
	150	* (address mappings, register initial values, etc.)
	151	* You should know what you are doing if you make changes here.
	152	*/
	153
	154	/*-----------------------------------------------------------------------
	155	* Physical Memory Map
	156	*/
	157	#define PHYS_SDRAM_60X 0x00000000 /* SDRAM (60x Bus) */
	158	#define PHYS_SDRAM_60X_SIZE 0x08000000 /* 128 MB */
	159
	160	#define PHYS_SDRAM_LOCAL 0x40000000 /* SDRAM (Local Bus) */
	161	#define PHYS_SDRAM_LOCAL_SIZE 0x04000000 /* 64 MB */
	162
53677ef1 WD	163	#define PHYS_DPRAM_PCI 0xE8000000 /* DPRAM PPC/PCI */
53677ef1 WD	164	#define PHYS_DPRAM_PCI_SIZE 0x00020000 /* 128 KB */
e2211743 WD	165
	166	/#define PHYS_DPRAM_PCI_SEM 0x04020000 / DPRAM PPC/PCI Semaphore */
	167	/#define PHYS_DPRAM_PCI_SEM_SIZE 0x00000001 / 1 Byte */
	168
53677ef1 WD	169	#define PHYS_DPRAM_SHARC 0xE8100000 /* DPRAM PPC/Sharc */
53677ef1 WD	170	#define PHYS_DPRAM_SHARC_SIZE 0x00040000 /* 256 KB */
e2211743 WD	171
	172	/#define PHYS_DPRAM_SHARC_SEM 0x04140000 / DPRAM PPC/Sharc Semaphore */
	173	/#define PHYS_DPRAM_SHARC_SEM_SIZE 0x00000001 / 1 Byte */
	174
	175	#define PHYS_VIRTEX_REGISTER 0xE8300000 /* FPGA implemented register */
	176	#define PHYS_VIRTEX_REGISTER_SIZE 0x00000100
	177
	178	#define PHYS_USB 0x04200000 /* USB Controller (60x Bus) */
	179	#define PHYS_USB_SIZE 0x00000002 /* 2 Bytes */
	180
	181	#define PHYS_IMMR 0xF0000000 /* Internal Memory Mapped Reg. */
	182
	183	#define PHYS_FLASH 0xFF000000 /* Flash (60x Bus) */
	184	#define PHYS_FLASH_SIZE 0x01000000 /* 16 MB */
	185
6d0f6bcf	186	#define CONFIG_SYS_IMMR PHYS_IMMR
e2211743 WD	187
	188	/*-----------------------------------------------------------------------
	189	* Reset Address
	190	*
	191	* In order to reset the CPU, U-Boot jumps to a special address which
	192	* causes a machine check exception. The default address for this is
6d0f6bcf	193	* CONFIG_SYS_MONITOR_BASE - sizeof (ulong), which might not always work, eg. when
e2211743 WD	194	* testing the monitor in RAM using a JTAG debugger.
e2211743 WD	195	*
6d0f6bcf	196	* Just set CONFIG_SYS_RESET_ADDRESS to an address that you know is sure to
e2211743 WD	197	* cause a bus error on your hardware.
e2211743 WD	198	*/
6d0f6bcf	199	#define CONFIG_SYS_RESET_ADDRESS 0x20000000
e2211743 WD	200
	201	/*-----------------------------------------------------------------------
	202	* Hard Reset Configuration Words
	203	*/
	204
6d0f6bcf JCPV	205	#if defined(CONFIG_SYS_RSD_BOOT_LOW)
6d0f6bcf JCPV	206	# define CONFIG_SYS_RSD_HRCW_BOOT_FLAGS (HRCW_CIP \| HRCW_BMS)
e2211743	207	#else
6d0f6bcf JCPV	208	# define CONFIG_SYS_RSD_HRCW_BOOT_FLAGS (0)
6d0f6bcf JCPV	209	#endif /* defined(CONFIG_SYS_RSD_BOOT_LOW) */
e2211743	210
6d0f6bcf JCPV	211	/* get the HRCW ISB field from CONFIG_SYS_IMMR */
	212	#define CONFIG_SYS_RSD_HRCW_IMMR ( ((CONFIG_SYS_IMMR & 0x10000000) >> 10) \|\
	213	((CONFIG_SYS_IMMR & 0x01000000) >> 7) \|\
	214	((CONFIG_SYS_IMMR & 0x00100000) >> 4) )
e2211743	215
6d0f6bcf	216	#define CONFIG_SYS_HRCW_MASTER (HRCW_L2CPC10 \| \
e2211743	217	HRCW_DPPC11 \| \
6d0f6bcf	218	CONFIG_SYS_RSD_HRCW_IMMR \|\
8bde7f77 WD	219	HRCW_MMR00 \| \
	220	HRCW_APPC10 \| \
	221	HRCW_CS10PC00 \| \
	222	HRCW_MODCK_H0000 \|\
6d0f6bcf	223	CONFIG_SYS_RSD_HRCW_BOOT_FLAGS)
e2211743 WD	224
e2211743 WD	225	/* no slaves */
6d0f6bcf JCPV	226	#define CONFIG_SYS_HRCW_SLAVE1 0
	227	#define CONFIG_SYS_HRCW_SLAVE2 0
	228	#define CONFIG_SYS_HRCW_SLAVE3 0
	229	#define CONFIG_SYS_HRCW_SLAVE4 0
	230	#define CONFIG_SYS_HRCW_SLAVE5 0
	231	#define CONFIG_SYS_HRCW_SLAVE6 0
	232	#define CONFIG_SYS_HRCW_SLAVE7 0
e2211743 WD	233
	234	/*-----------------------------------------------------------------------
	235	* Definitions for initial stack pointer and data area (in DPRAM)
	236	*/
6d0f6bcf	237	#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR
553f0982	238	#define CONFIG_SYS_INIT_RAM_SIZE 0x4000 /* Size of used area in DPRAM */
25ddd1fb	239	#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
6d0f6bcf	240	#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
e2211743 WD	241
	242	/*-----------------------------------------------------------------------
	243	* Start addresses for the final memory configuration
	244	* (Set up by the startup code)
6d0f6bcf JCPV	245	* Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
6d0f6bcf JCPV	246	* Note also that the logic that sets CONFIG_SYS_RAMBOOT is platform dependend.
e2211743	247	*/
6d0f6bcf JCPV	248	#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_60X
	249	#define CONFIG_SYS_FLASH_BASE PHYS_FLASH
	250	/#define CONFIG_SYS_MONITOR_BASE 0x200000 /
	251	#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
	252	#if CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE
	253	#define CONFIG_SYS_RAMBOOT
e2211743	254	#endif
6d0f6bcf JCPV	255	#define CONFIG_SYS_MONITOR_LEN (160 << 10) /* Reserve 160 kB for Monitor */
6d0f6bcf JCPV	256	#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
e2211743 WD	257
	258	/*
	259	* For booting Linux, the board info and command line data
	260	* have to be in the first 8 MB of memory, since this is
	261	* the maximum mapped by the Linux kernel during initialization.
	262	*/
6d0f6bcf	263	#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
e2211743 WD	264
	265	/*-----------------------------------------------------------------------
	266	* FLASH and environment organization
	267	*/
6d0f6bcf JCPV	268	#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of memory banks */
6d0f6bcf JCPV	269	#define CONFIG_SYS_MAX_FLASH_SECT 63 /* max number of sectors on one chip */
e2211743	270
6d0f6bcf JCPV	271	#define CONFIG_SYS_FLASH_ERASE_TOUT 12000 /* Timeout for Flash Erase (in ms) */
6d0f6bcf JCPV	272	#define CONFIG_SYS_FLASH_WRITE_TOUT 3000 /* Timeout for Flash Write (in ms) */
e2211743 WD	273
	274	/* turn off NVRAM env feature */
	275	#undef CONFIG_NVRAM_ENV
	276
5a1aceb0	277	#define CONFIG_ENV_IS_IN_FLASH 1
0e8d1586 JCPV	278	#define CONFIG_ENV_ADDR (PHYS_FLASH + 0x28000) /* Addr of Environment Sector */
0e8d1586 JCPV	279	#define CONFIG_ENV_SECT_SIZE 0x8000 /* Total Size of Environment Sector */
e2211743 WD	280
	281	/*-----------------------------------------------------------------------
	282	* Cache Configuration
	283	*/
6d0f6bcf	284	#define CONFIG_SYS_CACHELINE_SIZE 32 /* For MPC8260 CPU */
90cc3eb6	285	#if defined(CONFIG_CMD_KGDB)
6d0f6bcf	286	#define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */
e2211743 WD	287	#endif
	288
	289	/*-----------------------------------------------------------------------
	290	* HIDx - Hardware Implementation-dependent Registers 2-11
	291	*-----------------------------------------------------------------------
	292	* HID0 also contains cache control - initially enable both caches and
	293	* invalidate contents, then the final state leaves only the instruction
	294	* cache enabled. Note that Power-On and Hard reset invalidate the caches,
	295	* but Soft reset does not.
	296	*
	297	* HID1 has only read-only information - nothing to set.
	298	*/
6d0f6bcf JCPV	299	#define CONFIG_SYS_HID0_INIT (HID0_ICE\|HID0_DCE\|HID0_ICFI\|HID0_DCI\|HID0_IFEM\|HID0_ABE)
	300	#define CONFIG_SYS_HID0_FINAL (HID0_ICE\|HID0_IFEM\|HID0_ABE\|HID0_EMCP)
	301	#define CONFIG_SYS_HID2 0
e2211743 WD	302
	303	/*-----------------------------------------------------------------------
	304	* RMR - Reset Mode Register
	305	*-----------------------------------------------------------------------
	306	*/
6d0f6bcf	307	#define CONFIG_SYS_RMR 0
e2211743 WD	308
	309	/*-----------------------------------------------------------------------
	310	* BCR - Bus Configuration 4-25
	311	*-----------------------------------------------------------------------
	312	*/
6d0f6bcf	313	#define CONFIG_SYS_BCR 0x100c0000
e2211743 WD	314
	315	/*-----------------------------------------------------------------------
	316	* SIUMCR - SIU Module Configuration 4-31
	317	*-----------------------------------------------------------------------
	318	*/
	319
6d0f6bcf	320	#define CONFIG_SYS_SIUMCR (SIUMCR_DPPC11 \| SIUMCR_L2CPC10 \| SIUMCR_APPC10 \| \
e2211743 WD	321	SIUMCR_CS10PC01 \| SIUMCR_BCTLC01)
	322
	323	/*-----------------------------------------------------------------------
	324	* SYPCR - System Protection Control 11-9
	325	* SYPCR can only be written once after reset!
	326	*-----------------------------------------------------------------------
	327	* Watchdog & Bus Monitor Timer max, 60x Bus Monitor enable
	328	*/
6d0f6bcf	329	#define CONFIG_SYS_SYPCR (SYPCR_SWTC \| SYPCR_BMT \| SYPCR_PBME \| SYPCR_LBME \| \
e2211743 WD	330	SYPCR_SWRI \| SYPCR_SWP)
	331
	332	/*-----------------------------------------------------------------------
	333	* TMCNTSC - Time Counter Status and Control 4-40
	334	*-----------------------------------------------------------------------
	335	* Clear once per Second and Alarm Interrupt Status, Set 32KHz timersclk,
	336	* and enable Time Counter
	337	*/
6d0f6bcf	338	#define CONFIG_SYS_TMCNTSC (TMCNTSC_SEC \| TMCNTSC_ALR \| TMCNTSC_TCF \| TMCNTSC_TCE)
e2211743 WD	339
	340	/*-----------------------------------------------------------------------
	341	* PISCR - Periodic Interrupt Status and Control 4-42
	342	*-----------------------------------------------------------------------
	343	* Clear Periodic Interrupt Status, Set 32KHz timersclk, and enable
	344	* Periodic timer
	345	*/
6d0f6bcf	346	#define CONFIG_SYS_PISCR (PISCR_PS\|PISCR_PTF\|PISCR_PTE)
e2211743 WD	347
	348	/*-----------------------------------------------------------------------
	349	* SCCR - System Clock Control 9-8
	350	*-----------------------------------------------------------------------
	351	*/
6d0f6bcf	352	#define CONFIG_SYS_SCCR 0x00000000
e2211743 WD	353
	354	/*-----------------------------------------------------------------------
	355	* RCCR - RISC Controller Configuration 13-7
	356	*-----------------------------------------------------------------------
	357	*/
6d0f6bcf	358	#define CONFIG_SYS_RCCR 0
e2211743 WD	359
	360	/*
	361	* Init Memory Controller:
	362	*/
	363
6d0f6bcf JCPV	364	#define CONFIG_SYS_PSDMR 0x494D2452
6d0f6bcf JCPV	365	#define CONFIG_SYS_LSDMR 0x49492552
e2211743 WD	366
e2211743 WD	367	/* Flash */
6d0f6bcf JCPV	368	#define CONFIG_SYS_BR0_PRELIM (PHYS_FLASH \| BRx_V)
6d0f6bcf JCPV	369	#define CONFIG_SYS_OR0_PRELIM (P2SZ_TO_AM(PHYS_FLASH_SIZE) \| \
e2211743 WD	370	ORxG_BCTLD \| \
	371	ORxG_SCY_5_CLK)
	372
	373	/* DPRAM to the PCI BUS on the protocol board */
6d0f6bcf JCPV	374	#define CONFIG_SYS_BR1_PRELIM (PHYS_DPRAM_PCI \| BRx_V)
6d0f6bcf JCPV	375	#define CONFIG_SYS_OR1_PRELIM (P2SZ_TO_AM(PHYS_DPRAM_PCI_SIZE) \| \
e2211743 WD	376	ORxG_ACS_DIV4)
	377
	378	/* 60x Bus SDRAM */
6d0f6bcf JCPV	379	#define CONFIG_SYS_BR2_PRELIM (PHYS_SDRAM_60X \| BRx_MS_SDRAM_P \| BRx_V)
6d0f6bcf JCPV	380	#define CONFIG_SYS_OR2_PRELIM (ORxS_SIZE_TO_AM(PHYS_SDRAM_60X_SIZE) \| \
e2211743 WD	381	ORxS_BPD_4 \| \
	382	ORxS_ROWST_PBI1_A2 \| \
	383	ORxS_NUMR_13 \| \
	384	ORxS_IBID)
	385
	386	/* Virtex-FPGA - Register */
6d0f6bcf JCPV	387	#define CONFIG_SYS_BR3_PRELIM (PHYS_VIRTEX_REGISTER \| BRx_V)
6d0f6bcf JCPV	388	#define CONFIG_SYS_OR3_PRELIM (ORxS_SIZE_TO_AM(PHYS_VIRTEX_REGISTER_SIZE) \| \
8bde7f77 WD	389	ORxG_SCY_1_CLK \| \
	390	ORxG_ACS_DIV2 \| \
	391	ORxG_CSNT )
e2211743 WD	392
e2211743 WD	393	/* local bus SDRAM */
6d0f6bcf JCPV	394	#define CONFIG_SYS_BR4_PRELIM (PHYS_SDRAM_LOCAL \| BRx_PS_32 \| BRx_MS_SDRAM_L \| BRx_V)
6d0f6bcf JCPV	395	#define CONFIG_SYS_OR4_PRELIM (ORxS_SIZE_TO_AM(PHYS_SDRAM_LOCAL_SIZE) \| \
e2211743 WD	396	ORxS_BPD_4 \| \
	397	ORxS_ROWST_PBI1_A4 \| \
	398	ORxS_NUMR_13)
	399
	400	/* DPRAM to the Sharc-Bus on the protocol board */
6d0f6bcf JCPV	401	#define CONFIG_SYS_BR5_PRELIM (PHYS_DPRAM_SHARC \| BRx_V)
6d0f6bcf JCPV	402	#define CONFIG_SYS_OR5_PRELIM (P2SZ_TO_AM(PHYS_DPRAM_SHARC_SIZE) \| \
e2211743 WD	403	ORxG_ACS_DIV4)
e2211743 WD	404
e2211743	405	#endif /* __CONFIG_H */