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fe8c2806 WD |
1 | /* |
2 | * (C) Copyright 2000 | |
3 | * Murray Jensen <Murray.Jensen@cmst.csiro.au> | |
4 | * | |
5 | * (C) Copyright 2000 | |
6 | * Sysgo Real-Time Solutions, GmbH <www.elinos.com> | |
7 | * Marius Groeger <mgroeger@sysgo.de> | |
8 | * | |
9 | * (C) Copyright 2001 | |
10 | * Advent Networks, Inc. <http://www.adventnetworks.com> | |
11 | * Jay Monkman <jtm@smoothsmoothie.com> | |
12 | * | |
13 | * Configuration settings for the WindRiver SBC8260 board. | |
14 | * See http://www.windriver.com/products/html/sbc8260.html | |
15 | * | |
16 | * See file CREDITS for list of people who contributed to this | |
17 | * project. | |
18 | * | |
19 | * This program is free software; you can redistribute it and/or | |
20 | * modify it under the terms of the GNU General Public License as | |
21 | * published by the Free Software Foundation; either version 2 of | |
22 | * the License, or (at your option) any later version. | |
23 | * | |
24 | * This program is distributed in the hope that it will be useful, | |
25 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
26 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
27 | * GNU General Public License for more details. | |
28 | * | |
29 | * You should have received a copy of the GNU General Public License | |
30 | * along with this program; if not, write to the Free Software | |
31 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | |
32 | * MA 02111-1307 USA | |
33 | */ | |
34 | ||
35 | #ifndef __CONFIG_H | |
36 | #define __CONFIG_H | |
37 | ||
2ae18241 WD |
38 | #define CONFIG_SYS_TEXT_BASE 0x40000000 |
39 | ||
fe8c2806 WD |
40 | #undef DEBUG_BOOTP_EXT /* Debug received vendor fields */ |
41 | ||
78137c3c WD |
42 | #undef CONFIG_LOGBUFFER /* External logbuffer support */ |
43 | ||
fe8c2806 WD |
44 | /***************************************************************************** |
45 | * | |
46 | * These settings must match the way _your_ board is set up | |
47 | * | |
48 | *****************************************************************************/ | |
49 | ||
50 | /* What is the oscillator's (UX2) frequency in Hz? */ | |
51 | #define CONFIG_8260_CLKIN 66666600 | |
52 | ||
53 | /*----------------------------------------------------------------------- | |
54 | * MODCK_H & MODCLK[1-3] - Ref: Section 9.2 in MPC8206 User Manual | |
55 | *----------------------------------------------------------------------- | |
56 | * What should MODCK_H be? It is dependent on the oscillator | |
57 | * frequency, MODCK[1-3], and desired CPM and core frequencies. | |
58 | * Here are some example values (all frequencies are in MHz): | |
59 | * | |
60 | * MODCK_H MODCK[1-3] Osc CPM Core S2-6 S2-7 S2-8 | |
61 | * ------- ---------- --- --- ---- ----- ----- ----- | |
62 | * 0x1 0x5 33 100 133 Open Close Open | |
63 | * 0x1 0x6 33 100 166 Open Open Close | |
64 | * 0x1 0x7 33 100 200 Open Open Open | |
65 | * | |
66 | * 0x2 0x2 33 133 133 Close Open Close | |
67 | * 0x2 0x3 33 133 166 Close Open Open | |
68 | * 0x2 0x4 33 133 200 Open Close Close | |
69 | * 0x2 0x5 33 133 233 Open Close Open | |
70 | * 0x2 0x6 33 133 266 Open Open Close | |
71 | * | |
72 | * 0x5 0x5 66 133 133 Open Close Open | |
73 | * 0x5 0x6 66 133 166 Open Open Close | |
74 | * 0x5 0x7 66 133 200 Open Open Open | |
75 | * 0x6 0x0 66 133 233 Close Close Close | |
76 | * 0x6 0x1 66 133 266 Close Close Open | |
77 | * 0x6 0x2 66 133 300 Close Open Close | |
78 | */ | |
6d0f6bcf | 79 | #define CONFIG_SYS_SBC_MODCK_H 0x05 |
fe8c2806 WD |
80 | |
81 | /* Define this if you want to boot from 0x00000100. If you don't define | |
82 | * this, you will need to program the bootloader to 0xfff00000, and | |
83 | * get the hardware reset config words at 0xfe000000. The simplest | |
84 | * way to do that is to program the bootloader at both addresses. | |
85 | * It is suggested that you just let U-Boot live at 0x00000000. | |
86 | */ | |
6d0f6bcf | 87 | #define CONFIG_SYS_SBC_BOOT_LOW 1 |
fe8c2806 WD |
88 | |
89 | /* What should the base address of the main FLASH be and how big is | |
14d0a02a | 90 | * it (in MBytes)? This must contain CONFIG_SYS_TEXT_BASE from board/sacsng/config.mk |
fe8c2806 WD |
91 | * The main FLASH is whichever is connected to *CS0. |
92 | */ | |
6d0f6bcf JCPV |
93 | #define CONFIG_SYS_FLASH0_BASE 0x40000000 |
94 | #define CONFIG_SYS_FLASH0_SIZE 2 | |
fe8c2806 WD |
95 | |
96 | /* What should the base address of the secondary FLASH be and how big | |
97 | * is it (in Mbytes)? The secondary FLASH is whichever is connected | |
98 | * to *CS6. | |
99 | */ | |
6d0f6bcf JCPV |
100 | #define CONFIG_SYS_FLASH1_BASE 0x60000000 |
101 | #define CONFIG_SYS_FLASH1_SIZE 2 | |
fe8c2806 WD |
102 | |
103 | /* Define CONFIG_VERY_BIG_RAM to allow use of SDRAMs larger than 256MBytes | |
104 | */ | |
105 | #define CONFIG_VERY_BIG_RAM 1 | |
106 | ||
107 | /* What should be the base address of SDRAM DIMM and how big is | |
108 | * it (in Mbytes)? This will normally auto-configure via the SPD. | |
109 | */ | |
6d0f6bcf JCPV |
110 | #define CONFIG_SYS_SDRAM0_BASE 0x00000000 |
111 | #define CONFIG_SYS_SDRAM0_SIZE 64 | |
fe8c2806 WD |
112 | |
113 | /* | |
114 | * Memory map example with 64 MB DIMM: | |
115 | * | |
116 | * 0x0000 0000 Exception Vector code, 8k | |
117 | * : | |
118 | * 0x0000 1FFF | |
119 | * 0x0000 2000 Free for Application Use | |
120 | * : | |
121 | * : | |
122 | * | |
123 | * : | |
124 | * : | |
125 | * 0x03F5 FF30 Monitor Stack (Growing downward) | |
126 | * Monitor Stack Buffer (0x80) | |
127 | * 0x03F5 FFB0 Board Info Data | |
128 | * 0x03F6 0000 Malloc Arena | |
0e8d1586 | 129 | * : CONFIG_ENV_SECT_SIZE, 16k |
6d0f6bcf | 130 | * : CONFIG_SYS_MALLOC_LEN, 128k |
fe8c2806 | 131 | * 0x03FC 0000 RAM Copy of Monitor Code |
6d0f6bcf JCPV |
132 | * : CONFIG_SYS_MONITOR_LEN, 256k |
133 | * 0x03FF FFFF [End of RAM], CONFIG_SYS_SDRAM_SIZE - 1 | |
fe8c2806 WD |
134 | */ |
135 | ||
6d0f6bcf JCPV |
136 | #define CONFIG_POST (CONFIG_SYS_POST_MEMORY | \ |
137 | CONFIG_SYS_POST_CPU) | |
fe8c2806 WD |
138 | |
139 | ||
140 | /* | |
141 | * select serial console configuration | |
142 | * | |
143 | * if either CONFIG_CONS_ON_SMC or CONFIG_CONS_ON_SCC is selected, then | |
144 | * CONFIG_CONS_INDEX must be set to the channel number (1-2 for SMC, 1-4 | |
145 | * for SCC). | |
146 | * | |
147 | * if CONFIG_CONS_NONE is defined, then the serial console routines must | |
148 | * defined elsewhere. | |
149 | */ | |
150 | #define CONFIG_CONS_ON_SMC 1 /* define if console on SMC */ | |
151 | #undef CONFIG_CONS_ON_SCC /* define if console on SCC */ | |
152 | #undef CONFIG_CONS_NONE /* define if console on neither */ | |
153 | #define CONFIG_CONS_INDEX 1 /* which SMC/SCC channel for console */ | |
154 | ||
155 | /* | |
156 | * select ethernet configuration | |
157 | * | |
158 | * if either CONFIG_ETHER_ON_SCC or CONFIG_ETHER_ON_FCC is selected, then | |
159 | * CONFIG_ETHER_INDEX must be set to the channel number (1-4 for SCC, 1-3 | |
160 | * for FCC) | |
161 | * | |
162 | * if CONFIG_ETHER_NONE is defined, then either the ethernet routines must be | |
639221c7 | 163 | * defined elsewhere (as for the console), or CONFIG_CMD_NET must be unset. |
fe8c2806 WD |
164 | */ |
165 | ||
166 | #undef CONFIG_ETHER_ON_SCC | |
167 | #define CONFIG_ETHER_ON_FCC | |
168 | #undef CONFIG_ETHER_NONE /* define if ethernet on neither */ | |
169 | ||
170 | #ifdef CONFIG_ETHER_ON_SCC | |
171 | #define CONFIG_ETHER_INDEX 1 /* which SCC/FCC channel for ethernet */ | |
172 | #endif /* CONFIG_ETHER_ON_SCC */ | |
173 | ||
174 | #ifdef CONFIG_ETHER_ON_FCC | |
175 | #define CONFIG_ETHER_INDEX 2 /* which SCC/FCC channel for ethernet */ | |
78137c3c | 176 | #undef CONFIG_ETHER_LOOPBACK_TEST /* Ethernet external loopback test */ |
fe8c2806 WD |
177 | #define CONFIG_MII /* MII PHY management */ |
178 | #define CONFIG_BITBANGMII /* bit-bang MII PHY management */ | |
179 | /* | |
180 | * Port pins used for bit-banged MII communictions (if applicable). | |
181 | */ | |
182 | ||
183 | #define MDIO_PORT 2 /* Port A=0, B=1, C=2, D=3 */ | |
be225442 LCM |
184 | #define MDIO_DECLARE volatile ioport_t *iop = ioport_addr ( \ |
185 | (immap_t *) CONFIG_SYS_IMMR, MDIO_PORT ) | |
186 | #define MDC_DECLARE MDIO_DECLARE | |
187 | ||
fe8c2806 WD |
188 | #define MDIO_ACTIVE (iop->pdir |= 0x40000000) |
189 | #define MDIO_TRISTATE (iop->pdir &= ~0x40000000) | |
190 | #define MDIO_READ ((iop->pdat & 0x40000000) != 0) | |
191 | ||
192 | #define MDIO(bit) if(bit) iop->pdat |= 0x40000000; \ | |
193 | else iop->pdat &= ~0x40000000 | |
194 | ||
195 | #define MDC(bit) if(bit) iop->pdat |= 0x80000000; \ | |
196 | else iop->pdat &= ~0x80000000 | |
197 | ||
198 | #define MIIDELAY udelay(50) | |
199 | #endif /* CONFIG_ETHER_ON_FCC */ | |
200 | ||
201 | #if defined(CONFIG_ETHER_ON_SCC) && (CONFIG_ETHER_INDEX == 1) | |
202 | ||
203 | /* | |
204 | * - RX clk is CLK11 | |
205 | * - TX clk is CLK12 | |
206 | */ | |
6d0f6bcf | 207 | # define CONFIG_SYS_CMXSCR_VALUE (CMXSCR_RS1CS_CLK11 | CMXSCR_TS1CS_CLK12) |
fe8c2806 WD |
208 | |
209 | #elif defined(CONFIG_ETHER_ON_FCC) && (CONFIG_ETHER_INDEX == 2) | |
210 | ||
211 | /* | |
212 | * - Rx-CLK is CLK13 | |
213 | * - Tx-CLK is CLK14 | |
214 | * - Select bus for bd/buffers (see 28-13) | |
215 | * - Enable Full Duplex in FSMR | |
216 | */ | |
6d0f6bcf JCPV |
217 | # define CONFIG_SYS_CMXFCR_MASK (CMXFCR_FC2|CMXFCR_RF2CS_MSK|CMXFCR_TF2CS_MSK) |
218 | # define CONFIG_SYS_CMXFCR_VALUE (CMXFCR_RF2CS_CLK13|CMXFCR_TF2CS_CLK14) | |
219 | # define CONFIG_SYS_CPMFCR_RAMTYPE 0 | |
220 | # define CONFIG_SYS_FCC_PSMR (FCC_PSMR_FDE | FCC_PSMR_LPB) | |
fe8c2806 WD |
221 | |
222 | #endif /* CONFIG_ETHER_ON_FCC, CONFIG_ETHER_INDEX */ | |
223 | ||
224 | #define CONFIG_SHOW_BOOT_PROGRESS 1 /* boot progress enabled */ | |
225 | ||
226 | /* | |
227 | * Configure for RAM tests. | |
228 | */ | |
6d0f6bcf | 229 | #undef CONFIG_SYS_DRAM_TEST /* calls other tests in board.c */ |
fe8c2806 WD |
230 | |
231 | ||
232 | /* | |
233 | * Status LED for power up status feedback. | |
234 | */ | |
235 | #define CONFIG_STATUS_LED 1 /* Status LED enabled */ | |
236 | ||
237 | #define STATUS_LED_PAR im_ioport.iop_ppara | |
238 | #define STATUS_LED_DIR im_ioport.iop_pdira | |
239 | #define STATUS_LED_ODR im_ioport.iop_podra | |
240 | #define STATUS_LED_DAT im_ioport.iop_pdata | |
241 | ||
242 | #define STATUS_LED_BIT 0x00000800 /* LED 0 is on PA.20 */ | |
6d0f6bcf | 243 | #define STATUS_LED_PERIOD (CONFIG_SYS_HZ) |
fe8c2806 WD |
244 | #define STATUS_LED_STATE STATUS_LED_OFF |
245 | #define STATUS_LED_BIT1 0x00001000 /* LED 1 is on PA.19 */ | |
6d0f6bcf | 246 | #define STATUS_LED_PERIOD1 (CONFIG_SYS_HZ) |
fe8c2806 WD |
247 | #define STATUS_LED_STATE1 STATUS_LED_OFF |
248 | #define STATUS_LED_BIT2 0x00002000 /* LED 2 is on PA.18 */ | |
6d0f6bcf | 249 | #define STATUS_LED_PERIOD2 (CONFIG_SYS_HZ/2) |
fe8c2806 WD |
250 | #define STATUS_LED_STATE2 STATUS_LED_ON |
251 | ||
252 | #define STATUS_LED_ACTIVE 0 /* LED on for bit == 0 */ | |
253 | ||
254 | #define STATUS_LED_YELLOW 0 | |
255 | #define STATUS_LED_GREEN 1 | |
256 | #define STATUS_LED_RED 2 | |
257 | #define STATUS_LED_BOOT 1 | |
258 | ||
259 | ||
260 | /* | |
1d0350ed | 261 | * Select SPI support configuration |
fe8c2806 | 262 | */ |
1d0350ed WD |
263 | #define CONFIG_SOFT_SPI /* Enable SPI driver */ |
264 | #define MAX_SPI_BYTES 4 /* Maximum number of bytes we can handle */ | |
8bde7f77 WD |
265 | #undef DEBUG_SPI /* Disable SPI debugging */ |
266 | ||
fe8c2806 WD |
267 | /* |
268 | * Software (bit-bang) SPI driver configuration | |
269 | */ | |
270 | #ifdef CONFIG_SOFT_SPI | |
271 | ||
272 | /* | |
273 | * Software (bit-bang) SPI driver configuration | |
274 | */ | |
275 | #define I2C_SCLK 0x00002000 /* PD 18: Shift clock */ | |
276 | #define I2C_MOSI 0x00004000 /* PD 17: Master Out, Slave In */ | |
277 | #define I2C_MISO 0x00008000 /* PD 16: Master In, Slave Out */ | |
278 | ||
279 | #undef SPI_INIT /* no port initialization needed */ | |
280 | #define SPI_READ ((immr->im_ioport.iop_pdatd & I2C_MISO) != 0) | |
ced209c5 WD |
281 | #define SPI_SDA(bit) do { \ |
282 | if(bit) immr->im_ioport.iop_pdatd |= I2C_MOSI; \ | |
283 | else immr->im_ioport.iop_pdatd &= ~I2C_MOSI; \ | |
284 | } while (0) | |
285 | #define SPI_SCL(bit) do { \ | |
286 | if(bit) immr->im_ioport.iop_pdatd |= I2C_SCLK; \ | |
287 | else immr->im_ioport.iop_pdatd &= ~I2C_SCLK; \ | |
288 | } while (0) | |
1d0350ed | 289 | #define SPI_DELAY /* No delay is needed */ |
fe8c2806 WD |
290 | #endif /* CONFIG_SOFT_SPI */ |
291 | ||
292 | ||
293 | /* | |
294 | * select I2C support configuration | |
295 | * | |
296 | * Supported configurations are {none, software, hardware} drivers. | |
297 | * If the software driver is chosen, there are some additional | |
298 | * configuration items that the driver uses to drive the port pins. | |
299 | */ | |
300 | #undef CONFIG_HARD_I2C /* I2C with hardware support */ | |
301 | #define CONFIG_SOFT_I2C 1 /* I2C bit-banged */ | |
6d0f6bcf JCPV |
302 | #define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */ |
303 | #define CONFIG_SYS_I2C_SLAVE 0x7F | |
fe8c2806 WD |
304 | |
305 | /* | |
306 | * Software (bit-bang) I2C driver configuration | |
307 | */ | |
308 | #ifdef CONFIG_SOFT_I2C | |
309 | #define I2C_PORT 3 /* Port A=0, B=1, C=2, D=3 */ | |
310 | #define I2C_ACTIVE (iop->pdir |= 0x00010000) | |
311 | #define I2C_TRISTATE (iop->pdir &= ~0x00010000) | |
312 | #define I2C_READ ((iop->pdat & 0x00010000) != 0) | |
313 | #define I2C_SDA(bit) if(bit) iop->pdat |= 0x00010000; \ | |
314 | else iop->pdat &= ~0x00010000 | |
315 | #define I2C_SCL(bit) if(bit) iop->pdat |= 0x00020000; \ | |
316 | else iop->pdat &= ~0x00020000 | |
317 | #define I2C_DELAY udelay(20) /* 1/4 I2C clock duration */ | |
318 | #endif /* CONFIG_SOFT_I2C */ | |
319 | ||
320 | /* Define this to reserve an entire FLASH sector for | |
321 | * environment variables. Otherwise, the environment will be | |
322 | * put in the same sector as U-Boot, and changing variables | |
323 | * will erase U-Boot temporarily | |
324 | */ | |
0e8d1586 | 325 | #define CONFIG_ENV_IN_OWN_SECT 1 |
fe8c2806 WD |
326 | |
327 | /* Define this to contain any number of null terminated strings that | |
328 | * will be part of the default enviroment compiled into the boot image. | |
329 | */ | |
330 | #define CONFIG_EXTRA_ENV_SETTINGS \ | |
78137c3c WD |
331 | "quiet=0\0" \ |
332 | "serverip=192.168.123.205\0" \ | |
fe8c2806 WD |
333 | "ipaddr=192.168.123.203\0" \ |
334 | "checkhostname=VR8500\0" \ | |
335 | "reprog="\ | |
78137c3c | 336 | "bootp; " \ |
fe8c2806 WD |
337 | "tftpboot 0x140000 /bdi2000/u-boot.bin; " \ |
338 | "protect off 60000000 6003FFFF; " \ | |
339 | "erase 60000000 6003FFFF; " \ | |
fe126d8b | 340 | "cp.b 140000 60000000 ${filesize}; " \ |
fe8c2806 WD |
341 | "protect on 60000000 6003FFFF\0" \ |
342 | "copyenv="\ | |
343 | "protect off 60040000 6004FFFF; " \ | |
344 | "erase 60040000 6004FFFF; " \ | |
345 | "cp.b 40040000 60040000 10000; " \ | |
346 | "protect on 60040000 6004FFFF\0" \ | |
347 | "copyprog="\ | |
348 | "protect off 60000000 6003FFFF; " \ | |
349 | "erase 60000000 6003FFFF; " \ | |
350 | "cp.b 40000000 60000000 40000; " \ | |
351 | "protect on 60000000 6003FFFF\0" \ | |
352 | "zapenv="\ | |
353 | "protect off 40040000 4004FFFF; " \ | |
354 | "erase 40040000 4004FFFF; " \ | |
355 | "protect on 40040000 4004FFFF\0" \ | |
356 | "zapotherenv="\ | |
357 | "protect off 60040000 6004FFFF; " \ | |
358 | "erase 60040000 6004FFFF; " \ | |
359 | "protect on 60040000 6004FFFF\0" \ | |
360 | "root-on-initrd="\ | |
361 | "setenv bootcmd "\ | |
362 | "version\\;" \ | |
363 | "echo\\;" \ | |
364 | "bootp\\;" \ | |
365 | "setenv bootargs root=/dev/ram0 rw quiet " \ | |
fe126d8b | 366 | "ip=\\${ipaddr}:\\${serverip}:\\${gatewayip}:\\${netmask}:\\${hostname}::off\\;" \ |
fe8c2806 WD |
367 | "run boot-hook\\;" \ |
368 | "bootm\0" \ | |
369 | "root-on-initrd-debug="\ | |
370 | "setenv bootcmd "\ | |
371 | "version\\;" \ | |
372 | "echo\\;" \ | |
373 | "bootp\\;" \ | |
374 | "setenv bootargs root=/dev/ram0 rw debug " \ | |
fe126d8b | 375 | "ip=\\${ipaddr}:\\${serverip}:\\${gatewayip}:\\${netmask}:\\${hostname}::off\\;" \ |
fe8c2806 WD |
376 | "run debug-hook\\;" \ |
377 | "run boot-hook\\;" \ | |
378 | "bootm\0" \ | |
379 | "root-on-nfs="\ | |
380 | "setenv bootcmd "\ | |
381 | "version\\;" \ | |
382 | "echo\\;" \ | |
383 | "bootp\\;" \ | |
384 | "setenv bootargs root=/dev/nfs rw quiet " \ | |
fe126d8b WD |
385 | "nfsroot=\\${serverip}:\\${rootpath} " \ |
386 | "ip=\\${ipaddr}:\\${serverip}:\\${gatewayip}:\\${netmask}:\\${hostname}::off\\;" \ | |
fe8c2806 WD |
387 | "run boot-hook\\;" \ |
388 | "bootm\0" \ | |
389 | "root-on-nfs-debug="\ | |
390 | "setenv bootcmd "\ | |
391 | "version\\;" \ | |
392 | "echo\\;" \ | |
393 | "bootp\\;" \ | |
394 | "setenv bootargs root=/dev/nfs rw debug " \ | |
fe126d8b WD |
395 | "nfsroot=\\${serverip}:\\${rootpath} " \ |
396 | "ip=\\${ipaddr}:\\${serverip}:\\${gatewayip}:\\${netmask}:\\${hostname}::off\\;" \ | |
fe8c2806 WD |
397 | "run debug-hook\\;" \ |
398 | "run boot-hook\\;" \ | |
399 | "bootm\0" \ | |
400 | "debug-checkout="\ | |
401 | "setenv checkhostname;" \ | |
402 | "setenv ethaddr 00:09:70:00:00:01;" \ | |
403 | "bootp;" \ | |
fe126d8b WD |
404 | "setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} debug " \ |
405 | "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off;" \ | |
fe8c2806 WD |
406 | "run debug-hook;" \ |
407 | "run boot-hook;" \ | |
408 | "bootm\0" \ | |
409 | "debug-hook="\ | |
fe126d8b WD |
410 | "echo ipaddr ${ipaddr};" \ |
411 | "echo serverip ${serverip};" \ | |
412 | "echo gatewayip ${gatewayip};" \ | |
413 | "echo netmask ${netmask};" \ | |
414 | "echo hostname ${hostname}\0" \ | |
fe8c2806 WD |
415 | "ana=run adc ; run dac\0" \ |
416 | "adc=run adc-12 ; run adc-34\0" \ | |
0f89c54b PT |
417 | "adc-12=echo ### ADC-12 ; i2c md e 81 e\0" \ |
418 | "adc-34=echo ### ADC-34 ; i2c md f 81 e\0" \ | |
419 | "dac=echo ### DAC ; i2c md 11 81 5\0" \ | |
78137c3c | 420 | "boot-hook=echo\0" |
fe8c2806 WD |
421 | |
422 | /* What should the console's baud rate be? */ | |
423 | #define CONFIG_BAUDRATE 9600 | |
424 | ||
425 | /* Ethernet MAC address */ | |
426 | #define CONFIG_ETHADDR 00:09:70:00:00:00 | |
427 | ||
428 | /* The default Ethernet MAC address can be overwritten just once */ | |
429 | #ifdef CONFIG_ETHADDR | |
430 | #define CONFIG_OVERWRITE_ETHADDR_ONCE 1 | |
431 | #endif | |
432 | ||
433 | /* | |
434 | * Define this to do some miscellaneous board-specific initialization. | |
435 | */ | |
436 | #define CONFIG_MISC_INIT_R | |
437 | ||
438 | /* Set to a positive value to delay for running BOOTCOMMAND */ | |
439 | #define CONFIG_BOOTDELAY 1 /* autoboot after 1 second */ | |
440 | ||
441 | /* Be selective on what keys can delay or stop the autoboot process | |
442 | * To stop use: " " | |
443 | */ | |
444 | #define CONFIG_AUTOBOOT_KEYED | |
f2302d44 | 445 | #define CONFIG_AUTOBOOT_PROMPT "Autobooting...\n" |
fe8c2806 WD |
446 | #define CONFIG_AUTOBOOT_STOP_STR " " |
447 | #undef CONFIG_AUTOBOOT_DELAY_STR | |
448 | #define CONFIG_ZERO_BOOTDELAY_CHECK | |
449 | #define DEBUG_BOOTKEYS 0 | |
450 | ||
451 | /* Define a command string that is automatically executed when no character | |
452 | * is read on the console interface withing "Boot Delay" after reset. | |
453 | */ | |
53677ef1 | 454 | #undef CONFIG_BOOT_ROOT_INITRD /* Use ram disk for the root file system */ |
b79a11cc | 455 | #define CONFIG_BOOT_ROOT_NFS /* Use a NFS mounted root file system */ |
fe8c2806 | 456 | |
42dfe7a1 | 457 | #ifdef CONFIG_BOOT_ROOT_INITRD |
fe8c2806 WD |
458 | #define CONFIG_BOOTCOMMAND \ |
459 | "version;" \ | |
460 | "echo;" \ | |
461 | "bootp;" \ | |
462 | "setenv bootargs root=/dev/ram0 rw quiet " \ | |
fe126d8b | 463 | "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off;" \ |
fe8c2806 WD |
464 | "run boot-hook;" \ |
465 | "bootm" | |
466 | #endif /* CONFIG_BOOT_ROOT_INITRD */ | |
467 | ||
42dfe7a1 | 468 | #ifdef CONFIG_BOOT_ROOT_NFS |
fe8c2806 WD |
469 | #define CONFIG_BOOTCOMMAND \ |
470 | "version;" \ | |
471 | "echo;" \ | |
472 | "bootp;" \ | |
fe126d8b WD |
473 | "setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} quiet " \ |
474 | "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off;" \ | |
fe8c2806 WD |
475 | "run boot-hook;" \ |
476 | "bootm" | |
477 | #endif /* CONFIG_BOOT_ROOT_NFS */ | |
478 | ||
479 | #define CONFIG_BOOTP_RANDOM_DELAY /* Randomize the BOOTP retry delay */ | |
480 | ||
d3b8c1a7 JL |
481 | /* |
482 | * BOOTP options | |
fe8c2806 | 483 | */ |
d3b8c1a7 JL |
484 | #define CONFIG_BOOTP_SUBNETMASK |
485 | #define CONFIG_BOOTP_GATEWAY | |
486 | #define CONFIG_BOOTP_HOSTNAME | |
487 | #define CONFIG_BOOTP_BOOTPATH | |
488 | #define CONFIG_BOOTP_BOOTFILESIZE | |
489 | #define CONFIG_BOOTP_DNS | |
490 | #define CONFIG_BOOTP_DNS2 | |
491 | #define CONFIG_BOOTP_SEND_HOSTNAME | |
492 | ||
fe8c2806 WD |
493 | |
494 | /* undef this to save memory */ | |
6d0f6bcf | 495 | #define CONFIG_SYS_LONGHELP |
fe8c2806 WD |
496 | |
497 | /* Monitor Command Prompt */ | |
6d0f6bcf | 498 | #define CONFIG_SYS_PROMPT "=> " |
fe8c2806 | 499 | |
6d0f6bcf JCPV |
500 | #undef CONFIG_SYS_HUSH_PARSER |
501 | #ifdef CONFIG_SYS_HUSH_PARSER | |
502 | #define CONFIG_SYS_PROMPT_HUSH_PS2 "> " | |
fe8c2806 WD |
503 | #endif |
504 | ||
1d0350ed WD |
505 | /* When CONFIG_TIMESTAMP is selected, the timestamp (date and time) |
506 | * of an image is printed by image commands like bootm or iminfo. | |
507 | */ | |
508 | #define CONFIG_TIMESTAMP | |
509 | ||
42d1f039 | 510 | /* If this variable is defined, an environment variable named "ver" |
78137c3c WD |
511 | * is created by U-Boot showing the U-Boot version. |
512 | */ | |
513 | #define CONFIG_VERSION_VARIABLE | |
514 | ||
46da1e96 JL |
515 | |
516 | /* | |
517 | * Command line configuration. | |
518 | */ | |
519 | #include <config_cmd_default.h> | |
520 | ||
521 | #define CONFIG_CMD_ELF | |
522 | #define CONFIG_CMD_ASKENV | |
523 | #define CONFIG_CMD_I2C | |
524 | #define CONFIG_CMD_SPI | |
525 | #define CONFIG_CMD_SDRAM | |
526 | #define CONFIG_CMD_REGINFO | |
527 | #define CONFIG_CMD_IMMAP | |
528 | #define CONFIG_CMD_IRQ | |
529 | #define CONFIG_CMD_PING | |
530 | ||
531 | #undef CONFIG_CMD_KGDB | |
532 | ||
fe8c2806 | 533 | #ifdef CONFIG_ETHER_ON_FCC |
46da1e96 JL |
534 | #define CONFIG_CMD_MII |
535 | #endif | |
536 | ||
fe8c2806 WD |
537 | |
538 | /* Where do the internal registers live? */ | |
6d0f6bcf | 539 | #define CONFIG_SYS_IMMR 0xF0000000 |
fe8c2806 | 540 | |
78137c3c WD |
541 | #undef CONFIG_WATCHDOG /* disable the watchdog */ |
542 | ||
fe8c2806 WD |
543 | /***************************************************************************** |
544 | * | |
545 | * You should not have to modify any of the following settings | |
546 | * | |
547 | *****************************************************************************/ | |
548 | ||
549 | #define CONFIG_MPC8260 1 /* This is an MPC8260 CPU */ | |
550 | #define CONFIG_SBC8260 1 /* on an EST SBC8260 Board */ | |
551 | #define CONFIG_SACSng 1 /* munged for the SACSng */ | |
9c4c5ae3 | 552 | #define CONFIG_CPM2 1 /* Has a CPM2 */ |
fe8c2806 | 553 | |
fe8c2806 WD |
554 | /* |
555 | * Miscellaneous configurable options | |
556 | */ | |
6d0f6bcf | 557 | #define CONFIG_SYS_BOOTM_HEADER_QUIET 1 /* Suppress the image header dump */ |
42d1f039 | 558 | /* in the bootm command. */ |
6d0f6bcf | 559 | #define CONFIG_SYS_BOOTM_PROGESS_QUIET 1 /* Suppress the progress displays, */ |
42d1f039 | 560 | /* "## <message>" from the bootm cmd */ |
6d0f6bcf | 561 | #define CONFIG_SYS_BOOTP_CHECK_HOSTNAME 1 /* If checkhostname environment is */ |
42d1f039 WD |
562 | /* defined, then the hostname param */ |
563 | /* validated against checkhostname. */ | |
6d0f6bcf JCPV |
564 | #define CONFIG_SYS_BOOTP_RETRY_COUNT 0x40000000 /* # of timeouts before giving up */ |
565 | #define CONFIG_SYS_BOOTP_SHORT_RANDOM_DELAY 1 /* Use a short random delay value */ | |
42d1f039 | 566 | /* (limited to maximum of 1024 msec) */ |
6d0f6bcf | 567 | #define CONFIG_SYS_CHK_FOR_ABORT_AT_LEAST_ONCE 1 |
42d1f039 WD |
568 | /* Check for abort key presses */ |
569 | /* at least once in dependent of the */ | |
570 | /* CONFIG_BOOTDELAY value. */ | |
6d0f6bcf JCPV |
571 | #define CONFIG_SYS_CONSOLE_INFO_QUIET 1 /* Don't print console @ startup */ |
572 | #define CONFIG_SYS_FAULT_ECHO_LINK_DOWN 1 /* Echo the inverted Ethernet link */ | |
42d1f039 | 573 | /* state to the fault LED. */ |
6d0f6bcf | 574 | #define CONFIG_SYS_FAULT_MII_ADDR 0x02 /* MII addr of the PHY to check for */ |
42d1f039 | 575 | /* the Ethernet link state. */ |
6d0f6bcf | 576 | #define CONFIG_SYS_STATUS_FLASH_UNTIL_TFTP_OK 1 /* Keeping the status LED flashing */ |
42d1f039 | 577 | /* until the TFTP is successful. */ |
6d0f6bcf | 578 | #define CONFIG_SYS_STATUS_OFF_AFTER_NETBOOT 1 /* After a successful netboot, */ |
42d1f039 | 579 | /* turn off the STATUS LEDs. */ |
6d0f6bcf | 580 | #define CONFIG_SYS_TFTP_BLINK_STATUS_ON_DATA_IN 1 /* Blink status LED based on */ |
42d1f039 | 581 | /* incoming data. */ |
6d0f6bcf | 582 | #define CONFIG_SYS_TFTP_BLOCKS_PER_HASH 100 /* For every XX blocks, output a '#' */ |
42d1f039 | 583 | /* to signify that tftp is moving. */ |
6d0f6bcf | 584 | #define CONFIG_SYS_TFTP_HASHES_PER_FLASH 200 /* For every '#' hashes, */ |
42d1f039 | 585 | /* flash the status LED. */ |
6d0f6bcf | 586 | #define CONFIG_SYS_TFTP_HASHES_PER_LINE 65 /* Only output XX '#'s per line */ |
42d1f039 | 587 | /* during the tftp file transfer. */ |
6d0f6bcf | 588 | #define CONFIG_SYS_TFTP_PROGESS_QUIET 1 /* Suppress the progress displays */ |
42d1f039 | 589 | /* '#'s from the tftp command. */ |
6d0f6bcf | 590 | #define CONFIG_SYS_TFTP_STATUS_QUIET 1 /* Suppress the status displays */ |
42d1f039 | 591 | /* issued during the tftp command. */ |
6d0f6bcf | 592 | #define CONFIG_SYS_TFTP_TIMEOUT_COUNT 5 /* How many timeouts TFTP will allow */ |
78137c3c WD |
593 | /* before it gives up. */ |
594 | ||
46da1e96 | 595 | #if defined(CONFIG_CMD_KGDB) |
6d0f6bcf | 596 | # define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ |
fe8c2806 | 597 | #else |
6d0f6bcf | 598 | # define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ |
fe8c2806 WD |
599 | #endif |
600 | ||
601 | /* Print Buffer Size */ | |
6d0f6bcf | 602 | #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT)+16) |
fe8c2806 | 603 | |
6d0f6bcf | 604 | #define CONFIG_SYS_MAXARGS 32 /* max number of command args */ |
fe8c2806 | 605 | |
6d0f6bcf | 606 | #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ |
fe8c2806 | 607 | |
6d0f6bcf JCPV |
608 | #define CONFIG_SYS_LOAD_ADDR 0x400000 /* default load address */ |
609 | #define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */ | |
fe8c2806 | 610 | |
6d0f6bcf JCPV |
611 | #define CONFIG_SYS_ALT_MEMTEST /* Select full-featured memory test */ |
612 | #define CONFIG_SYS_MEMTEST_START 0x2000 /* memtest works from the end of */ | |
fe8c2806 WD |
613 | /* the exception vector table */ |
614 | /* to the end of the DRAM */ | |
615 | /* less monitor and malloc area */ | |
6d0f6bcf JCPV |
616 | #define CONFIG_SYS_STACK_USAGE 0x10000 /* Reserve 64k for the stack usage */ |
617 | #define CONFIG_SYS_MEM_END_USAGE ( CONFIG_SYS_MONITOR_LEN \ | |
618 | + CONFIG_SYS_MALLOC_LEN \ | |
0e8d1586 | 619 | + CONFIG_ENV_SECT_SIZE \ |
6d0f6bcf | 620 | + CONFIG_SYS_STACK_USAGE ) |
fe8c2806 | 621 | |
6d0f6bcf JCPV |
622 | #define CONFIG_SYS_MEMTEST_END ( CONFIG_SYS_SDRAM_SIZE * 1024 * 1024 \ |
623 | - CONFIG_SYS_MEM_END_USAGE ) | |
fe8c2806 WD |
624 | |
625 | /* valid baudrates */ | |
6d0f6bcf | 626 | #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } |
fe8c2806 WD |
627 | |
628 | /* | |
629 | * Low Level Configuration Settings | |
630 | * (address mappings, register initial values, etc.) | |
631 | * You should know what you are doing if you make changes here. | |
632 | */ | |
633 | ||
6d0f6bcf JCPV |
634 | #define CONFIG_SYS_FLASH_BASE CONFIG_SYS_FLASH0_BASE |
635 | #define CONFIG_SYS_FLASH_SIZE CONFIG_SYS_FLASH0_SIZE | |
636 | #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_SDRAM0_BASE | |
637 | #define CONFIG_SYS_SDRAM_SIZE CONFIG_SYS_SDRAM0_SIZE | |
fe8c2806 WD |
638 | |
639 | /*----------------------------------------------------------------------- | |
640 | * Hard Reset Configuration Words | |
641 | */ | |
6d0f6bcf JCPV |
642 | #if defined(CONFIG_SYS_SBC_BOOT_LOW) |
643 | # define CONFIG_SYS_SBC_HRCW_BOOT_FLAGS (HRCW_CIP | HRCW_BMS) | |
fe8c2806 | 644 | #else |
6d0f6bcf JCPV |
645 | # define CONFIG_SYS_SBC_HRCW_BOOT_FLAGS (0) |
646 | #endif /* defined(CONFIG_SYS_SBC_BOOT_LOW) */ | |
fe8c2806 | 647 | |
6d0f6bcf JCPV |
648 | /* get the HRCW ISB field from CONFIG_SYS_IMMR */ |
649 | #define CONFIG_SYS_SBC_HRCW_IMMR ( ((CONFIG_SYS_IMMR & 0x10000000) >> 10) | \ | |
650 | ((CONFIG_SYS_IMMR & 0x01000000) >> 7) | \ | |
651 | ((CONFIG_SYS_IMMR & 0x00100000) >> 4) ) | |
fe8c2806 | 652 | |
6d0f6bcf | 653 | #define CONFIG_SYS_HRCW_MASTER ( HRCW_BPS10 | \ |
fe8c2806 | 654 | HRCW_DPPC11 | \ |
6d0f6bcf | 655 | CONFIG_SYS_SBC_HRCW_IMMR | \ |
fe8c2806 WD |
656 | HRCW_MMR00 | \ |
657 | HRCW_LBPC11 | \ | |
658 | HRCW_APPC10 | \ | |
659 | HRCW_CS10PC00 | \ | |
6d0f6bcf JCPV |
660 | (CONFIG_SYS_SBC_MODCK_H & HRCW_MODCK_H1111) | \ |
661 | CONFIG_SYS_SBC_HRCW_BOOT_FLAGS ) | |
fe8c2806 WD |
662 | |
663 | /* no slaves */ | |
6d0f6bcf JCPV |
664 | #define CONFIG_SYS_HRCW_SLAVE1 0 |
665 | #define CONFIG_SYS_HRCW_SLAVE2 0 | |
666 | #define CONFIG_SYS_HRCW_SLAVE3 0 | |
667 | #define CONFIG_SYS_HRCW_SLAVE4 0 | |
668 | #define CONFIG_SYS_HRCW_SLAVE5 0 | |
669 | #define CONFIG_SYS_HRCW_SLAVE6 0 | |
670 | #define CONFIG_SYS_HRCW_SLAVE7 0 | |
fe8c2806 WD |
671 | |
672 | /*----------------------------------------------------------------------- | |
673 | * Definitions for initial stack pointer and data area (in DPRAM) | |
674 | */ | |
6d0f6bcf | 675 | #define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR |
553f0982 | 676 | #define CONFIG_SYS_INIT_RAM_SIZE 0x4000 /* Size of used area in DPRAM */ |
25ddd1fb | 677 | #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) |
6d0f6bcf | 678 | #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET |
fe8c2806 WD |
679 | |
680 | /*----------------------------------------------------------------------- | |
681 | * Start addresses for the final memory configuration | |
682 | * (Set up by the startup code) | |
6d0f6bcf JCPV |
683 | * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 |
684 | * Note also that the logic that sets CONFIG_SYS_RAMBOOT is platform dependent. | |
fe8c2806 | 685 | */ |
6d0f6bcf | 686 | #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH0_BASE |
fe8c2806 | 687 | |
6d0f6bcf JCPV |
688 | #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE) |
689 | # define CONFIG_SYS_RAMBOOT | |
fe8c2806 WD |
690 | #endif |
691 | ||
6d0f6bcf JCPV |
692 | #define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ |
693 | #define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ | |
fe8c2806 WD |
694 | |
695 | /* | |
696 | * For booting Linux, the board info and command line data | |
697 | * have to be in the first 8 MB of memory, since this is | |
698 | * the maximum mapped by the Linux kernel during initialization. | |
699 | */ | |
6d0f6bcf | 700 | #define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ |
fe8c2806 WD |
701 | |
702 | /*----------------------------------------------------------------------- | |
703 | * FLASH and environment organization | |
704 | */ | |
705 | ||
6d0f6bcf JCPV |
706 | #define CONFIG_SYS_FLASH_CFI 1 /* Flash is CFI conformant */ |
707 | #undef CONFIG_SYS_FLASH_PROTECTION /* use hardware protection */ | |
708 | #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of memory banks */ | |
709 | #define CONFIG_SYS_MAX_FLASH_SECT (64+4) /* max number of sectors on one chip */ | |
fe8c2806 | 710 | |
6d0f6bcf JCPV |
711 | #define CONFIG_SYS_FLASH_ERASE_TOUT 8000 /* Timeout for Flash Erase (in ms) */ |
712 | #define CONFIG_SYS_FLASH_WRITE_TOUT 1 /* Timeout for Flash Write (in ms) */ | |
fe8c2806 | 713 | |
6d0f6bcf | 714 | #ifndef CONFIG_SYS_RAMBOOT |
5a1aceb0 | 715 | # define CONFIG_ENV_IS_IN_FLASH 1 |
fe8c2806 | 716 | |
0e8d1586 | 717 | # ifdef CONFIG_ENV_IN_OWN_SECT |
6d0f6bcf | 718 | # define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN) |
0e8d1586 | 719 | # define CONFIG_ENV_SECT_SIZE 0x10000 |
fe8c2806 | 720 | # else |
6d0f6bcf | 721 | # define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_SYS_MONITOR_LEN - CONFIG_ENV_SECT_SIZE) |
0e8d1586 JCPV |
722 | # define CONFIG_ENV_SIZE 0x1000 /* Total Size of Environment Sector */ |
723 | # define CONFIG_ENV_SECT_SIZE 0x10000 /* see README - env sect real size */ | |
724 | # endif /* CONFIG_ENV_IN_OWN_SECT */ | |
fe8c2806 WD |
725 | |
726 | #else | |
9314cee6 | 727 | # define CONFIG_ENV_IS_IN_NVRAM 1 |
6d0f6bcf | 728 | # define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000) |
0e8d1586 | 729 | # define CONFIG_ENV_SIZE 0x200 |
6d0f6bcf | 730 | #endif /* CONFIG_SYS_RAMBOOT */ |
fe8c2806 WD |
731 | |
732 | /*----------------------------------------------------------------------- | |
733 | * Cache Configuration | |
734 | */ | |
6d0f6bcf | 735 | #define CONFIG_SYS_CACHELINE_SIZE 32 /* For MPC8260 CPU */ |
fe8c2806 | 736 | |
46da1e96 | 737 | #if defined(CONFIG_CMD_KGDB) |
6d0f6bcf | 738 | # define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */ |
fe8c2806 WD |
739 | #endif |
740 | ||
741 | /*----------------------------------------------------------------------- | |
742 | * HIDx - Hardware Implementation-dependent Registers 2-11 | |
743 | *----------------------------------------------------------------------- | |
744 | * HID0 also contains cache control - initially enable both caches and | |
745 | * invalidate contents, then the final state leaves only the instruction | |
746 | * cache enabled. Note that Power-On and Hard reset invalidate the caches, | |
747 | * but Soft reset does not. | |
748 | * | |
749 | * HID1 has only read-only information - nothing to set. | |
750 | */ | |
6d0f6bcf | 751 | #define CONFIG_SYS_HID0_INIT (HID0_ICE |\ |
fe8c2806 WD |
752 | HID0_DCE |\ |
753 | HID0_ICFI |\ | |
754 | HID0_DCI |\ | |
755 | HID0_IFEM |\ | |
756 | HID0_ABE) | |
757 | ||
6d0f6bcf | 758 | #define CONFIG_SYS_HID0_FINAL (HID0_ICE |\ |
fe8c2806 WD |
759 | HID0_IFEM |\ |
760 | HID0_ABE |\ | |
761 | HID0_EMCP) | |
6d0f6bcf | 762 | #define CONFIG_SYS_HID2 0 |
fe8c2806 WD |
763 | |
764 | /*----------------------------------------------------------------------- | |
765 | * RMR - Reset Mode Register | |
766 | *----------------------------------------------------------------------- | |
767 | */ | |
6d0f6bcf | 768 | #define CONFIG_SYS_RMR 0 |
fe8c2806 WD |
769 | |
770 | /*----------------------------------------------------------------------- | |
771 | * BCR - Bus Configuration 4-25 | |
772 | *----------------------------------------------------------------------- | |
773 | */ | |
6d0f6bcf | 774 | #define CONFIG_SYS_BCR (BCR_ETM) |
fe8c2806 WD |
775 | |
776 | /*----------------------------------------------------------------------- | |
777 | * SIUMCR - SIU Module Configuration 4-31 | |
778 | *----------------------------------------------------------------------- | |
779 | */ | |
780 | ||
6d0f6bcf | 781 | #define CONFIG_SYS_SIUMCR (SIUMCR_DPPC11 |\ |
fe8c2806 WD |
782 | SIUMCR_L2CPC00 |\ |
783 | SIUMCR_APPC10 |\ | |
784 | SIUMCR_MMR00) | |
785 | ||
786 | ||
787 | /*----------------------------------------------------------------------- | |
788 | * SYPCR - System Protection Control 11-9 | |
789 | * SYPCR can only be written once after reset! | |
790 | *----------------------------------------------------------------------- | |
791 | * Watchdog & Bus Monitor Timer max, 60x Bus Monitor enable | |
792 | */ | |
78137c3c | 793 | #if defined(CONFIG_WATCHDOG) |
6d0f6bcf | 794 | #define CONFIG_SYS_SYPCR (SYPCR_SWTC |\ |
78137c3c WD |
795 | SYPCR_BMT |\ |
796 | SYPCR_PBME |\ | |
797 | SYPCR_LBME |\ | |
798 | SYPCR_SWRI |\ | |
799 | SYPCR_SWP |\ | |
42d1f039 | 800 | SYPCR_SWE) |
78137c3c | 801 | #else |
6d0f6bcf | 802 | #define CONFIG_SYS_SYPCR (SYPCR_SWTC |\ |
fe8c2806 WD |
803 | SYPCR_BMT |\ |
804 | SYPCR_PBME |\ | |
805 | SYPCR_LBME |\ | |
806 | SYPCR_SWRI |\ | |
807 | SYPCR_SWP) | |
78137c3c | 808 | #endif /* CONFIG_WATCHDOG */ |
fe8c2806 WD |
809 | |
810 | /*----------------------------------------------------------------------- | |
811 | * TMCNTSC - Time Counter Status and Control 4-40 | |
812 | *----------------------------------------------------------------------- | |
813 | * Clear once per Second and Alarm Interrupt Status, Set 32KHz timersclk, | |
814 | * and enable Time Counter | |
815 | */ | |
6d0f6bcf | 816 | #define CONFIG_SYS_TMCNTSC (TMCNTSC_SEC |\ |
fe8c2806 WD |
817 | TMCNTSC_ALR |\ |
818 | TMCNTSC_TCF |\ | |
819 | TMCNTSC_TCE) | |
820 | ||
821 | /*----------------------------------------------------------------------- | |
822 | * PISCR - Periodic Interrupt Status and Control 4-42 | |
823 | *----------------------------------------------------------------------- | |
824 | * Clear Periodic Interrupt Status, Set 32KHz timersclk, and enable | |
825 | * Periodic timer | |
826 | */ | |
6d0f6bcf | 827 | #define CONFIG_SYS_PISCR (PISCR_PS |\ |
fe8c2806 WD |
828 | PISCR_PTF |\ |
829 | PISCR_PTE) | |
830 | ||
831 | /*----------------------------------------------------------------------- | |
832 | * SCCR - System Clock Control 9-8 | |
833 | *----------------------------------------------------------------------- | |
834 | */ | |
6d0f6bcf | 835 | #define CONFIG_SYS_SCCR 0 |
fe8c2806 WD |
836 | |
837 | /*----------------------------------------------------------------------- | |
838 | * RCCR - RISC Controller Configuration 13-7 | |
839 | *----------------------------------------------------------------------- | |
840 | */ | |
6d0f6bcf | 841 | #define CONFIG_SYS_RCCR 0 |
fe8c2806 WD |
842 | |
843 | /* | |
844 | * Initialize Memory Controller: | |
845 | * | |
846 | * Bank Bus Machine PortSz Device | |
847 | * ---- --- ------- ------ ------ | |
848 | * 0 60x GPCM 16 bit FLASH (primary flash - 2MB) | |
849 | * 1 60x GPCM -- bit (Unused) | |
850 | * 2 60x SDRAM 64 bit SDRAM (DIMM) | |
851 | * 3 60x SDRAM 64 bit SDRAM (DIMM) | |
852 | * 4 60x GPCM -- bit (Unused) | |
853 | * 5 60x GPCM -- bit (Unused) | |
854 | * 6 60x GPCM 16 bit FLASH (secondary flash - 2MB) | |
855 | */ | |
856 | ||
857 | /*----------------------------------------------------------------------- | |
858 | * BR0,BR1 - Base Register | |
859 | * Ref: Section 10.3.1 on page 10-14 | |
860 | * OR0,OR1 - Option Register | |
861 | * Ref: Section 10.3.2 on page 10-18 | |
862 | *----------------------------------------------------------------------- | |
863 | */ | |
864 | ||
865 | /* Bank 0 - Primary FLASH | |
866 | */ | |
867 | ||
868 | /* BR0 is configured as follows: | |
869 | * | |
870 | * - Base address of 0x40000000 | |
871 | * - 16 bit port size | |
872 | * - Data errors checking is disabled | |
873 | * - Read and write access | |
874 | * - GPCM 60x bus | |
875 | * - Access are handled by the memory controller according to MSEL | |
876 | * - Not used for atomic operations | |
877 | * - No data pipelining is done | |
878 | * - Valid | |
879 | */ | |
6d0f6bcf | 880 | #define CONFIG_SYS_BR0_PRELIM ((CONFIG_SYS_FLASH0_BASE & BRx_BA_MSK) |\ |
fe8c2806 WD |
881 | BRx_PS_16 |\ |
882 | BRx_MS_GPCM_P |\ | |
883 | BRx_V) | |
884 | ||
885 | /* OR0 is configured as follows: | |
886 | * | |
887 | * - 4 MB | |
888 | * - *BCTL0 is asserted upon access to the current memory bank | |
889 | * - *CW / *WE are negated a quarter of a clock earlier | |
890 | * - *CS is output at the same time as the address lines | |
891 | * - Uses a clock cycle length of 5 | |
892 | * - *PSDVAL is generated internally by the memory controller | |
893 | * unless *GTA is asserted earlier externally. | |
894 | * - Relaxed timing is generated by the GPCM for accesses | |
895 | * initiated to this memory region. | |
896 | * - One idle clock is inserted between a read access from the | |
897 | * current bank and the next access. | |
898 | */ | |
6d0f6bcf | 899 | #define CONFIG_SYS_OR0_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH0_SIZE) |\ |
fe8c2806 WD |
900 | ORxG_CSNT |\ |
901 | ORxG_ACS_DIV1 |\ | |
902 | ORxG_SCY_5_CLK |\ | |
903 | ORxG_TRLX |\ | |
904 | ORxG_EHTR) | |
905 | ||
906 | /*----------------------------------------------------------------------- | |
907 | * BR2,BR3 - Base Register | |
908 | * Ref: Section 10.3.1 on page 10-14 | |
909 | * OR2,OR3 - Option Register | |
910 | * Ref: Section 10.3.2 on page 10-16 | |
911 | *----------------------------------------------------------------------- | |
912 | */ | |
913 | ||
914 | /* Bank 2,3 - SDRAM DIMM | |
915 | */ | |
916 | ||
917 | /* The BR2 is configured as follows: | |
918 | * | |
919 | * - Base address of 0x00000000 | |
920 | * - 64 bit port size (60x bus only) | |
921 | * - Data errors checking is disabled | |
922 | * - Read and write access | |
923 | * - SDRAM 60x bus | |
924 | * - Access are handled by the memory controller according to MSEL | |
925 | * - Not used for atomic operations | |
926 | * - No data pipelining is done | |
927 | * - Valid | |
928 | */ | |
6d0f6bcf | 929 | #define CONFIG_SYS_BR2_PRELIM ((CONFIG_SYS_SDRAM0_BASE & BRx_BA_MSK) |\ |
fe8c2806 WD |
930 | BRx_PS_64 |\ |
931 | BRx_MS_SDRAM_P |\ | |
932 | BRx_V) | |
933 | ||
6d0f6bcf | 934 | #define CONFIG_SYS_BR3_PRELIM ((CONFIG_SYS_SDRAM0_BASE & BRx_BA_MSK) |\ |
fe8c2806 WD |
935 | BRx_PS_64 |\ |
936 | BRx_MS_SDRAM_P |\ | |
937 | BRx_V) | |
938 | ||
939 | /* With a 64 MB DIMM, the OR2 is configured as follows: | |
940 | * | |
941 | * - 64 MB | |
942 | * - 4 internal banks per device | |
943 | * - Row start address bit is A8 with PSDMR[PBI] = 0 | |
944 | * - 12 row address lines | |
945 | * - Back-to-back page mode | |
946 | * - Internal bank interleaving within save device enabled | |
947 | */ | |
6d0f6bcf JCPV |
948 | #if (CONFIG_SYS_SDRAM0_SIZE == 64) |
949 | #define CONFIG_SYS_OR2_PRELIM (MEG_TO_AM(CONFIG_SYS_SDRAM0_SIZE) |\ | |
fe8c2806 WD |
950 | ORxS_BPD_4 |\ |
951 | ORxS_ROWST_PBI0_A8 |\ | |
952 | ORxS_NUMR_12) | |
953 | #else | |
954 | #error "INVALID SDRAM CONFIGURATION" | |
955 | #endif | |
956 | ||
957 | /*----------------------------------------------------------------------- | |
958 | * PSDMR - 60x Bus SDRAM Mode Register | |
959 | * Ref: Section 10.3.3 on page 10-21 | |
960 | *----------------------------------------------------------------------- | |
961 | */ | |
962 | ||
963 | /* Address that the DIMM SPD memory lives at. | |
964 | */ | |
965 | #define SDRAM_SPD_ADDR 0x50 | |
966 | ||
6d0f6bcf | 967 | #if (CONFIG_SYS_SDRAM0_SIZE == 64) |
fe8c2806 WD |
968 | /* With a 64 MB DIMM, the PSDMR is configured as follows: |
969 | * | |
970 | * - Bank Based Interleaving, | |
971 | * - Refresh Enable, | |
972 | * - Address Multiplexing where A5 is output on A14 pin | |
973 | * (A6 on A15, and so on), | |
974 | * - use address pins A14-A16 as bank select, | |
975 | * - A9 is output on SDA10 during an ACTIVATE command, | |
976 | * - earliest timing for ACTIVATE command after REFRESH command is 7 clocks, | |
977 | * - earliest timing for ACTIVATE or REFRESH command after PRECHARGE command | |
978 | * is 3 clocks, | |
979 | * - earliest timing for READ/WRITE command after ACTIVATE command is | |
980 | * 2 clocks, | |
981 | * - earliest timing for PRECHARGE after last data was read is 1 clock, | |
982 | * - earliest timing for PRECHARGE after last data was written is 1 clock, | |
983 | * - CAS Latency is 2. | |
984 | */ | |
6d0f6bcf | 985 | #define CONFIG_SYS_PSDMR (PSDMR_RFEN |\ |
fe8c2806 WD |
986 | PSDMR_SDAM_A14_IS_A5 |\ |
987 | PSDMR_BSMA_A14_A16 |\ | |
988 | PSDMR_SDA10_PBI0_A9 |\ | |
989 | PSDMR_RFRC_7_CLK |\ | |
990 | PSDMR_PRETOACT_3W |\ | |
991 | PSDMR_ACTTORW_2W |\ | |
992 | PSDMR_LDOTOPRE_1C |\ | |
993 | PSDMR_WRC_1C |\ | |
994 | PSDMR_CL_2) | |
995 | #else | |
996 | #error "INVALID SDRAM CONFIGURATION" | |
997 | #endif | |
998 | ||
999 | /* | |
1000 | * Shoot for approximately 1MHz on the prescaler. | |
1001 | */ | |
1002 | #if (CONFIG_8260_CLKIN >= (60 * 1000 * 1000)) | |
6d0f6bcf | 1003 | #define CONFIG_SYS_MPTPR MPTPR_PTP_DIV64 |
fe8c2806 | 1004 | #elif (CONFIG_8260_CLKIN >= (30 * 1000 * 1000)) |
6d0f6bcf | 1005 | #define CONFIG_SYS_MPTPR MPTPR_PTP_DIV32 |
fe8c2806 | 1006 | #else |
6d0f6bcf JCPV |
1007 | #warning "Unconfigured bus clock freq: check CONFIG_SYS_MPTPR and CONFIG_SYS_PSRT are OK" |
1008 | #define CONFIG_SYS_MPTPR MPTPR_PTP_DIV32 | |
fe8c2806 | 1009 | #endif |
6d0f6bcf | 1010 | #define CONFIG_SYS_PSRT 14 |
fe8c2806 WD |
1011 | |
1012 | ||
1013 | /*----------------------------------------------------------------------- | |
1014 | * BR6 - Base Register | |
1015 | * Ref: Section 10.3.1 on page 10-14 | |
1016 | * OR6 - Option Register | |
1017 | * Ref: Section 10.3.2 on page 10-18 | |
1018 | *----------------------------------------------------------------------- | |
1019 | */ | |
1020 | ||
1021 | /* Bank 6 - Secondary FLASH | |
1022 | * | |
1023 | * The secondary FLASH is connected to *CS6 | |
1024 | */ | |
6d0f6bcf | 1025 | #if (defined(CONFIG_SYS_FLASH1_BASE) && defined(CONFIG_SYS_FLASH1_SIZE)) |
fe8c2806 WD |
1026 | |
1027 | /* BR6 is configured as follows: | |
1028 | * | |
1029 | * - Base address of 0x60000000 | |
1030 | * - 16 bit port size | |
1031 | * - Data errors checking is disabled | |
1032 | * - Read and write access | |
1033 | * - GPCM 60x bus | |
1034 | * - Access are handled by the memory controller according to MSEL | |
1035 | * - Not used for atomic operations | |
1036 | * - No data pipelining is done | |
1037 | * - Valid | |
1038 | */ | |
6d0f6bcf | 1039 | # define CONFIG_SYS_BR6_PRELIM ((CONFIG_SYS_FLASH1_BASE & BRx_BA_MSK) |\ |
fe8c2806 WD |
1040 | BRx_PS_16 |\ |
1041 | BRx_MS_GPCM_P |\ | |
1042 | BRx_V) | |
1043 | ||
1044 | /* OR6 is configured as follows: | |
1045 | * | |
1046 | * - 2 MB | |
1047 | * - *BCTL0 is asserted upon access to the current memory bank | |
1048 | * - *CW / *WE are negated a quarter of a clock earlier | |
1049 | * - *CS is output at the same time as the address lines | |
1050 | * - Uses a clock cycle length of 5 | |
1051 | * - *PSDVAL is generated internally by the memory controller | |
1052 | * unless *GTA is asserted earlier externally. | |
1053 | * - Relaxed timing is generated by the GPCM for accesses | |
1054 | * initiated to this memory region. | |
1055 | * - One idle clock is inserted between a read access from the | |
1056 | * current bank and the next access. | |
1057 | */ | |
6d0f6bcf | 1058 | # define CONFIG_SYS_OR6_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH1_SIZE) |\ |
fe8c2806 WD |
1059 | ORxG_CSNT |\ |
1060 | ORxG_ACS_DIV1 |\ | |
1061 | ORxG_SCY_5_CLK |\ | |
1062 | ORxG_TRLX |\ | |
1063 | ORxG_EHTR) | |
6d0f6bcf | 1064 | #endif /* (defined(CONFIG_SYS_FLASH1_BASE) && defined(CONFIG_SYS_FLASH1_SIZE)) */ |
fe8c2806 | 1065 | |
fe8c2806 | 1066 | #endif /* __CONFIG_H */ |