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1/*
2 * (C) Copyright 2000
3 * Murray Jensen <Murray.Jensen@cmst.csiro.au>
4 *
5 * (C) Copyright 2000
6 * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
7 * Marius Groeger <mgroeger@sysgo.de>
8 *
9 * (C) Copyright 2001
10 * Advent Networks, Inc. <http://www.adventnetworks.com>
11 * Jay Monkman <jtm@smoothsmoothie.com>
12 *
13 * Configuration settings for the WindRiver SBC8260 board.
14 * See http://www.windriver.com/products/html/sbc8260.html
15 *
16 * See file CREDITS for list of people who contributed to this
17 * project.
18 *
19 * This program is free software; you can redistribute it and/or
20 * modify it under the terms of the GNU General Public License as
21 * published by the Free Software Foundation; either version 2 of
22 * the License, or (at your option) any later version.
23 *
24 * This program is distributed in the hope that it will be useful,
25 * but WITHOUT ANY WARRANTY; without even the implied warranty of
26 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
27 * GNU General Public License for more details.
28 *
29 * You should have received a copy of the GNU General Public License
30 * along with this program; if not, write to the Free Software
31 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
32 * MA 02111-1307 USA
33 */
34
35#ifndef __CONFIG_H
36#define __CONFIG_H
37
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38#undef DEBUG_BOOTP_EXT /* Debug received vendor fields */
39
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40#undef CONFIG_LOGBUFFER /* External logbuffer support */
41
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42/*****************************************************************************
43 *
44 * These settings must match the way _your_ board is set up
45 *
46 *****************************************************************************/
47
48/* What is the oscillator's (UX2) frequency in Hz? */
49#define CONFIG_8260_CLKIN 66666600
50
51/*-----------------------------------------------------------------------
52 * MODCK_H & MODCLK[1-3] - Ref: Section 9.2 in MPC8206 User Manual
53 *-----------------------------------------------------------------------
54 * What should MODCK_H be? It is dependent on the oscillator
55 * frequency, MODCK[1-3], and desired CPM and core frequencies.
56 * Here are some example values (all frequencies are in MHz):
57 *
58 * MODCK_H MODCK[1-3] Osc CPM Core S2-6 S2-7 S2-8
59 * ------- ---------- --- --- ---- ----- ----- -----
60 * 0x1 0x5 33 100 133 Open Close Open
61 * 0x1 0x6 33 100 166 Open Open Close
62 * 0x1 0x7 33 100 200 Open Open Open
63 *
64 * 0x2 0x2 33 133 133 Close Open Close
65 * 0x2 0x3 33 133 166 Close Open Open
66 * 0x2 0x4 33 133 200 Open Close Close
67 * 0x2 0x5 33 133 233 Open Close Open
68 * 0x2 0x6 33 133 266 Open Open Close
69 *
70 * 0x5 0x5 66 133 133 Open Close Open
71 * 0x5 0x6 66 133 166 Open Open Close
72 * 0x5 0x7 66 133 200 Open Open Open
73 * 0x6 0x0 66 133 233 Close Close Close
74 * 0x6 0x1 66 133 266 Close Close Open
75 * 0x6 0x2 66 133 300 Close Open Close
76 */
6d0f6bcf 77#define CONFIG_SYS_SBC_MODCK_H 0x05
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78
79/* Define this if you want to boot from 0x00000100. If you don't define
80 * this, you will need to program the bootloader to 0xfff00000, and
81 * get the hardware reset config words at 0xfe000000. The simplest
82 * way to do that is to program the bootloader at both addresses.
83 * It is suggested that you just let U-Boot live at 0x00000000.
84 */
6d0f6bcf 85#define CONFIG_SYS_SBC_BOOT_LOW 1
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86
87/* What should the base address of the main FLASH be and how big is
88 * it (in MBytes)? This must contain TEXT_BASE from board/sacsng/config.mk
89 * The main FLASH is whichever is connected to *CS0.
90 */
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91#define CONFIG_SYS_FLASH0_BASE 0x40000000
92#define CONFIG_SYS_FLASH0_SIZE 2
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93
94/* What should the base address of the secondary FLASH be and how big
95 * is it (in Mbytes)? The secondary FLASH is whichever is connected
96 * to *CS6.
97 */
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98#define CONFIG_SYS_FLASH1_BASE 0x60000000
99#define CONFIG_SYS_FLASH1_SIZE 2
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100
101/* Define CONFIG_VERY_BIG_RAM to allow use of SDRAMs larger than 256MBytes
102 */
103#define CONFIG_VERY_BIG_RAM 1
104
105/* What should be the base address of SDRAM DIMM and how big is
106 * it (in Mbytes)? This will normally auto-configure via the SPD.
107*/
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108#define CONFIG_SYS_SDRAM0_BASE 0x00000000
109#define CONFIG_SYS_SDRAM0_SIZE 64
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110
111/*
112 * Memory map example with 64 MB DIMM:
113 *
114 * 0x0000 0000 Exception Vector code, 8k
115 * :
116 * 0x0000 1FFF
117 * 0x0000 2000 Free for Application Use
118 * :
119 * :
120 *
121 * :
122 * :
123 * 0x03F5 FF30 Monitor Stack (Growing downward)
124 * Monitor Stack Buffer (0x80)
125 * 0x03F5 FFB0 Board Info Data
126 * 0x03F6 0000 Malloc Arena
0e8d1586 127 * : CONFIG_ENV_SECT_SIZE, 16k
6d0f6bcf 128 * : CONFIG_SYS_MALLOC_LEN, 128k
fe8c2806 129 * 0x03FC 0000 RAM Copy of Monitor Code
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130 * : CONFIG_SYS_MONITOR_LEN, 256k
131 * 0x03FF FFFF [End of RAM], CONFIG_SYS_SDRAM_SIZE - 1
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132 */
133
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134#define CONFIG_POST (CONFIG_SYS_POST_MEMORY | \
135 CONFIG_SYS_POST_CPU)
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136
137
138/*
139 * select serial console configuration
140 *
141 * if either CONFIG_CONS_ON_SMC or CONFIG_CONS_ON_SCC is selected, then
142 * CONFIG_CONS_INDEX must be set to the channel number (1-2 for SMC, 1-4
143 * for SCC).
144 *
145 * if CONFIG_CONS_NONE is defined, then the serial console routines must
146 * defined elsewhere.
147 */
148#define CONFIG_CONS_ON_SMC 1 /* define if console on SMC */
149#undef CONFIG_CONS_ON_SCC /* define if console on SCC */
150#undef CONFIG_CONS_NONE /* define if console on neither */
151#define CONFIG_CONS_INDEX 1 /* which SMC/SCC channel for console */
152
153/*
154 * select ethernet configuration
155 *
156 * if either CONFIG_ETHER_ON_SCC or CONFIG_ETHER_ON_FCC is selected, then
157 * CONFIG_ETHER_INDEX must be set to the channel number (1-4 for SCC, 1-3
158 * for FCC)
159 *
160 * if CONFIG_ETHER_NONE is defined, then either the ethernet routines must be
639221c7 161 * defined elsewhere (as for the console), or CONFIG_CMD_NET must be unset.
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162 */
163
164#undef CONFIG_ETHER_ON_SCC
165#define CONFIG_ETHER_ON_FCC
166#undef CONFIG_ETHER_NONE /* define if ethernet on neither */
167
168#ifdef CONFIG_ETHER_ON_SCC
169#define CONFIG_ETHER_INDEX 1 /* which SCC/FCC channel for ethernet */
170#endif /* CONFIG_ETHER_ON_SCC */
171
172#ifdef CONFIG_ETHER_ON_FCC
173#define CONFIG_ETHER_INDEX 2 /* which SCC/FCC channel for ethernet */
78137c3c 174#undef CONFIG_ETHER_LOOPBACK_TEST /* Ethernet external loopback test */
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175#define CONFIG_MII /* MII PHY management */
176#define CONFIG_BITBANGMII /* bit-bang MII PHY management */
177/*
178 * Port pins used for bit-banged MII communictions (if applicable).
179 */
180
181#define MDIO_PORT 2 /* Port A=0, B=1, C=2, D=3 */
182#define MDIO_ACTIVE (iop->pdir |= 0x40000000)
183#define MDIO_TRISTATE (iop->pdir &= ~0x40000000)
184#define MDIO_READ ((iop->pdat & 0x40000000) != 0)
185
186#define MDIO(bit) if(bit) iop->pdat |= 0x40000000; \
187 else iop->pdat &= ~0x40000000
188
189#define MDC(bit) if(bit) iop->pdat |= 0x80000000; \
190 else iop->pdat &= ~0x80000000
191
192#define MIIDELAY udelay(50)
193#endif /* CONFIG_ETHER_ON_FCC */
194
195#if defined(CONFIG_ETHER_ON_SCC) && (CONFIG_ETHER_INDEX == 1)
196
197/*
198 * - RX clk is CLK11
199 * - TX clk is CLK12
200 */
6d0f6bcf 201# define CONFIG_SYS_CMXSCR_VALUE (CMXSCR_RS1CS_CLK11 | CMXSCR_TS1CS_CLK12)
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202
203#elif defined(CONFIG_ETHER_ON_FCC) && (CONFIG_ETHER_INDEX == 2)
204
205/*
206 * - Rx-CLK is CLK13
207 * - Tx-CLK is CLK14
208 * - Select bus for bd/buffers (see 28-13)
209 * - Enable Full Duplex in FSMR
210 */
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211# define CONFIG_SYS_CMXFCR_MASK (CMXFCR_FC2|CMXFCR_RF2CS_MSK|CMXFCR_TF2CS_MSK)
212# define CONFIG_SYS_CMXFCR_VALUE (CMXFCR_RF2CS_CLK13|CMXFCR_TF2CS_CLK14)
213# define CONFIG_SYS_CPMFCR_RAMTYPE 0
214# define CONFIG_SYS_FCC_PSMR (FCC_PSMR_FDE | FCC_PSMR_LPB)
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215
216#endif /* CONFIG_ETHER_ON_FCC, CONFIG_ETHER_INDEX */
217
218#define CONFIG_SHOW_BOOT_PROGRESS 1 /* boot progress enabled */
219
220/*
221 * Configure for RAM tests.
222 */
6d0f6bcf 223#undef CONFIG_SYS_DRAM_TEST /* calls other tests in board.c */
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224
225
226/*
227 * Status LED for power up status feedback.
228 */
229#define CONFIG_STATUS_LED 1 /* Status LED enabled */
230
231#define STATUS_LED_PAR im_ioport.iop_ppara
232#define STATUS_LED_DIR im_ioport.iop_pdira
233#define STATUS_LED_ODR im_ioport.iop_podra
234#define STATUS_LED_DAT im_ioport.iop_pdata
235
236#define STATUS_LED_BIT 0x00000800 /* LED 0 is on PA.20 */
6d0f6bcf 237#define STATUS_LED_PERIOD (CONFIG_SYS_HZ)
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238#define STATUS_LED_STATE STATUS_LED_OFF
239#define STATUS_LED_BIT1 0x00001000 /* LED 1 is on PA.19 */
6d0f6bcf 240#define STATUS_LED_PERIOD1 (CONFIG_SYS_HZ)
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241#define STATUS_LED_STATE1 STATUS_LED_OFF
242#define STATUS_LED_BIT2 0x00002000 /* LED 2 is on PA.18 */
6d0f6bcf 243#define STATUS_LED_PERIOD2 (CONFIG_SYS_HZ/2)
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244#define STATUS_LED_STATE2 STATUS_LED_ON
245
246#define STATUS_LED_ACTIVE 0 /* LED on for bit == 0 */
247
248#define STATUS_LED_YELLOW 0
249#define STATUS_LED_GREEN 1
250#define STATUS_LED_RED 2
251#define STATUS_LED_BOOT 1
252
253
254/*
1d0350ed 255 * Select SPI support configuration
fe8c2806 256 */
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257#define CONFIG_SOFT_SPI /* Enable SPI driver */
258#define MAX_SPI_BYTES 4 /* Maximum number of bytes we can handle */
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259#undef DEBUG_SPI /* Disable SPI debugging */
260
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261/*
262 * Software (bit-bang) SPI driver configuration
263 */
264#ifdef CONFIG_SOFT_SPI
265
266/*
267 * Software (bit-bang) SPI driver configuration
268 */
269#define I2C_SCLK 0x00002000 /* PD 18: Shift clock */
270#define I2C_MOSI 0x00004000 /* PD 17: Master Out, Slave In */
271#define I2C_MISO 0x00008000 /* PD 16: Master In, Slave Out */
272
273#undef SPI_INIT /* no port initialization needed */
274#define SPI_READ ((immr->im_ioport.iop_pdatd & I2C_MISO) != 0)
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275#define SPI_SDA(bit) do { \
276 if(bit) immr->im_ioport.iop_pdatd |= I2C_MOSI; \
277 else immr->im_ioport.iop_pdatd &= ~I2C_MOSI; \
278 } while (0)
279#define SPI_SCL(bit) do { \
280 if(bit) immr->im_ioport.iop_pdatd |= I2C_SCLK; \
281 else immr->im_ioport.iop_pdatd &= ~I2C_SCLK; \
282 } while (0)
1d0350ed 283#define SPI_DELAY /* No delay is needed */
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284#endif /* CONFIG_SOFT_SPI */
285
286
287/*
288 * select I2C support configuration
289 *
290 * Supported configurations are {none, software, hardware} drivers.
291 * If the software driver is chosen, there are some additional
292 * configuration items that the driver uses to drive the port pins.
293 */
294#undef CONFIG_HARD_I2C /* I2C with hardware support */
295#define CONFIG_SOFT_I2C 1 /* I2C bit-banged */
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296#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */
297#define CONFIG_SYS_I2C_SLAVE 0x7F
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298
299/*
300 * Software (bit-bang) I2C driver configuration
301 */
302#ifdef CONFIG_SOFT_I2C
303#define I2C_PORT 3 /* Port A=0, B=1, C=2, D=3 */
304#define I2C_ACTIVE (iop->pdir |= 0x00010000)
305#define I2C_TRISTATE (iop->pdir &= ~0x00010000)
306#define I2C_READ ((iop->pdat & 0x00010000) != 0)
307#define I2C_SDA(bit) if(bit) iop->pdat |= 0x00010000; \
308 else iop->pdat &= ~0x00010000
309#define I2C_SCL(bit) if(bit) iop->pdat |= 0x00020000; \
310 else iop->pdat &= ~0x00020000
311#define I2C_DELAY udelay(20) /* 1/4 I2C clock duration */
312#endif /* CONFIG_SOFT_I2C */
313
314/* Define this to reserve an entire FLASH sector for
315 * environment variables. Otherwise, the environment will be
316 * put in the same sector as U-Boot, and changing variables
317 * will erase U-Boot temporarily
318 */
0e8d1586 319#define CONFIG_ENV_IN_OWN_SECT 1
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320
321/* Define this to contain any number of null terminated strings that
322 * will be part of the default enviroment compiled into the boot image.
323 */
324#define CONFIG_EXTRA_ENV_SETTINGS \
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325"quiet=0\0" \
326"serverip=192.168.123.205\0" \
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327"ipaddr=192.168.123.203\0" \
328"checkhostname=VR8500\0" \
329"reprog="\
78137c3c 330 "bootp; " \
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331 "tftpboot 0x140000 /bdi2000/u-boot.bin; " \
332 "protect off 60000000 6003FFFF; " \
333 "erase 60000000 6003FFFF; " \
fe126d8b 334 "cp.b 140000 60000000 ${filesize}; " \
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335 "protect on 60000000 6003FFFF\0" \
336"copyenv="\
337 "protect off 60040000 6004FFFF; " \
338 "erase 60040000 6004FFFF; " \
339 "cp.b 40040000 60040000 10000; " \
340 "protect on 60040000 6004FFFF\0" \
341"copyprog="\
342 "protect off 60000000 6003FFFF; " \
343 "erase 60000000 6003FFFF; " \
344 "cp.b 40000000 60000000 40000; " \
345 "protect on 60000000 6003FFFF\0" \
346"zapenv="\
347 "protect off 40040000 4004FFFF; " \
348 "erase 40040000 4004FFFF; " \
349 "protect on 40040000 4004FFFF\0" \
350"zapotherenv="\
351 "protect off 60040000 6004FFFF; " \
352 "erase 60040000 6004FFFF; " \
353 "protect on 60040000 6004FFFF\0" \
354"root-on-initrd="\
355 "setenv bootcmd "\
356 "version\\;" \
357 "echo\\;" \
358 "bootp\\;" \
359 "setenv bootargs root=/dev/ram0 rw quiet " \
fe126d8b 360 "ip=\\${ipaddr}:\\${serverip}:\\${gatewayip}:\\${netmask}:\\${hostname}::off\\;" \
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361 "run boot-hook\\;" \
362 "bootm\0" \
363"root-on-initrd-debug="\
364 "setenv bootcmd "\
365 "version\\;" \
366 "echo\\;" \
367 "bootp\\;" \
368 "setenv bootargs root=/dev/ram0 rw debug " \
fe126d8b 369 "ip=\\${ipaddr}:\\${serverip}:\\${gatewayip}:\\${netmask}:\\${hostname}::off\\;" \
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370 "run debug-hook\\;" \
371 "run boot-hook\\;" \
372 "bootm\0" \
373"root-on-nfs="\
374 "setenv bootcmd "\
375 "version\\;" \
376 "echo\\;" \
377 "bootp\\;" \
378 "setenv bootargs root=/dev/nfs rw quiet " \
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379 "nfsroot=\\${serverip}:\\${rootpath} " \
380 "ip=\\${ipaddr}:\\${serverip}:\\${gatewayip}:\\${netmask}:\\${hostname}::off\\;" \
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381 "run boot-hook\\;" \
382 "bootm\0" \
383"root-on-nfs-debug="\
384 "setenv bootcmd "\
385 "version\\;" \
386 "echo\\;" \
387 "bootp\\;" \
388 "setenv bootargs root=/dev/nfs rw debug " \
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389 "nfsroot=\\${serverip}:\\${rootpath} " \
390 "ip=\\${ipaddr}:\\${serverip}:\\${gatewayip}:\\${netmask}:\\${hostname}::off\\;" \
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391 "run debug-hook\\;" \
392 "run boot-hook\\;" \
393 "bootm\0" \
394"debug-checkout="\
395 "setenv checkhostname;" \
396 "setenv ethaddr 00:09:70:00:00:01;" \
397 "bootp;" \
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398 "setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} debug " \
399 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off;" \
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400 "run debug-hook;" \
401 "run boot-hook;" \
402 "bootm\0" \
403"debug-hook="\
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404 "echo ipaddr ${ipaddr};" \
405 "echo serverip ${serverip};" \
406 "echo gatewayip ${gatewayip};" \
407 "echo netmask ${netmask};" \
408 "echo hostname ${hostname}\0" \
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409"ana=run adc ; run dac\0" \
410"adc=run adc-12 ; run adc-34\0" \
411"adc-12=echo ### ADC-12 ; imd.b e 81 e\0" \
412"adc-34=echo ### ADC-34 ; imd.b f 81 e\0" \
413"dac=echo ### DAC ; imd.b 11 81 5\0" \
78137c3c 414"boot-hook=echo\0"
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415
416/* What should the console's baud rate be? */
417#define CONFIG_BAUDRATE 9600
418
419/* Ethernet MAC address */
420#define CONFIG_ETHADDR 00:09:70:00:00:00
421
422/* The default Ethernet MAC address can be overwritten just once */
423#ifdef CONFIG_ETHADDR
424#define CONFIG_OVERWRITE_ETHADDR_ONCE 1
425#endif
426
427/*
428 * Define this to do some miscellaneous board-specific initialization.
429 */
430#define CONFIG_MISC_INIT_R
431
432/* Set to a positive value to delay for running BOOTCOMMAND */
433#define CONFIG_BOOTDELAY 1 /* autoboot after 1 second */
434
435/* Be selective on what keys can delay or stop the autoboot process
436 * To stop use: " "
437 */
438#define CONFIG_AUTOBOOT_KEYED
f2302d44 439#define CONFIG_AUTOBOOT_PROMPT "Autobooting...\n"
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440#define CONFIG_AUTOBOOT_STOP_STR " "
441#undef CONFIG_AUTOBOOT_DELAY_STR
442#define CONFIG_ZERO_BOOTDELAY_CHECK
443#define DEBUG_BOOTKEYS 0
444
445/* Define a command string that is automatically executed when no character
446 * is read on the console interface withing "Boot Delay" after reset.
447 */
53677ef1 448#undef CONFIG_BOOT_ROOT_INITRD /* Use ram disk for the root file system */
b79a11cc 449#define CONFIG_BOOT_ROOT_NFS /* Use a NFS mounted root file system */
fe8c2806 450
42dfe7a1 451#ifdef CONFIG_BOOT_ROOT_INITRD
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452#define CONFIG_BOOTCOMMAND \
453 "version;" \
454 "echo;" \
455 "bootp;" \
456 "setenv bootargs root=/dev/ram0 rw quiet " \
fe126d8b 457 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off;" \
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458 "run boot-hook;" \
459 "bootm"
460#endif /* CONFIG_BOOT_ROOT_INITRD */
461
42dfe7a1 462#ifdef CONFIG_BOOT_ROOT_NFS
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463#define CONFIG_BOOTCOMMAND \
464 "version;" \
465 "echo;" \
466 "bootp;" \
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467 "setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} quiet " \
468 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off;" \
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469 "run boot-hook;" \
470 "bootm"
471#endif /* CONFIG_BOOT_ROOT_NFS */
472
473#define CONFIG_BOOTP_RANDOM_DELAY /* Randomize the BOOTP retry delay */
474
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475/*
476 * BOOTP options
fe8c2806 477 */
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478#define CONFIG_BOOTP_SUBNETMASK
479#define CONFIG_BOOTP_GATEWAY
480#define CONFIG_BOOTP_HOSTNAME
481#define CONFIG_BOOTP_BOOTPATH
482#define CONFIG_BOOTP_BOOTFILESIZE
483#define CONFIG_BOOTP_DNS
484#define CONFIG_BOOTP_DNS2
485#define CONFIG_BOOTP_SEND_HOSTNAME
486
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487
488/* undef this to save memory */
6d0f6bcf 489#define CONFIG_SYS_LONGHELP
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490
491/* Monitor Command Prompt */
6d0f6bcf 492#define CONFIG_SYS_PROMPT "=> "
fe8c2806 493
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494#undef CONFIG_SYS_HUSH_PARSER
495#ifdef CONFIG_SYS_HUSH_PARSER
496#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
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497#endif
498
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499/* When CONFIG_TIMESTAMP is selected, the timestamp (date and time)
500 * of an image is printed by image commands like bootm or iminfo.
501 */
502#define CONFIG_TIMESTAMP
503
42d1f039 504/* If this variable is defined, an environment variable named "ver"
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505 * is created by U-Boot showing the U-Boot version.
506 */
507#define CONFIG_VERSION_VARIABLE
508
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509
510/*
511 * Command line configuration.
512 */
513#include <config_cmd_default.h>
514
515#define CONFIG_CMD_ELF
516#define CONFIG_CMD_ASKENV
517#define CONFIG_CMD_I2C
518#define CONFIG_CMD_SPI
519#define CONFIG_CMD_SDRAM
520#define CONFIG_CMD_REGINFO
521#define CONFIG_CMD_IMMAP
522#define CONFIG_CMD_IRQ
523#define CONFIG_CMD_PING
524
525#undef CONFIG_CMD_KGDB
526
fe8c2806 527#ifdef CONFIG_ETHER_ON_FCC
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528#define CONFIG_CMD_MII
529#endif
530
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531
532/* Where do the internal registers live? */
6d0f6bcf 533#define CONFIG_SYS_IMMR 0xF0000000
fe8c2806 534
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535#undef CONFIG_WATCHDOG /* disable the watchdog */
536
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537/*****************************************************************************
538 *
539 * You should not have to modify any of the following settings
540 *
541 *****************************************************************************/
542
543#define CONFIG_MPC8260 1 /* This is an MPC8260 CPU */
544#define CONFIG_SBC8260 1 /* on an EST SBC8260 Board */
545#define CONFIG_SACSng 1 /* munged for the SACSng */
9c4c5ae3 546#define CONFIG_CPM2 1 /* Has a CPM2 */
fe8c2806 547
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548/*
549 * Miscellaneous configurable options
550 */
6d0f6bcf 551#define CONFIG_SYS_BOOTM_HEADER_QUIET 1 /* Suppress the image header dump */
42d1f039 552 /* in the bootm command. */
6d0f6bcf 553#define CONFIG_SYS_BOOTM_PROGESS_QUIET 1 /* Suppress the progress displays, */
42d1f039 554 /* "## <message>" from the bootm cmd */
6d0f6bcf 555#define CONFIG_SYS_BOOTP_CHECK_HOSTNAME 1 /* If checkhostname environment is */
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556 /* defined, then the hostname param */
557 /* validated against checkhostname. */
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558#define CONFIG_SYS_BOOTP_RETRY_COUNT 0x40000000 /* # of timeouts before giving up */
559#define CONFIG_SYS_BOOTP_SHORT_RANDOM_DELAY 1 /* Use a short random delay value */
42d1f039 560 /* (limited to maximum of 1024 msec) */
6d0f6bcf 561#define CONFIG_SYS_CHK_FOR_ABORT_AT_LEAST_ONCE 1
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562 /* Check for abort key presses */
563 /* at least once in dependent of the */
564 /* CONFIG_BOOTDELAY value. */
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565#define CONFIG_SYS_CONSOLE_INFO_QUIET 1 /* Don't print console @ startup */
566#define CONFIG_SYS_FAULT_ECHO_LINK_DOWN 1 /* Echo the inverted Ethernet link */
42d1f039 567 /* state to the fault LED. */
6d0f6bcf 568#define CONFIG_SYS_FAULT_MII_ADDR 0x02 /* MII addr of the PHY to check for */
42d1f039 569 /* the Ethernet link state. */
6d0f6bcf 570#define CONFIG_SYS_STATUS_FLASH_UNTIL_TFTP_OK 1 /* Keeping the status LED flashing */
42d1f039 571 /* until the TFTP is successful. */
6d0f6bcf 572#define CONFIG_SYS_STATUS_OFF_AFTER_NETBOOT 1 /* After a successful netboot, */
42d1f039 573 /* turn off the STATUS LEDs. */
6d0f6bcf 574#define CONFIG_SYS_TFTP_BLINK_STATUS_ON_DATA_IN 1 /* Blink status LED based on */
42d1f039 575 /* incoming data. */
6d0f6bcf 576#define CONFIG_SYS_TFTP_BLOCKS_PER_HASH 100 /* For every XX blocks, output a '#' */
42d1f039 577 /* to signify that tftp is moving. */
6d0f6bcf 578#define CONFIG_SYS_TFTP_HASHES_PER_FLASH 200 /* For every '#' hashes, */
42d1f039 579 /* flash the status LED. */
6d0f6bcf 580#define CONFIG_SYS_TFTP_HASHES_PER_LINE 65 /* Only output XX '#'s per line */
42d1f039 581 /* during the tftp file transfer. */
6d0f6bcf 582#define CONFIG_SYS_TFTP_PROGESS_QUIET 1 /* Suppress the progress displays */
42d1f039 583 /* '#'s from the tftp command. */
6d0f6bcf 584#define CONFIG_SYS_TFTP_STATUS_QUIET 1 /* Suppress the status displays */
42d1f039 585 /* issued during the tftp command. */
6d0f6bcf 586#define CONFIG_SYS_TFTP_TIMEOUT_COUNT 5 /* How many timeouts TFTP will allow */
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587 /* before it gives up. */
588
46da1e96 589#if defined(CONFIG_CMD_KGDB)
6d0f6bcf 590# define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
fe8c2806 591#else
6d0f6bcf 592# define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
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593#endif
594
595/* Print Buffer Size */
6d0f6bcf 596#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT)+16)
fe8c2806 597
6d0f6bcf 598#define CONFIG_SYS_MAXARGS 32 /* max number of command args */
fe8c2806 599
6d0f6bcf 600#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
fe8c2806 601
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602#define CONFIG_SYS_LOAD_ADDR 0x400000 /* default load address */
603#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */
fe8c2806 604
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605#define CONFIG_SYS_ALT_MEMTEST /* Select full-featured memory test */
606#define CONFIG_SYS_MEMTEST_START 0x2000 /* memtest works from the end of */
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607 /* the exception vector table */
608 /* to the end of the DRAM */
609 /* less monitor and malloc area */
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610#define CONFIG_SYS_STACK_USAGE 0x10000 /* Reserve 64k for the stack usage */
611#define CONFIG_SYS_MEM_END_USAGE ( CONFIG_SYS_MONITOR_LEN \
612 + CONFIG_SYS_MALLOC_LEN \
0e8d1586 613 + CONFIG_ENV_SECT_SIZE \
6d0f6bcf 614 + CONFIG_SYS_STACK_USAGE )
fe8c2806 615
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616#define CONFIG_SYS_MEMTEST_END ( CONFIG_SYS_SDRAM_SIZE * 1024 * 1024 \
617 - CONFIG_SYS_MEM_END_USAGE )
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618
619/* valid baudrates */
6d0f6bcf 620#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
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621
622/*
623 * Low Level Configuration Settings
624 * (address mappings, register initial values, etc.)
625 * You should know what you are doing if you make changes here.
626 */
627
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628#define CONFIG_SYS_FLASH_BASE CONFIG_SYS_FLASH0_BASE
629#define CONFIG_SYS_FLASH_SIZE CONFIG_SYS_FLASH0_SIZE
630#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_SDRAM0_BASE
631#define CONFIG_SYS_SDRAM_SIZE CONFIG_SYS_SDRAM0_SIZE
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632
633/*-----------------------------------------------------------------------
634 * Hard Reset Configuration Words
635 */
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636#if defined(CONFIG_SYS_SBC_BOOT_LOW)
637# define CONFIG_SYS_SBC_HRCW_BOOT_FLAGS (HRCW_CIP | HRCW_BMS)
fe8c2806 638#else
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639# define CONFIG_SYS_SBC_HRCW_BOOT_FLAGS (0)
640#endif /* defined(CONFIG_SYS_SBC_BOOT_LOW) */
fe8c2806 641
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642/* get the HRCW ISB field from CONFIG_SYS_IMMR */
643#define CONFIG_SYS_SBC_HRCW_IMMR ( ((CONFIG_SYS_IMMR & 0x10000000) >> 10) | \
644 ((CONFIG_SYS_IMMR & 0x01000000) >> 7) | \
645 ((CONFIG_SYS_IMMR & 0x00100000) >> 4) )
fe8c2806 646
6d0f6bcf 647#define CONFIG_SYS_HRCW_MASTER ( HRCW_BPS10 | \
fe8c2806 648 HRCW_DPPC11 | \
6d0f6bcf 649 CONFIG_SYS_SBC_HRCW_IMMR | \
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650 HRCW_MMR00 | \
651 HRCW_LBPC11 | \
652 HRCW_APPC10 | \
653 HRCW_CS10PC00 | \
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654 (CONFIG_SYS_SBC_MODCK_H & HRCW_MODCK_H1111) | \
655 CONFIG_SYS_SBC_HRCW_BOOT_FLAGS )
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656
657/* no slaves */
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658#define CONFIG_SYS_HRCW_SLAVE1 0
659#define CONFIG_SYS_HRCW_SLAVE2 0
660#define CONFIG_SYS_HRCW_SLAVE3 0
661#define CONFIG_SYS_HRCW_SLAVE4 0
662#define CONFIG_SYS_HRCW_SLAVE5 0
663#define CONFIG_SYS_HRCW_SLAVE6 0
664#define CONFIG_SYS_HRCW_SLAVE7 0
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665
666/*-----------------------------------------------------------------------
667 * Definitions for initial stack pointer and data area (in DPRAM)
668 */
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669#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR
670#define CONFIG_SYS_INIT_RAM_END 0x4000 /* End of used area in DPRAM */
671#define CONFIG_SYS_GBL_DATA_SIZE 128 /* bytes reserved for initial data */
672#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
673#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
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674
675/*-----------------------------------------------------------------------
676 * Start addresses for the final memory configuration
677 * (Set up by the startup code)
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678 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
679 * Note also that the logic that sets CONFIG_SYS_RAMBOOT is platform dependent.
fe8c2806 680 */
6d0f6bcf 681#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH0_BASE
fe8c2806 682
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683#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
684# define CONFIG_SYS_RAMBOOT
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685#endif
686
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687#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
688#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
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689
690/*
691 * For booting Linux, the board info and command line data
692 * have to be in the first 8 MB of memory, since this is
693 * the maximum mapped by the Linux kernel during initialization.
694 */
6d0f6bcf 695#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
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696
697/*-----------------------------------------------------------------------
698 * FLASH and environment organization
699 */
700
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701#define CONFIG_SYS_FLASH_CFI 1 /* Flash is CFI conformant */
702#undef CONFIG_SYS_FLASH_PROTECTION /* use hardware protection */
703#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of memory banks */
704#define CONFIG_SYS_MAX_FLASH_SECT (64+4) /* max number of sectors on one chip */
fe8c2806 705
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706#define CONFIG_SYS_FLASH_ERASE_TOUT 8000 /* Timeout for Flash Erase (in ms) */
707#define CONFIG_SYS_FLASH_WRITE_TOUT 1 /* Timeout for Flash Write (in ms) */
fe8c2806 708
6d0f6bcf 709#ifndef CONFIG_SYS_RAMBOOT
5a1aceb0 710# define CONFIG_ENV_IS_IN_FLASH 1
fe8c2806 711
0e8d1586 712# ifdef CONFIG_ENV_IN_OWN_SECT
6d0f6bcf 713# define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
0e8d1586 714# define CONFIG_ENV_SECT_SIZE 0x10000
fe8c2806 715# else
6d0f6bcf 716# define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_SYS_MONITOR_LEN - CONFIG_ENV_SECT_SIZE)
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717# define CONFIG_ENV_SIZE 0x1000 /* Total Size of Environment Sector */
718# define CONFIG_ENV_SECT_SIZE 0x10000 /* see README - env sect real size */
719# endif /* CONFIG_ENV_IN_OWN_SECT */
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720
721#else
9314cee6 722# define CONFIG_ENV_IS_IN_NVRAM 1
6d0f6bcf 723# define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000)
0e8d1586 724# define CONFIG_ENV_SIZE 0x200
6d0f6bcf 725#endif /* CONFIG_SYS_RAMBOOT */
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726
727/*-----------------------------------------------------------------------
728 * Cache Configuration
729 */
6d0f6bcf 730#define CONFIG_SYS_CACHELINE_SIZE 32 /* For MPC8260 CPU */
fe8c2806 731
46da1e96 732#if defined(CONFIG_CMD_KGDB)
6d0f6bcf 733# define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */
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734#endif
735
736/*-----------------------------------------------------------------------
737 * HIDx - Hardware Implementation-dependent Registers 2-11
738 *-----------------------------------------------------------------------
739 * HID0 also contains cache control - initially enable both caches and
740 * invalidate contents, then the final state leaves only the instruction
741 * cache enabled. Note that Power-On and Hard reset invalidate the caches,
742 * but Soft reset does not.
743 *
744 * HID1 has only read-only information - nothing to set.
745 */
6d0f6bcf 746#define CONFIG_SYS_HID0_INIT (HID0_ICE |\
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747 HID0_DCE |\
748 HID0_ICFI |\
749 HID0_DCI |\
750 HID0_IFEM |\
751 HID0_ABE)
752
6d0f6bcf 753#define CONFIG_SYS_HID0_FINAL (HID0_ICE |\
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754 HID0_IFEM |\
755 HID0_ABE |\
756 HID0_EMCP)
6d0f6bcf 757#define CONFIG_SYS_HID2 0
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758
759/*-----------------------------------------------------------------------
760 * RMR - Reset Mode Register
761 *-----------------------------------------------------------------------
762 */
6d0f6bcf 763#define CONFIG_SYS_RMR 0
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764
765/*-----------------------------------------------------------------------
766 * BCR - Bus Configuration 4-25
767 *-----------------------------------------------------------------------
768 */
6d0f6bcf 769#define CONFIG_SYS_BCR (BCR_ETM)
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770
771/*-----------------------------------------------------------------------
772 * SIUMCR - SIU Module Configuration 4-31
773 *-----------------------------------------------------------------------
774 */
775
6d0f6bcf 776#define CONFIG_SYS_SIUMCR (SIUMCR_DPPC11 |\
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777 SIUMCR_L2CPC00 |\
778 SIUMCR_APPC10 |\
779 SIUMCR_MMR00)
780
781
782/*-----------------------------------------------------------------------
783 * SYPCR - System Protection Control 11-9
784 * SYPCR can only be written once after reset!
785 *-----------------------------------------------------------------------
786 * Watchdog & Bus Monitor Timer max, 60x Bus Monitor enable
787 */
78137c3c 788#if defined(CONFIG_WATCHDOG)
6d0f6bcf 789#define CONFIG_SYS_SYPCR (SYPCR_SWTC |\
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790 SYPCR_BMT |\
791 SYPCR_PBME |\
792 SYPCR_LBME |\
793 SYPCR_SWRI |\
794 SYPCR_SWP |\
42d1f039 795 SYPCR_SWE)
78137c3c 796#else
6d0f6bcf 797#define CONFIG_SYS_SYPCR (SYPCR_SWTC |\
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798 SYPCR_BMT |\
799 SYPCR_PBME |\
800 SYPCR_LBME |\
801 SYPCR_SWRI |\
802 SYPCR_SWP)
78137c3c 803#endif /* CONFIG_WATCHDOG */
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804
805/*-----------------------------------------------------------------------
806 * TMCNTSC - Time Counter Status and Control 4-40
807 *-----------------------------------------------------------------------
808 * Clear once per Second and Alarm Interrupt Status, Set 32KHz timersclk,
809 * and enable Time Counter
810 */
6d0f6bcf 811#define CONFIG_SYS_TMCNTSC (TMCNTSC_SEC |\
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812 TMCNTSC_ALR |\
813 TMCNTSC_TCF |\
814 TMCNTSC_TCE)
815
816/*-----------------------------------------------------------------------
817 * PISCR - Periodic Interrupt Status and Control 4-42
818 *-----------------------------------------------------------------------
819 * Clear Periodic Interrupt Status, Set 32KHz timersclk, and enable
820 * Periodic timer
821 */
6d0f6bcf 822#define CONFIG_SYS_PISCR (PISCR_PS |\
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823 PISCR_PTF |\
824 PISCR_PTE)
825
826/*-----------------------------------------------------------------------
827 * SCCR - System Clock Control 9-8
828 *-----------------------------------------------------------------------
829 */
6d0f6bcf 830#define CONFIG_SYS_SCCR 0
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831
832/*-----------------------------------------------------------------------
833 * RCCR - RISC Controller Configuration 13-7
834 *-----------------------------------------------------------------------
835 */
6d0f6bcf 836#define CONFIG_SYS_RCCR 0
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837
838/*
839 * Initialize Memory Controller:
840 *
841 * Bank Bus Machine PortSz Device
842 * ---- --- ------- ------ ------
843 * 0 60x GPCM 16 bit FLASH (primary flash - 2MB)
844 * 1 60x GPCM -- bit (Unused)
845 * 2 60x SDRAM 64 bit SDRAM (DIMM)
846 * 3 60x SDRAM 64 bit SDRAM (DIMM)
847 * 4 60x GPCM -- bit (Unused)
848 * 5 60x GPCM -- bit (Unused)
849 * 6 60x GPCM 16 bit FLASH (secondary flash - 2MB)
850 */
851
852/*-----------------------------------------------------------------------
853 * BR0,BR1 - Base Register
854 * Ref: Section 10.3.1 on page 10-14
855 * OR0,OR1 - Option Register
856 * Ref: Section 10.3.2 on page 10-18
857 *-----------------------------------------------------------------------
858 */
859
860/* Bank 0 - Primary FLASH
861 */
862
863/* BR0 is configured as follows:
864 *
865 * - Base address of 0x40000000
866 * - 16 bit port size
867 * - Data errors checking is disabled
868 * - Read and write access
869 * - GPCM 60x bus
870 * - Access are handled by the memory controller according to MSEL
871 * - Not used for atomic operations
872 * - No data pipelining is done
873 * - Valid
874 */
6d0f6bcf 875#define CONFIG_SYS_BR0_PRELIM ((CONFIG_SYS_FLASH0_BASE & BRx_BA_MSK) |\
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876 BRx_PS_16 |\
877 BRx_MS_GPCM_P |\
878 BRx_V)
879
880/* OR0 is configured as follows:
881 *
882 * - 4 MB
883 * - *BCTL0 is asserted upon access to the current memory bank
884 * - *CW / *WE are negated a quarter of a clock earlier
885 * - *CS is output at the same time as the address lines
886 * - Uses a clock cycle length of 5
887 * - *PSDVAL is generated internally by the memory controller
888 * unless *GTA is asserted earlier externally.
889 * - Relaxed timing is generated by the GPCM for accesses
890 * initiated to this memory region.
891 * - One idle clock is inserted between a read access from the
892 * current bank and the next access.
893 */
6d0f6bcf 894#define CONFIG_SYS_OR0_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH0_SIZE) |\
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895 ORxG_CSNT |\
896 ORxG_ACS_DIV1 |\
897 ORxG_SCY_5_CLK |\
898 ORxG_TRLX |\
899 ORxG_EHTR)
900
901/*-----------------------------------------------------------------------
902 * BR2,BR3 - Base Register
903 * Ref: Section 10.3.1 on page 10-14
904 * OR2,OR3 - Option Register
905 * Ref: Section 10.3.2 on page 10-16
906 *-----------------------------------------------------------------------
907 */
908
909/* Bank 2,3 - SDRAM DIMM
910 */
911
912/* The BR2 is configured as follows:
913 *
914 * - Base address of 0x00000000
915 * - 64 bit port size (60x bus only)
916 * - Data errors checking is disabled
917 * - Read and write access
918 * - SDRAM 60x bus
919 * - Access are handled by the memory controller according to MSEL
920 * - Not used for atomic operations
921 * - No data pipelining is done
922 * - Valid
923 */
6d0f6bcf 924#define CONFIG_SYS_BR2_PRELIM ((CONFIG_SYS_SDRAM0_BASE & BRx_BA_MSK) |\
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925 BRx_PS_64 |\
926 BRx_MS_SDRAM_P |\
927 BRx_V)
928
6d0f6bcf 929#define CONFIG_SYS_BR3_PRELIM ((CONFIG_SYS_SDRAM0_BASE & BRx_BA_MSK) |\
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930 BRx_PS_64 |\
931 BRx_MS_SDRAM_P |\
932 BRx_V)
933
934/* With a 64 MB DIMM, the OR2 is configured as follows:
935 *
936 * - 64 MB
937 * - 4 internal banks per device
938 * - Row start address bit is A8 with PSDMR[PBI] = 0
939 * - 12 row address lines
940 * - Back-to-back page mode
941 * - Internal bank interleaving within save device enabled
942 */
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943#if (CONFIG_SYS_SDRAM0_SIZE == 64)
944#define CONFIG_SYS_OR2_PRELIM (MEG_TO_AM(CONFIG_SYS_SDRAM0_SIZE) |\
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945 ORxS_BPD_4 |\
946 ORxS_ROWST_PBI0_A8 |\
947 ORxS_NUMR_12)
948#else
949#error "INVALID SDRAM CONFIGURATION"
950#endif
951
952/*-----------------------------------------------------------------------
953 * PSDMR - 60x Bus SDRAM Mode Register
954 * Ref: Section 10.3.3 on page 10-21
955 *-----------------------------------------------------------------------
956 */
957
958/* Address that the DIMM SPD memory lives at.
959 */
960#define SDRAM_SPD_ADDR 0x50
961
6d0f6bcf 962#if (CONFIG_SYS_SDRAM0_SIZE == 64)
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963/* With a 64 MB DIMM, the PSDMR is configured as follows:
964 *
965 * - Bank Based Interleaving,
966 * - Refresh Enable,
967 * - Address Multiplexing where A5 is output on A14 pin
968 * (A6 on A15, and so on),
969 * - use address pins A14-A16 as bank select,
970 * - A9 is output on SDA10 during an ACTIVATE command,
971 * - earliest timing for ACTIVATE command after REFRESH command is 7 clocks,
972 * - earliest timing for ACTIVATE or REFRESH command after PRECHARGE command
973 * is 3 clocks,
974 * - earliest timing for READ/WRITE command after ACTIVATE command is
975 * 2 clocks,
976 * - earliest timing for PRECHARGE after last data was read is 1 clock,
977 * - earliest timing for PRECHARGE after last data was written is 1 clock,
978 * - CAS Latency is 2.
979 */
6d0f6bcf 980#define CONFIG_SYS_PSDMR (PSDMR_RFEN |\
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981 PSDMR_SDAM_A14_IS_A5 |\
982 PSDMR_BSMA_A14_A16 |\
983 PSDMR_SDA10_PBI0_A9 |\
984 PSDMR_RFRC_7_CLK |\
985 PSDMR_PRETOACT_3W |\
986 PSDMR_ACTTORW_2W |\
987 PSDMR_LDOTOPRE_1C |\
988 PSDMR_WRC_1C |\
989 PSDMR_CL_2)
990#else
991#error "INVALID SDRAM CONFIGURATION"
992#endif
993
994/*
995 * Shoot for approximately 1MHz on the prescaler.
996 */
997#if (CONFIG_8260_CLKIN >= (60 * 1000 * 1000))
6d0f6bcf 998#define CONFIG_SYS_MPTPR MPTPR_PTP_DIV64
fe8c2806 999#elif (CONFIG_8260_CLKIN >= (30 * 1000 * 1000))
6d0f6bcf 1000#define CONFIG_SYS_MPTPR MPTPR_PTP_DIV32
fe8c2806 1001#else
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1002#warning "Unconfigured bus clock freq: check CONFIG_SYS_MPTPR and CONFIG_SYS_PSRT are OK"
1003#define CONFIG_SYS_MPTPR MPTPR_PTP_DIV32
fe8c2806 1004#endif
6d0f6bcf 1005#define CONFIG_SYS_PSRT 14
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1006
1007
1008/*-----------------------------------------------------------------------
1009 * BR6 - Base Register
1010 * Ref: Section 10.3.1 on page 10-14
1011 * OR6 - Option Register
1012 * Ref: Section 10.3.2 on page 10-18
1013 *-----------------------------------------------------------------------
1014 */
1015
1016/* Bank 6 - Secondary FLASH
1017 *
1018 * The secondary FLASH is connected to *CS6
1019 */
6d0f6bcf 1020#if (defined(CONFIG_SYS_FLASH1_BASE) && defined(CONFIG_SYS_FLASH1_SIZE))
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1021
1022/* BR6 is configured as follows:
1023 *
1024 * - Base address of 0x60000000
1025 * - 16 bit port size
1026 * - Data errors checking is disabled
1027 * - Read and write access
1028 * - GPCM 60x bus
1029 * - Access are handled by the memory controller according to MSEL
1030 * - Not used for atomic operations
1031 * - No data pipelining is done
1032 * - Valid
1033 */
6d0f6bcf 1034# define CONFIG_SYS_BR6_PRELIM ((CONFIG_SYS_FLASH1_BASE & BRx_BA_MSK) |\
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1035 BRx_PS_16 |\
1036 BRx_MS_GPCM_P |\
1037 BRx_V)
1038
1039/* OR6 is configured as follows:
1040 *
1041 * - 2 MB
1042 * - *BCTL0 is asserted upon access to the current memory bank
1043 * - *CW / *WE are negated a quarter of a clock earlier
1044 * - *CS is output at the same time as the address lines
1045 * - Uses a clock cycle length of 5
1046 * - *PSDVAL is generated internally by the memory controller
1047 * unless *GTA is asserted earlier externally.
1048 * - Relaxed timing is generated by the GPCM for accesses
1049 * initiated to this memory region.
1050 * - One idle clock is inserted between a read access from the
1051 * current bank and the next access.
1052 */
6d0f6bcf 1053# define CONFIG_SYS_OR6_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH1_SIZE) |\
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1054 ORxG_CSNT |\
1055 ORxG_ACS_DIV1 |\
1056 ORxG_SCY_5_CLK |\
1057 ORxG_TRLX |\
1058 ORxG_EHTR)
6d0f6bcf 1059#endif /* (defined(CONFIG_SYS_FLASH1_BASE) && defined(CONFIG_SYS_FLASH1_SIZE)) */
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1060
1061/*
1062 * Internal Definitions
1063 *
1064 * Boot Flags
1065 */
1066#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
1067#define BOOTFLAG_WARM 0x02 /* Software reboot */
1068
1069#endif /* __CONFIG_H */