[people/ms/u-boot.git] / include / configs / sbc8240.h

/*
 * (C) Copyright 2001
 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */

/*
 * Configuration settings for the sbc8240 board.
 */

/* ------------------------------------------------------------------------- */

/*
 * board/config.h - configuration options, board specific
 */

#ifndef __CONFIG_H
#define __CONFIG_H

/*
 * High Level Configuration Options
 * (easy to change)
 */

#define CONFIG_MPC824X		1
#define CONFIG_MPC8240		1
#define CONFIG_WRSBC8240	1

#define	CONFIG_SYS_TEXT_BASE	0xFFF00000

#define CONFIG_CONS_INDEX	1
#define CONFIG_BAUDRATE		9600
#define CONFIG_SYS_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }

#define CONFIG_PREBOOT  "echo;echo Welcome to U-Boot for the sbc8240;echo;echo Type \"? or help\" to get on-line help;echo"

#undef CONFIG_BOOTARGS

#define CONFIG_BOOTCOMMAND	"version;echo;tftpboot $loadaddr $loadfile;bootvx"	/* autoboot command	*/

#define CONFIG_EXTRA_ENV_SETTINGS \
	"bootargs=$fei(0,0)host:/T221ppc/target/config/sbc8240/vxWorks.st " \
	       "e=192.168.193.102 h=192.168.193.99 u=target pw=hello f=0x08 " \
	       "tn=sbc8240 o=fei \0" \
	"env_startaddr=FFF70000\0" \
	"env_endaddr=FFF7FFFF\0" \
	"loadfile=vxWorks.st\0" \
	"loadaddr=0x01000000\0" \
	"net_load=tftpboot $loadaddr $loadfile\0" \
	"uboot_startaddr=FFF00000\0" \
	"uboot_endaddr=FFF3FFFF\0" \
	"update=tftp $loadaddr /u-boot.bin;" \
		"protect off $uboot_startaddr $uboot_endaddr;" \
		"era $uboot_startaddr $uboot_endaddr;" \
		"cp.b $loadaddr $uboot_startaddr $filesize;" \
		"protect on $uboot_startaddr $uboot_endaddr\0" \
	"zapenv=protect off $env_startaddr $env_endaddr;" \
		"era $env_startaddr $env_endaddr;" \
		"protect on $env_startaddr $env_endaddr\0"

#define CONFIG_BOOTDELAY	5

/*
 * BOOTP options
 */
#define CONFIG_BOOTP_SUBNETMASK
#define CONFIG_BOOTP_GATEWAY
#define CONFIG_BOOTP_HOSTNAME
#define CONFIG_BOOTP_BOOTPATH
#define CONFIG_BOOTP_BOOTFILESIZE


#define CONFIG_ENV_OVERWRITE


/*
 * Command line configuration.
 */
#include <config_cmd_default.h>

#define CONFIG_CMD_BSP
#define CONFIG_CMD_DIAG
#define CONFIG_CMD_ELF
#define CONFIG_CMD_SAVEENV
#define CONFIG_CMD_FLASH
#define CONFIG_CMD_PCI
#define CONFIG_CMD_PING
#define CONFIG_CMD_SDRAM


/*
 * Miscellaneous configurable options
 */
#define CONFIG_SYS_LONGHELP			/* undef to save memory		*/
#define CONFIG_SYS_PROMPT	"=> "		/* Monitor Command Prompt	*/
#define CONFIG_SYS_CBSIZE	256		/* Console I/O Buffer Size	*/

#if 1
#define CONFIG_SYS_HUSH_PARSER		1	/* use "hush" command parser	*/
#endif
#ifdef CONFIG_SYS_HUSH_PARSER
#define CONFIG_SYS_PROMPT_HUSH_PS2	"> "
#endif

#define CONFIG_ETHADDR          DE:AD:BE:EF:01:01    /* Ethernet address */
#define CONFIG_IPADDR           192.168.193.102
#define CONFIG_NETMASK          255.255.255.248
#define CONFIG_SERVERIP         192.168.193.99

#define CONFIG_STATUS_LED               /* Status LED enabled           */
#define CONFIG_BOARD_SPECIFIC_LED       /* version has board specific leds */

#define STATUS_LED_BIT          0x00000001
#define STATUS_LED_PERIOD       (CONFIG_SYS_HZ / 2)
#define STATUS_LED_STATE        STATUS_LED_BLINKING
#define STATUS_LED_ACTIVE       0       /* LED on for bit == 0  */
#define STATUS_LED_BOOT         0       /* LED 0 used for boot status */

#ifndef __ASSEMBLY__
/* LEDs */
typedef unsigned int led_id_t;

#define __led_toggle(_msk) \
	do { \
		*((volatile char *) (CONFIG_SYS_LED_BASE)) ^= (_msk); \
	} while(0)

#define __led_set(_msk, _st) \
	do { \
		if ((_st)) \
			*((volatile char *) (CONFIG_SYS_LED_BASE)) |= (_msk); \
		else \
			*((volatile char *) (CONFIG_SYS_LED_BASE)) &= ~(_msk); \
	} while(0)

#define __led_init(msk, st) __led_set(msk, st)

#endif

#define CONFIG_MISC_INIT_R
#define CONFIG_SYS_LED_BASE	0xFFE80000

/* Print Buffer Size
 */
#define CONFIG_SYS_PBSIZE	(CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)

#define CONFIG_SYS_MAXARGS	16		/* max number of command args	*/
#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size	*/
#define CONFIG_SYS_LOAD_ADDR	0x00100000	/* Default load address		*/

/*-----------------------------------------------------------------------
 * Start addresses for the final memory configuration
 * (Set up by the startup code)
 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
 */
#define CONFIG_SYS_SDRAM_BASE	    0x00000000
#define CONFIG_SYS_FLASH_BASE	    0xFFF00000

#define CONFIG_SYS_RESET_ADDRESS   0xFFF00100

#define CONFIG_SYS_EUMB_ADDR	    0xFCE00000

#define CONFIG_SYS_MONITOR_BASE    CONFIG_SYS_TEXT_BASE

#define CONFIG_SYS_MONITOR_LEN	    (256 << 10) /* Reserve 256 kB for Monitor	*/
#define CONFIG_SYS_MALLOC_LEN	    (128 << 10) /* Reserve 128 kB for malloc()	*/

#define CONFIG_SYS_MEMTEST_START   0x00004000	/* memtest works on		*/
#define CONFIG_SYS_MEMTEST_END	    0x02000000	/* 0 ... 32 MB in DRAM		*/

	/* Maximum amount of RAM.
	 */
#define CONFIG_SYS_MAX_RAM_SIZE    0x10000000

#if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE
#undef CONFIG_SYS_RAMBOOT
#else
#define CONFIG_SYS_RAMBOOT
#endif

/*-----------------------------------------------------------------------
 * Definitions for initial stack pointer and data area
 */

	/* Size in bytes reserved for initial data
	 */

#define CONFIG_SYS_INIT_RAM_ADDR     0x40000000
#define CONFIG_SYS_INIT_RAM_SIZE      0x1000
#define CONFIG_SYS_GBL_DATA_OFFSET  (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)

/*
 * NS16550 Configuration
 */
#define CONFIG_SYS_NS16550
#define CONFIG_SYS_NS16550_SERIAL

#define CONFIG_SYS_NS16550_REG_SIZE	1

#define CONFIG_SYS_NS16550_CLK		3686400

#define CONFIG_SYS_NS16550_COM1	0xFFF80000

/*
 * Low Level Configuration Settings
 * (address mappings, register initial values, etc.)
 * You should know what you are doing if you make changes here.
 * For the detail description refer to the MPC8240 user's manual.
 */

#define CONFIG_SYS_CLK_FREQ  33000000
#define CONFIG_SYS_HZ		     1000
#define CONFIG_PLL_PCI_TO_MEM_MULTIPLIER 3

	/* Bit-field values for MCCR1.
	 */
#define CONFIG_SYS_ROMNAL	    0
#define CONFIG_SYS_ROMFAL	    7

	/* Bit-field values for MCCR2.
	 */
#define CONFIG_SYS_REFINT	    430	    /* Refresh interval			*/

	/* Burst To Precharge. Bits of this value go to MCCR3 and MCCR4.
	 */
#define CONFIG_SYS_BSTOPRE	    192

	/* Bit-field values for MCCR3.
	 */
#define CONFIG_SYS_REFREC	    2	    /* Refresh to activate interval	*/
#define CONFIG_SYS_RDLAT	    3	    /* Data latancy from read command	*/

	/* Bit-field values for MCCR4.
	 */
#define CONFIG_SYS_PRETOACT	    2	    /* Precharge to activate interval	*/
#define CONFIG_SYS_ACTTOPRE	    5	    /* Activate to Precharge interval	*/
#define CONFIG_SYS_SDMODE_CAS_LAT  2	    /* SDMODE CAS latancy		*/
#define CONFIG_SYS_SDMODE_WRAP	    0	    /* SDMODE wrap type			*/
#define CONFIG_SYS_SDMODE_BURSTLEN 2	    /* SDMODE Burst length		*/
#define CONFIG_SYS_ACTORW	    2
#define CONFIG_SYS_REGISTERD_TYPE_BUFFER 1

/* Memory bank settings.
 * Only bits 20-29 are actually used from these vales to set the
 * start/end addresses. The upper two bits will always be 0, and the lower
 * 20 bits will be 0x00000 for a start address, or 0xfffff for an end
 * address. Refer to the MPC8240 book.
 */

#define CONFIG_SYS_BANK0_START	    0x00000000
#define CONFIG_SYS_BANK0_END	    (CONFIG_SYS_MAX_RAM_SIZE - 1)
#define CONFIG_SYS_BANK0_ENABLE    1
#define CONFIG_SYS_BANK1_START	    0x3ff00000
#define CONFIG_SYS_BANK1_END	    0x3fffffff
#define CONFIG_SYS_BANK1_ENABLE    0
#define CONFIG_SYS_BANK2_START	    0x3ff00000
#define CONFIG_SYS_BANK2_END	    0x3fffffff
#define CONFIG_SYS_BANK2_ENABLE    0
#define CONFIG_SYS_BANK3_START	    0x3ff00000
#define CONFIG_SYS_BANK3_END	    0x3fffffff
#define CONFIG_SYS_BANK3_ENABLE    0
#define CONFIG_SYS_BANK4_START	    0x3ff00000
#define CONFIG_SYS_BANK4_END	    0x3fffffff
#define CONFIG_SYS_BANK4_ENABLE    0
#define CONFIG_SYS_BANK5_START	    0x3ff00000
#define CONFIG_SYS_BANK5_END	    0x3fffffff
#define CONFIG_SYS_BANK5_ENABLE    0
#define CONFIG_SYS_BANK6_START	    0x3ff00000
#define CONFIG_SYS_BANK6_END	    0x3fffffff
#define CONFIG_SYS_BANK6_ENABLE    0
#define CONFIG_SYS_BANK7_START	    0x3ff00000
#define CONFIG_SYS_BANK7_END	    0x3fffffff
#define CONFIG_SYS_BANK7_ENABLE    0

#define CONFIG_SYS_ODCR	    0xff

#define CONFIG_SYS_IBAT0L  (CONFIG_SYS_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
#define CONFIG_SYS_IBAT0U  (CONFIG_SYS_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)

#define CONFIG_SYS_IBAT1L  (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_10 | BATL_MEMCOHERENCE)
#define CONFIG_SYS_IBAT1U  (CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP)

#define CONFIG_SYS_IBAT2L  (0x80000000 | BATL_PP_10 | BATL_CACHEINHIBIT)
#define CONFIG_SYS_IBAT2U  (0x80000000 | BATU_BL_256M | BATU_VS | BATU_VP)

#define CONFIG_SYS_IBAT3L  (0xFC000000 | BATL_PP_10 | BATL_CACHEINHIBIT)
#define CONFIG_SYS_IBAT3U  (0xFC000000 | BATU_BL_64M | BATU_VS | BATU_VP)

#define CONFIG_SYS_DBAT0L  CONFIG_SYS_IBAT0L
#define CONFIG_SYS_DBAT0U  CONFIG_SYS_IBAT0U
#define CONFIG_SYS_DBAT1L  CONFIG_SYS_IBAT1L
#define CONFIG_SYS_DBAT1U  CONFIG_SYS_IBAT1U
#define CONFIG_SYS_DBAT2L  CONFIG_SYS_IBAT2L
#define CONFIG_SYS_DBAT2U  CONFIG_SYS_IBAT2U
#define CONFIG_SYS_DBAT3L  CONFIG_SYS_IBAT3L
#define CONFIG_SYS_DBAT3U  CONFIG_SYS_IBAT3U

/*
 * For booting Linux, the board info and command line data
 * have to be in the first 8 MB of memory, since this is
 * the maximum mapped by the Linux kernel during initialization.
 */
#define CONFIG_SYS_BOOTMAPSZ	    (8 << 20)	/* Initial Memory map for Linux */

/*-----------------------------------------------------------------------
 * FLASH organization
 */
#define CONFIG_SYS_MAX_FLASH_BANKS	1	/* Max number of flash banks		*/
#define CONFIG_SYS_MAX_FLASH_SECT	256	/* Max number of sectors in one bank	*/

#define CONFIG_SYS_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)	*/

/*
 * Init Memory Controller:
 *
 * BR0/1 and OR0/1 (FLASH)
 */

#define FLASH_BASE0_PRELIM      CONFIG_SYS_FLASH_BASE  /* FLASH bank #0        */
#define FLASH_BASE1_PRELIM      0               /* FLASH bank #1        */

	/* Warining: environment is not EMBEDDED in the U-Boot code.
	 * It's stored in flash separately.
	 */
#define CONFIG_ENV_IS_IN_FLASH	1
#define CONFIG_ENV_ADDR		0xFFF70000
#define CONFIG_ENV_SIZE		0x4000	/* Size of the Environment		*/
#define CONFIG_ENV_OFFSET		0	/* starting right at the beginning	*/
#define CONFIG_ENV_SECT_SIZE	0x40000 /* Size of the Environment Sector	*/

/*-----------------------------------------------------------------------
 * Cache Configuration
 */
#define CONFIG_SYS_CACHELINE_SIZE	32
#if defined(CONFIG_CMD_KGDB)
#  define CONFIG_SYS_CACHELINE_SHIFT	5	/* log base 2 of the above value	*/
#endif

/*-----------------------------------------------------------------------
 * PCI stuff
 *-----------------------------------------------------------------------
 */
#define CONFIG_PCI			/* include pci support			*/
#define CONFIG_PCI_PNP                  /* we need Plug 'n Play */
#define CONFIG_NET_MULTI		/* Multi ethernet cards support */
#define CONFIG_TULIP
#define CONFIG_EEPRO100
#define CONFIG_SYS_RX_ETH_BUFFER	8       /* use 8 rx buffer on eepro100  */
#endif /* __CONFIG_H */
Commit	Line	Data
466b7410 WD	1	/*
	2	* (C) Copyright 2001
	3	* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
	4	*
	5	* See file CREDITS for list of people who contributed to this
	6	* project.
	7	*
	8	* This program is free software; you can redistribute it and/or
	9	* modify it under the terms of the GNU General Public License as
	10	* published by the Free Software Foundation; either version 2 of
	11	* the License, or (at your option) any later version.
	12	*
	13	* This program is distributed in the hope that it will be useful,
	14	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	15	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	16	* GNU General Public License for more details.
	17	*
	18	* You should have received a copy of the GNU General Public License
	19	* along with this program; if not, write to the Free Software
	20	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	21	* MA 02111-1307 USA
	22	*/
	23
	24	/*
	25	* Configuration settings for the sbc8240 board.
	26	*/
	27
	28	/* ------------------------------------------------------------------------- */
	29
	30	/*
	31	* board/config.h - configuration options, board specific
	32	*/
	33
	34	#ifndef __CONFIG_H
	35	#define __CONFIG_H
	36
	37	/*
	38	* High Level Configuration Options
	39	* (easy to change)
	40	*/
	41
	42	#define CONFIG_MPC824X 1
	43	#define CONFIG_MPC8240 1
	44	#define CONFIG_WRSBC8240 1
	45
2ae18241 WD	46	#define CONFIG_SYS_TEXT_BASE 0xFFF00000
2ae18241 WD	47
466b7410 WD	48	#define CONFIG_CONS_INDEX 1
466b7410 WD	49	#define CONFIG_BAUDRATE 9600
6d0f6bcf	50	#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
466b7410 WD	51
	52	#define CONFIG_PREBOOT "echo;echo Welcome to U-Boot for the sbc8240;echo;echo Type \"? or help\" to get on-line help;echo"
	53
	54	#undef CONFIG_BOOTARGS
	55
	56	#define CONFIG_BOOTCOMMAND "version;echo;tftpboot $loadaddr $loadfile;bootvx" /* autoboot command */
	57
	58	#define CONFIG_EXTRA_ENV_SETTINGS \
	59	"bootargs=$fei(0,0)host:/T221ppc/target/config/sbc8240/vxWorks.st " \
	60	"e=192.168.193.102 h=192.168.193.99 u=target pw=hello f=0x08 " \
	61	"tn=sbc8240 o=fei \0" \
	62	"env_startaddr=FFF70000\0" \
	63	"env_endaddr=FFF7FFFF\0" \
	64	"loadfile=vxWorks.st\0" \
	65	"loadaddr=0x01000000\0" \
	66	"net_load=tftpboot $loadaddr $loadfile\0" \
	67	"uboot_startaddr=FFF00000\0" \
	68	"uboot_endaddr=FFF3FFFF\0" \
	69	"update=tftp $loadaddr /u-boot.bin;" \
	70	"protect off $uboot_startaddr $uboot_endaddr;" \
	71	"era $uboot_startaddr $uboot_endaddr;" \
	72	"cp.b $loadaddr $uboot_startaddr $filesize;" \
	73	"protect on $uboot_startaddr $uboot_endaddr\0" \
	74	"zapenv=protect off $env_startaddr $env_endaddr;" \
	75	"era $env_startaddr $env_endaddr;" \
	76	"protect on $env_startaddr $env_endaddr\0"
	77
	78	#define CONFIG_BOOTDELAY 5
	79
d3b8c1a7 JL	80	/*
	81	* BOOTP options
	82	*/
	83	#define CONFIG_BOOTP_SUBNETMASK
	84	#define CONFIG_BOOTP_GATEWAY
	85	#define CONFIG_BOOTP_HOSTNAME
	86	#define CONFIG_BOOTP_BOOTPATH
	87	#define CONFIG_BOOTP_BOOTFILESIZE
	88
466b7410 WD	89
	90	#define CONFIG_ENV_OVERWRITE
	91
866e3089 JL	92
	93	/*
	94	* Command line configuration.
466b7410	95	*/
866e3089 JL	96	#include <config_cmd_default.h>
	97
	98	#define CONFIG_CMD_BSP
	99	#define CONFIG_CMD_DIAG
	100	#define CONFIG_CMD_ELF
bdab39d3	101	#define CONFIG_CMD_SAVEENV
866e3089 JL	102	#define CONFIG_CMD_FLASH
	103	#define CONFIG_CMD_PCI
	104	#define CONFIG_CMD_PING
	105	#define CONFIG_CMD_SDRAM
	106
466b7410 WD	107
	108	/*
	109	* Miscellaneous configurable options
	110	*/
6d0f6bcf JCPV	111	#define CONFIG_SYS_LONGHELP /* undef to save memory */
	112	#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
	113	#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
466b7410 WD	114
466b7410 WD	115	#if 1
6d0f6bcf	116	#define CONFIG_SYS_HUSH_PARSER 1 /* use "hush" command parser */
466b7410	117	#endif
6d0f6bcf JCPV	118	#ifdef CONFIG_SYS_HUSH_PARSER
6d0f6bcf JCPV	119	#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
466b7410 WD	120	#endif
	121
	122	#define CONFIG_ETHADDR DE:AD:BE:EF:01:01 /* Ethernet address */
	123	#define CONFIG_IPADDR 192.168.193.102
	124	#define CONFIG_NETMASK 255.255.255.248
	125	#define CONFIG_SERVERIP 192.168.193.99
	126
	127	#define CONFIG_STATUS_LED /* Status LED enabled */
	128	#define CONFIG_BOARD_SPECIFIC_LED /* version has board specific leds */
	129
	130	#define STATUS_LED_BIT 0x00000001
6d0f6bcf	131	#define STATUS_LED_PERIOD (CONFIG_SYS_HZ / 2)
466b7410 WD	132	#define STATUS_LED_STATE STATUS_LED_BLINKING
	133	#define STATUS_LED_ACTIVE 0 /* LED on for bit == 0 */
	134	#define STATUS_LED_BOOT 0 /* LED 0 used for boot status */
	135
	136	#ifndef __ASSEMBLY__
	137	/* LEDs */
	138	typedef unsigned int led_id_t;
	139
	140	#define __led_toggle(_msk) \
	141	do { \
6d0f6bcf	142	((volatile char ) (CONFIG_SYS_LED_BASE)) ^= (_msk); \
466b7410 WD	143	} while(0)
	144
	145	#define __led_set(_msk, _st) \
	146	do { \
	147	if ((_st)) \
6d0f6bcf	148	((volatile char ) (CONFIG_SYS_LED_BASE)) \|= (_msk); \
466b7410	149	else \
6d0f6bcf	150	((volatile char ) (CONFIG_SYS_LED_BASE)) &= ~(_msk); \
466b7410 WD	151	} while(0)
	152
	153	#define __led_init(msk, st) __led_set(msk, st)
	154
	155	#endif
	156
	157	#define CONFIG_MISC_INIT_R
6d0f6bcf	158	#define CONFIG_SYS_LED_BASE 0xFFE80000
466b7410 WD	159
	160	/* Print Buffer Size
	161	*/
6d0f6bcf	162	#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
466b7410	163
6d0f6bcf JCPV	164	#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
	165	#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
	166	#define CONFIG_SYS_LOAD_ADDR 0x00100000 /* Default load address */
466b7410 WD	167
	168	/*-----------------------------------------------------------------------
	169	* Start addresses for the final memory configuration
	170	* (Set up by the startup code)
6d0f6bcf	171	* Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
466b7410	172	*/
6d0f6bcf JCPV	173	#define CONFIG_SYS_SDRAM_BASE 0x00000000
6d0f6bcf JCPV	174	#define CONFIG_SYS_FLASH_BASE 0xFFF00000
466b7410	175
6d0f6bcf	176	#define CONFIG_SYS_RESET_ADDRESS 0xFFF00100
466b7410	177
6d0f6bcf	178	#define CONFIG_SYS_EUMB_ADDR 0xFCE00000
466b7410	179
14d0a02a	180	#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
466b7410	181
6d0f6bcf JCPV	182	#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
6d0f6bcf JCPV	183	#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
466b7410	184
6d0f6bcf JCPV	185	#define CONFIG_SYS_MEMTEST_START 0x00004000 /* memtest works on */
6d0f6bcf JCPV	186	#define CONFIG_SYS_MEMTEST_END 0x02000000 /* 0 ... 32 MB in DRAM */
466b7410 WD	187
	188	/* Maximum amount of RAM.
	189	*/
6d0f6bcf	190	#define CONFIG_SYS_MAX_RAM_SIZE 0x10000000
466b7410	191
6d0f6bcf JCPV	192	#if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE
6d0f6bcf JCPV	193	#undef CONFIG_SYS_RAMBOOT
466b7410	194	#else
6d0f6bcf	195	#define CONFIG_SYS_RAMBOOT
466b7410 WD	196	#endif
	197
	198	/*-----------------------------------------------------------------------
	199	* Definitions for initial stack pointer and data area
	200	*/
	201
	202	/* Size in bytes reserved for initial data
	203	*/
466b7410	204
6d0f6bcf	205	#define CONFIG_SYS_INIT_RAM_ADDR 0x40000000
553f0982	206	#define CONFIG_SYS_INIT_RAM_SIZE 0x1000
25ddd1fb	207	#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
466b7410 WD	208
	209	/*
	210	* NS16550 Configuration
	211	*/
6d0f6bcf JCPV	212	#define CONFIG_SYS_NS16550
6d0f6bcf JCPV	213	#define CONFIG_SYS_NS16550_SERIAL
466b7410	214
6d0f6bcf	215	#define CONFIG_SYS_NS16550_REG_SIZE 1
466b7410	216
6d0f6bcf	217	#define CONFIG_SYS_NS16550_CLK 3686400
466b7410	218
6d0f6bcf	219	#define CONFIG_SYS_NS16550_COM1 0xFFF80000
466b7410 WD	220
	221	/*
	222	* Low Level Configuration Settings
	223	* (address mappings, register initial values, etc.)
	224	* You should know what you are doing if you make changes here.
	225	* For the detail description refer to the MPC8240 user's manual.
	226	*/
	227
	228	#define CONFIG_SYS_CLK_FREQ 33000000
6d0f6bcf	229	#define CONFIG_SYS_HZ 1000
466b7410 WD	230	#define CONFIG_PLL_PCI_TO_MEM_MULTIPLIER 3
	231
	232	/* Bit-field values for MCCR1.
	233	*/
6d0f6bcf JCPV	234	#define CONFIG_SYS_ROMNAL 0
6d0f6bcf JCPV	235	#define CONFIG_SYS_ROMFAL 7
466b7410 WD	236
	237	/* Bit-field values for MCCR2.
	238	*/
6d0f6bcf	239	#define CONFIG_SYS_REFINT 430 /* Refresh interval */
466b7410 WD	240
	241	/* Burst To Precharge. Bits of this value go to MCCR3 and MCCR4.
	242	*/
6d0f6bcf	243	#define CONFIG_SYS_BSTOPRE 192
466b7410 WD	244
	245	/* Bit-field values for MCCR3.
	246	*/
6d0f6bcf JCPV	247	#define CONFIG_SYS_REFREC 2 /* Refresh to activate interval */
6d0f6bcf JCPV	248	#define CONFIG_SYS_RDLAT 3 /* Data latancy from read command */
466b7410 WD	249
	250	/* Bit-field values for MCCR4.
	251	*/
6d0f6bcf JCPV	252	#define CONFIG_SYS_PRETOACT 2 /* Precharge to activate interval */
	253	#define CONFIG_SYS_ACTTOPRE 5 /* Activate to Precharge interval */
	254	#define CONFIG_SYS_SDMODE_CAS_LAT 2 /* SDMODE CAS latancy */
	255	#define CONFIG_SYS_SDMODE_WRAP 0 /* SDMODE wrap type */
	256	#define CONFIG_SYS_SDMODE_BURSTLEN 2 /* SDMODE Burst length */
	257	#define CONFIG_SYS_ACTORW 2
	258	#define CONFIG_SYS_REGISTERD_TYPE_BUFFER 1
466b7410 WD	259
	260	/* Memory bank settings.
	261	* Only bits 20-29 are actually used from these vales to set the
	262	* start/end addresses. The upper two bits will always be 0, and the lower
	263	* 20 bits will be 0x00000 for a start address, or 0xfffff for an end
	264	* address. Refer to the MPC8240 book.
	265	*/
	266
6d0f6bcf JCPV	267	#define CONFIG_SYS_BANK0_START 0x00000000
	268	#define CONFIG_SYS_BANK0_END (CONFIG_SYS_MAX_RAM_SIZE - 1)
	269	#define CONFIG_SYS_BANK0_ENABLE 1
	270	#define CONFIG_SYS_BANK1_START 0x3ff00000
	271	#define CONFIG_SYS_BANK1_END 0x3fffffff
	272	#define CONFIG_SYS_BANK1_ENABLE 0
	273	#define CONFIG_SYS_BANK2_START 0x3ff00000
	274	#define CONFIG_SYS_BANK2_END 0x3fffffff
	275	#define CONFIG_SYS_BANK2_ENABLE 0
	276	#define CONFIG_SYS_BANK3_START 0x3ff00000
	277	#define CONFIG_SYS_BANK3_END 0x3fffffff
	278	#define CONFIG_SYS_BANK3_ENABLE 0
	279	#define CONFIG_SYS_BANK4_START 0x3ff00000
	280	#define CONFIG_SYS_BANK4_END 0x3fffffff
	281	#define CONFIG_SYS_BANK4_ENABLE 0
	282	#define CONFIG_SYS_BANK5_START 0x3ff00000
	283	#define CONFIG_SYS_BANK5_END 0x3fffffff
	284	#define CONFIG_SYS_BANK5_ENABLE 0
	285	#define CONFIG_SYS_BANK6_START 0x3ff00000
	286	#define CONFIG_SYS_BANK6_END 0x3fffffff
	287	#define CONFIG_SYS_BANK6_ENABLE 0
	288	#define CONFIG_SYS_BANK7_START 0x3ff00000
	289	#define CONFIG_SYS_BANK7_END 0x3fffffff
	290	#define CONFIG_SYS_BANK7_ENABLE 0
	291
	292	#define CONFIG_SYS_ODCR 0xff
	293
	294	#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE \| BATL_PP_10 \| BATL_MEMCOHERENCE)
	295	#define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE \| BATU_BL_256M \| BATU_VS \| BATU_VP)
	296
	297	#define CONFIG_SYS_IBAT1L (CONFIG_SYS_INIT_RAM_ADDR \| BATL_PP_10 \| BATL_MEMCOHERENCE)
	298	#define CONFIG_SYS_IBAT1U (CONFIG_SYS_INIT_RAM_ADDR \| BATU_BL_128K \| BATU_VS \| BATU_VP)
	299
	300	#define CONFIG_SYS_IBAT2L (0x80000000 \| BATL_PP_10 \| BATL_CACHEINHIBIT)
	301	#define CONFIG_SYS_IBAT2U (0x80000000 \| BATU_BL_256M \| BATU_VS \| BATU_VP)
	302
	303	#define CONFIG_SYS_IBAT3L (0xFC000000 \| BATL_PP_10 \| BATL_CACHEINHIBIT)
	304	#define CONFIG_SYS_IBAT3U (0xFC000000 \| BATU_BL_64M \| BATU_VS \| BATU_VP)
	305
	306	#define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L
	307	#define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U
	308	#define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L
	309	#define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U
	310	#define CONFIG_SYS_DBAT2L CONFIG_SYS_IBAT2L
	311	#define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U
	312	#define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L
	313	#define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U
466b7410 WD	314
	315	/*
	316	* For booting Linux, the board info and command line data
	317	* have to be in the first 8 MB of memory, since this is
	318	* the maximum mapped by the Linux kernel during initialization.
	319	*/
6d0f6bcf	320	#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
466b7410 WD	321
	322	/*-----------------------------------------------------------------------
	323	* FLASH organization
	324	*/
6d0f6bcf JCPV	325	#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* Max number of flash banks */
6d0f6bcf JCPV	326	#define CONFIG_SYS_MAX_FLASH_SECT 256 /* Max number of sectors in one bank */
466b7410	327
6d0f6bcf JCPV	328	#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
6d0f6bcf JCPV	329	#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
466b7410 WD	330
	331	/*
	332	* Init Memory Controller:
	333	*
	334	* BR0/1 and OR0/1 (FLASH)
	335	*/
	336
6d0f6bcf	337	#define FLASH_BASE0_PRELIM CONFIG_SYS_FLASH_BASE /* FLASH bank #0 */
466b7410 WD	338	#define FLASH_BASE1_PRELIM 0 /* FLASH bank #1 */
	339
	340	/* Warining: environment is not EMBEDDED in the U-Boot code.
	341	* It's stored in flash separately.
	342	*/
5a1aceb0	343	#define CONFIG_ENV_IS_IN_FLASH 1
0e8d1586 JCPV	344	#define CONFIG_ENV_ADDR 0xFFF70000
	345	#define CONFIG_ENV_SIZE 0x4000 /* Size of the Environment */
	346	#define CONFIG_ENV_OFFSET 0 /* starting right at the beginning */
	347	#define CONFIG_ENV_SECT_SIZE 0x40000 /* Size of the Environment Sector */
466b7410 WD	348
	349	/*-----------------------------------------------------------------------
	350	* Cache Configuration
	351	*/
6d0f6bcf	352	#define CONFIG_SYS_CACHELINE_SIZE 32
866e3089	353	#if defined(CONFIG_CMD_KGDB)
6d0f6bcf	354	# define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */
466b7410 WD	355	#endif
466b7410 WD	356
466b7410 WD	357	/*-----------------------------------------------------------------------
	358	* PCI stuff
	359	*-----------------------------------------------------------------------
	360	*/
	361	#define CONFIG_PCI /* include pci support */
	362	#define CONFIG_PCI_PNP /* we need Plug 'n Play */
	363	#define CONFIG_NET_MULTI /* Multi ethernet cards support */
	364	#define CONFIG_TULIP
	365	#define CONFIG_EEPRO100
6d0f6bcf	366	#define CONFIG_SYS_RX_ETH_BUFFER 8 /* use 8 rx buffer on eepro100 */
466b7410	367	#endif /* __CONFIG_H */