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fe8c2806 | 1 | /* |
10a36a98 WD |
2 | * (C) Copyright 2000 |
3 | * Murray Jensen <Murray.Jensen@cmst.csiro.au> | |
fe8c2806 | 4 | * |
10a36a98 WD |
5 | * (C) Copyright 2000 |
6 | * Sysgo Real-Time Solutions, GmbH <www.elinos.com> | |
7 | * Marius Groeger <mgroeger@sysgo.de> | |
8 | * | |
9 | * (C) Copyright 2001 | |
10 | * Advent Networks, Inc. <http://www.adventnetworks.com> | |
11 | * Jay Monkman <jtm@smoothsmoothie.com> | |
12 | * | |
13 | * Configuration settings for the WindRiver SBC8260 board. | |
14 | * See http://www.windriver.com/products/html/sbc8260.html | |
fe8c2806 WD |
15 | * |
16 | * See file CREDITS for list of people who contributed to this | |
17 | * project. | |
18 | * | |
19 | * This program is free software; you can redistribute it and/or | |
20 | * modify it under the terms of the GNU General Public License as | |
21 | * published by the Free Software Foundation; either version 2 of | |
22 | * the License, or (at your option) any later version. | |
23 | * | |
24 | * This program is distributed in the hope that it will be useful, | |
25 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
26 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
27 | * GNU General Public License for more details. | |
28 | * | |
29 | * You should have received a copy of the GNU General Public License | |
30 | * along with this program; if not, write to the Free Software | |
31 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | |
32 | * MA 02111-1307 USA | |
33 | */ | |
34 | ||
35 | #ifndef __CONFIG_H | |
36 | #define __CONFIG_H | |
37 | ||
2ae18241 WD |
38 | #define CONFIG_SYS_TEXT_BASE 0x40000000 |
39 | ||
10a36a98 | 40 | /* Enable debug prints */ |
10a36a98 | 41 | #undef DEBUG_BOOTP_EXT /* Debug received vendor fields */ |
fe8c2806 | 42 | |
10a36a98 WD |
43 | /***************************************************************************** |
44 | * | |
45 | * These settings must match the way _your_ board is set up | |
46 | * | |
47 | *****************************************************************************/ | |
fe8c2806 | 48 | |
10a36a98 WD |
49 | /* What is the oscillator's (UX2) frequency in Hz? */ |
50 | #define CONFIG_8260_CLKIN (66 * 1000 * 1000) | |
51 | ||
52 | /*----------------------------------------------------------------------- | |
53 | * MODCK_H & MODCLK[1-3] - Ref: Section 9.2 in MPC8206 User Manual | |
54 | *----------------------------------------------------------------------- | |
55 | * What should MODCK_H be? It is dependent on the oscillator | |
56 | * frequency, MODCK[1-3], and desired CPM and core frequencies. | |
57 | * Here are some example values (all frequencies are in MHz): | |
58 | * | |
59 | * MODCK_H MODCK[1-3] Osc CPM Core S2-6 S2-7 S2-8 | |
60 | * ------- ---------- --- --- ---- ----- ----- ----- | |
61 | * 0x1 0x5 33 100 133 Open Close Open | |
62 | * 0x1 0x6 33 100 166 Open Open Close | |
63 | * 0x1 0x7 33 100 200 Open Open Open | |
64 | * | |
65 | * 0x2 0x2 33 133 133 Close Open Close | |
66 | * 0x2 0x3 33 133 166 Close Open Open | |
67 | * 0x2 0x4 33 133 200 Open Close Close | |
68 | * 0x2 0x5 33 133 233 Open Close Open | |
69 | * 0x2 0x6 33 133 266 Open Open Close | |
70 | * | |
71 | * 0x5 0x5 66 133 133 Open Close Open | |
72 | * 0x5 0x6 66 133 166 Open Open Close | |
73 | * 0x5 0x7 66 133 200 Open Open Open | |
74 | * 0x6 0x0 66 133 233 Close Close Close | |
75 | * 0x6 0x1 66 133 266 Close Close Open | |
76 | * 0x6 0x2 66 133 300 Close Open Close | |
77 | */ | |
6d0f6bcf | 78 | #define CONFIG_SYS_SBC_MODCK_H 0x05 |
fe8c2806 | 79 | |
10a36a98 WD |
80 | /* Define this if you want to boot from 0x00000100. If you don't define |
81 | * this, you will need to program the bootloader to 0xfff00000, and | |
82 | * get the hardware reset config words at 0xfe000000. The simplest | |
83 | * way to do that is to program the bootloader at both addresses. | |
84 | * It is suggested that you just let U-Boot live at 0x00000000. | |
85 | */ | |
6d0f6bcf | 86 | #define CONFIG_SYS_SBC_BOOT_LOW 1 |
fe8c2806 | 87 | |
10a36a98 | 88 | /* What should the base address of the main FLASH be and how big is |
14d0a02a | 89 | * it (in MBytes)? This must contain CONFIG_SYS_TEXT_BASE from board/sbc8260/config.mk |
10a36a98 WD |
90 | * The main FLASH is whichever is connected to *CS0. U-Boot expects |
91 | * this to be the SIMM. | |
92 | */ | |
6d0f6bcf JCPV |
93 | #define CONFIG_SYS_FLASH0_BASE 0x40000000 |
94 | #define CONFIG_SYS_FLASH0_SIZE 4 | |
fe8c2806 | 95 | |
10a36a98 WD |
96 | /* What should the base address of the secondary FLASH be and how big |
97 | * is it (in Mbytes)? The secondary FLASH is whichever is connected | |
98 | * to *CS6. U-Boot expects this to be the on board FLASH. If you don't | |
99 | * want it enabled, don't define these constants. | |
100 | */ | |
6d0f6bcf JCPV |
101 | #define CONFIG_SYS_FLASH1_BASE 0x60000000 |
102 | #define CONFIG_SYS_FLASH1_SIZE 2 | |
fe8c2806 | 103 | |
10a36a98 WD |
104 | /* What should be the base address of SDRAM DIMM and how big is |
105 | * it (in Mbytes)? | |
106 | */ | |
6d0f6bcf JCPV |
107 | #define CONFIG_SYS_SDRAM0_BASE 0x00000000 |
108 | #define CONFIG_SYS_SDRAM0_SIZE 64 | |
fe8c2806 | 109 | |
10a36a98 WD |
110 | /* What should be the base address of the LEDs and switch S0? |
111 | * If you don't want them enabled, don't define this. | |
fe8c2806 | 112 | */ |
6d0f6bcf | 113 | #define CONFIG_SYS_LED_BASE 0xa0000000 |
fe8c2806 WD |
114 | |
115 | ||
10a36a98 WD |
116 | /* |
117 | * SBC8260 with 16 MB DIMM: | |
118 | * | |
119 | * 0x0000 0000 Exception Vector code, 8k | |
120 | * : | |
121 | * 0x0000 1FFF | |
122 | * 0x0000 2000 Free for Application Use | |
123 | * : | |
124 | * : | |
125 | * | |
126 | * : | |
127 | * : | |
128 | * 0x00F5 FF30 Monitor Stack (Growing downward) | |
129 | * Monitor Stack Buffer (0x80) | |
130 | * 0x00F5 FFB0 Board Info Data | |
131 | * 0x00F6 0000 Malloc Arena | |
0e8d1586 | 132 | * : CONFIG_ENV_SECT_SIZE, 256k |
6d0f6bcf | 133 | * : CONFIG_SYS_MALLOC_LEN, 128k |
10a36a98 | 134 | * 0x00FC 0000 RAM Copy of Monitor Code |
6d0f6bcf JCPV |
135 | * : CONFIG_SYS_MONITOR_LEN, 256k |
136 | * 0x00FF FFFF [End of RAM], CONFIG_SYS_SDRAM_SIZE - 1 | |
10a36a98 | 137 | */ |
fe8c2806 | 138 | |
10a36a98 WD |
139 | /* |
140 | * SBC8260 with 64 MB DIMM: | |
141 | * | |
142 | * 0x0000 0000 Exception Vector code, 8k | |
143 | * : | |
144 | * 0x0000 1FFF | |
145 | * 0x0000 2000 Free for Application Use | |
146 | * : | |
147 | * : | |
148 | * | |
149 | * : | |
150 | * : | |
151 | * 0x03F5 FF30 Monitor Stack (Growing downward) | |
152 | * Monitor Stack Buffer (0x80) | |
153 | * 0x03F5 FFB0 Board Info Data | |
154 | * 0x03F6 0000 Malloc Arena | |
0e8d1586 | 155 | * : CONFIG_ENV_SECT_SIZE, 256k |
6d0f6bcf | 156 | * : CONFIG_SYS_MALLOC_LEN, 128k |
10a36a98 | 157 | * 0x03FC 0000 RAM Copy of Monitor Code |
6d0f6bcf JCPV |
158 | * : CONFIG_SYS_MONITOR_LEN, 256k |
159 | * 0x03FF FFFF [End of RAM], CONFIG_SYS_SDRAM_SIZE - 1 | |
10a36a98 | 160 | */ |
fe8c2806 WD |
161 | |
162 | ||
10a36a98 WD |
163 | /* |
164 | * select serial console configuration | |
165 | * | |
166 | * if either CONFIG_CONS_ON_SMC or CONFIG_CONS_ON_SCC is selected, then | |
167 | * CONFIG_CONS_INDEX must be set to the channel number (1-2 for SMC, 1-4 | |
168 | * for SCC). | |
169 | * | |
170 | * if CONFIG_CONS_NONE is defined, then the serial console routines must | |
171 | * defined elsewhere. | |
172 | */ | |
173 | #define CONFIG_CONS_ON_SMC 1 /* define if console on SMC */ | |
174 | #undef CONFIG_CONS_ON_SCC /* define if console on SCC */ | |
175 | #undef CONFIG_CONS_NONE /* define if console on neither */ | |
176 | #define CONFIG_CONS_INDEX 1 /* which SMC/SCC channel for console */ | |
fe8c2806 WD |
177 | |
178 | /* | |
10a36a98 WD |
179 | * select ethernet configuration |
180 | * | |
181 | * if either CONFIG_ETHER_ON_SCC or CONFIG_ETHER_ON_FCC is selected, then | |
182 | * CONFIG_ETHER_INDEX must be set to the channel number (1-4 for SCC, 1-3 | |
183 | * for FCC) | |
184 | * | |
185 | * if CONFIG_ETHER_NONE is defined, then either the ethernet routines must be | |
639221c7 | 186 | * defined elsewhere (as for the console), or CONFIG_CMD_NET must be unset. |
fe8c2806 WD |
187 | */ |
188 | ||
10a36a98 WD |
189 | #undef CONFIG_ETHER_ON_SCC |
190 | #define CONFIG_ETHER_ON_FCC | |
191 | #undef CONFIG_ETHER_NONE /* define if ethernet on neither */ | |
fe8c2806 | 192 | |
10a36a98 WD |
193 | #ifdef CONFIG_ETHER_ON_SCC |
194 | #define CONFIG_ETHER_INDEX 1 /* which SCC/FCC channel for ethernet */ | |
195 | #endif /* CONFIG_ETHER_ON_SCC */ | |
fe8c2806 | 196 | |
10a36a98 WD |
197 | #ifdef CONFIG_ETHER_ON_FCC |
198 | #define CONFIG_ETHER_INDEX 2 /* which SCC/FCC channel for ethernet */ | |
199 | #undef CONFIG_ETHER_LOOPBACK_TEST /* Ethernet external loopback test */ | |
200 | #define CONFIG_MII /* MII PHY management */ | |
201 | #define CONFIG_BITBANGMII /* bit-bang MII PHY management */ | |
202 | /* | |
203 | * Port pins used for bit-banged MII communictions (if applicable). | |
204 | */ | |
205 | #define MDIO_PORT 2 /* Port C */ | |
be225442 LCM |
206 | #define MDIO_DECLARE volatile ioport_t *iop = ioport_addr ( \ |
207 | (immap_t *) CONFIG_SYS_IMMR, MDIO_PORT ) | |
208 | #define MDC_DECLARE MDIO_DECLARE | |
209 | ||
10a36a98 WD |
210 | #define MDIO_ACTIVE (iop->pdir |= 0x00400000) |
211 | #define MDIO_TRISTATE (iop->pdir &= ~0x00400000) | |
212 | #define MDIO_READ ((iop->pdat & 0x00400000) != 0) | |
fe8c2806 | 213 | |
10a36a98 WD |
214 | #define MDIO(bit) if(bit) iop->pdat |= 0x00400000; \ |
215 | else iop->pdat &= ~0x00400000 | |
fe8c2806 | 216 | |
10a36a98 WD |
217 | #define MDC(bit) if(bit) iop->pdat |= 0x00200000; \ |
218 | else iop->pdat &= ~0x00200000 | |
fe8c2806 | 219 | |
10a36a98 WD |
220 | #define MIIDELAY udelay(1) |
221 | #endif /* CONFIG_ETHER_ON_FCC */ | |
fe8c2806 | 222 | |
10a36a98 | 223 | #if defined(CONFIG_ETHER_ON_SCC) && (CONFIG_ETHER_INDEX == 1) |
fe8c2806 | 224 | |
10a36a98 WD |
225 | /* |
226 | * - RX clk is CLK11 | |
227 | * - TX clk is CLK12 | |
228 | */ | |
6d0f6bcf | 229 | # define CONFIG_SYS_CMXSCR_VALUE (CMXSCR_RS1CS_CLK11 | CMXSCR_TS1CS_CLK12) |
fe8c2806 | 230 | |
10a36a98 | 231 | #elif defined(CONFIG_ETHER_ON_FCC) && (CONFIG_ETHER_INDEX == 2) |
fe8c2806 | 232 | |
10a36a98 WD |
233 | /* |
234 | * - Rx-CLK is CLK13 | |
235 | * - Tx-CLK is CLK14 | |
236 | * - Select bus for bd/buffers (see 28-13) | |
237 | * - Enable Full Duplex in FSMR | |
238 | */ | |
6d0f6bcf JCPV |
239 | # define CONFIG_SYS_CMXFCR_MASK (CMXFCR_FC2|CMXFCR_RF2CS_MSK|CMXFCR_TF2CS_MSK) |
240 | # define CONFIG_SYS_CMXFCR_VALUE (CMXFCR_RF2CS_CLK13|CMXFCR_TF2CS_CLK14) | |
241 | # define CONFIG_SYS_CPMFCR_RAMTYPE 0 | |
242 | # define CONFIG_SYS_FCC_PSMR (FCC_PSMR_FDE | FCC_PSMR_LPB) | |
fe8c2806 | 243 | |
10a36a98 WD |
244 | #endif /* CONFIG_ETHER_ON_FCC, CONFIG_ETHER_INDEX */ |
245 | ||
246 | /* | |
247 | * Select SPI support configuration | |
248 | */ | |
249 | #undef CONFIG_SPI /* Disable SPI driver */ | |
fe8c2806 | 250 | |
10a36a98 WD |
251 | /* |
252 | * Select i2c support configuration | |
253 | * | |
254 | * Supported configurations are {none, software, hardware} drivers. | |
255 | * If the software driver is chosen, there are some additional | |
256 | * configuration items that the driver uses to drive the port pins. | |
257 | */ | |
258 | #undef CONFIG_HARD_I2C /* I2C with hardware support */ | |
259 | #define CONFIG_SOFT_I2C 1 /* I2C bit-banged */ | |
6d0f6bcf JCPV |
260 | #define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */ |
261 | #define CONFIG_SYS_I2C_SLAVE 0x7F | |
10a36a98 WD |
262 | |
263 | /* | |
264 | * Software (bit-bang) I2C driver configuration | |
265 | */ | |
266 | #ifdef CONFIG_SOFT_I2C | |
267 | #define I2C_PORT 3 /* Port A=0, B=1, C=2, D=3 */ | |
268 | #define I2C_ACTIVE (iop->pdir |= 0x00010000) | |
269 | #define I2C_TRISTATE (iop->pdir &= ~0x00010000) | |
270 | #define I2C_READ ((iop->pdat & 0x00010000) != 0) | |
271 | #define I2C_SDA(bit) if(bit) iop->pdat |= 0x00010000; \ | |
272 | else iop->pdat &= ~0x00010000 | |
273 | #define I2C_SCL(bit) if(bit) iop->pdat |= 0x00020000; \ | |
274 | else iop->pdat &= ~0x00020000 | |
275 | #define I2C_DELAY udelay(5) /* 1/4 I2C clock duration */ | |
276 | #endif /* CONFIG_SOFT_I2C */ | |
277 | ||
278 | ||
279 | /* Define this to reserve an entire FLASH sector (256 KB) for | |
280 | * environment variables. Otherwise, the environment will be | |
281 | * put in the same sector as U-Boot, and changing variables | |
282 | * will erase U-Boot temporarily | |
283 | */ | |
0e8d1586 | 284 | #define CONFIG_ENV_IN_OWN_SECT 1 |
fe8c2806 | 285 | |
10a36a98 WD |
286 | /* Define to allow the user to overwrite serial and ethaddr */ |
287 | #define CONFIG_ENV_OVERWRITE | |
fe8c2806 | 288 | |
10a36a98 | 289 | /* What should the console's baud rate be? */ |
fe8c2806 WD |
290 | #define CONFIG_BAUDRATE 9600 |
291 | ||
10a36a98 WD |
292 | /* Ethernet MAC address |
293 | * Note: We are using the EST Corporation OUI (00:a0:1e:xx:xx:xx) | |
294 | * http://standards.ieee.org/regauth/oui/index.shtml | |
295 | */ | |
296 | #define CONFIG_ETHADDR 00:a0:1e:a8:7b:cb | |
297 | ||
298 | /* | |
299 | * Define this to set the last octet of the ethernet address from the | |
300 | * DS0-DS7 switch and light the LEDs with the result. The DS0-DS7 | |
301 | * switch and the LEDs are backwards with respect to each other. DS7 | |
302 | * is on the board edge side of both the LED strip and the DS0-DS7 | |
303 | * switch. | |
304 | */ | |
305 | #undef CONFIG_MISC_INIT_R | |
fe8c2806 | 306 | |
10a36a98 WD |
307 | /* Set to a positive value to delay for running BOOTCOMMAND */ |
308 | #define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ | |
fe8c2806 | 309 | |
10a36a98 WD |
310 | /* Be selective on what keys can delay or stop the autoboot process |
311 | * To stop use: " " | |
312 | */ | |
313 | #undef CONFIG_AUTOBOOT_KEYED | |
314 | #ifdef CONFIG_AUTOBOOT_KEYED | |
f2302d44 SR |
315 | # define CONFIG_AUTOBOOT_PROMPT \ |
316 | "Autobooting in %d seconds, press \" \" to stop\n", bootdelay | |
10a36a98 WD |
317 | # define CONFIG_AUTOBOOT_STOP_STR " " |
318 | # undef CONFIG_AUTOBOOT_DELAY_STR | |
319 | # define DEBUG_BOOTKEYS 0 | |
fe8c2806 WD |
320 | #endif |
321 | ||
10a36a98 WD |
322 | /* Define this to contain any number of null terminated strings that |
323 | * will be part of the default enviroment compiled into the boot image. | |
324 | * | |
325 | * Variable Usage | |
326 | * -------------- ------------------------------------------------------- | |
327 | * serverip server IP address | |
328 | * ipaddr my IP address | |
329 | * reprog Reload flash with a new copy of U-Boot | |
330 | * zapenv Erase the environment area in flash | |
331 | * root-on-initrd Set the bootcmd variable to allow booting of an initial | |
332 | * ram disk. | |
333 | * root-on-nfs Set the bootcmd variable to allow booting of a NFS | |
334 | * mounted root filesystem. | |
335 | * boot-hook Convenient stub to do something useful before the | |
336 | * bootm command is executed. | |
337 | * | |
338 | * Example usage of root-on-initrd and root-on-nfs : | |
339 | * | |
340 | * Note: The lines have been wrapped to improved its readability. | |
341 | * | |
342 | * => printenv bootcmd | |
343 | * bootcmd=version;echo;bootp;setenv bootargs root=/dev/nfs rw | |
fe126d8b WD |
344 | * nfsroot=${serverip}:${rootpath} |
345 | * ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off;run boot-hook;bootm | |
10a36a98 WD |
346 | * |
347 | * => run root-on-initrd | |
348 | * => printenv bootcmd | |
349 | * bootcmd=version;echo;bootp;setenv bootargs root=/dev/ram0 rw | |
fe126d8b | 350 | * ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off;run boot-hook;bootm |
10a36a98 WD |
351 | * |
352 | * => run root-on-nfs | |
353 | * => printenv bootcmd | |
354 | * bootcmd=version;echo;bootp;setenv bootargs root=/dev/nfs rw | |
fe126d8b WD |
355 | * nfsroot=${serverip}:${rootpath} |
356 | * ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off;run boot-hook;bootm | |
10a36a98 WD |
357 | * |
358 | */ | |
359 | #define CONFIG_EXTRA_ENV_SETTINGS \ | |
b9283e2d | 360 | "serverip=192.168.123.205\0" \ |
10a36a98 WD |
361 | "ipaddr=192.168.123.213\0" \ |
362 | "reprog="\ | |
363 | "bootp;" \ | |
364 | "tftpboot 0x140000 /bdi2000/u-boot.bin;" \ | |
365 | "protect off 1:0;" \ | |
366 | "erase 1:0;" \ | |
fe126d8b | 367 | "cp.b 140000 40000000 ${filesize};" \ |
10a36a98 WD |
368 | "protect on 1:0\0" \ |
369 | "zapenv="\ | |
370 | "protect off 1:1;" \ | |
371 | "erase 1:1;" \ | |
372 | "protect on 1:1\0" \ | |
373 | "root-on-initrd="\ | |
374 | "setenv bootcmd "\ | |
375 | "version;" \ | |
376 | "echo;" \ | |
377 | "bootp;" \ | |
378 | "setenv bootargs root=/dev/ram0 rw " \ | |
fe126d8b | 379 | "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off;" \ |
10a36a98 WD |
380 | "run boot-hook;" \ |
381 | "bootm\0" \ | |
382 | "root-on-nfs="\ | |
383 | "setenv bootcmd "\ | |
384 | "version;" \ | |
385 | "echo;" \ | |
386 | "bootp;" \ | |
387 | "setenv bootargs root=/dev/nfs rw " \ | |
fe126d8b WD |
388 | "nfsroot=${serverip}:${rootpath} " \ |
389 | "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off;" \ | |
10a36a98 WD |
390 | "run boot-hook;" \ |
391 | "bootm\0" \ | |
392 | "boot-hook=echo\0" | |
393 | ||
394 | /* Define a command string that is automatically executed when no character | |
395 | * is read on the console interface withing "Boot Delay" after reset. | |
396 | */ | |
53677ef1 | 397 | #undef CONFIG_BOOT_ROOT_INITRD /* Use ram disk for the root file system */ |
10a36a98 WD |
398 | #define CONFIG_BOOT_ROOT_NFS /* Use a NFS mounted root file system */ |
399 | ||
400 | #ifdef CONFIG_BOOT_ROOT_INITRD | |
401 | #define CONFIG_BOOTCOMMAND \ | |
402 | "version;" \ | |
403 | "echo;" \ | |
404 | "bootp;" \ | |
405 | "setenv bootargs root=/dev/ram0 rw " \ | |
fe126d8b | 406 | "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off;" \ |
10a36a98 WD |
407 | "bootm" |
408 | #endif /* CONFIG_BOOT_ROOT_INITRD */ | |
409 | ||
410 | #ifdef CONFIG_BOOT_ROOT_NFS | |
411 | #define CONFIG_BOOTCOMMAND \ | |
412 | "version;" \ | |
413 | "echo;" \ | |
414 | "bootp;" \ | |
fe126d8b WD |
415 | "setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \ |
416 | "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off;" \ | |
10a36a98 WD |
417 | "bootm" |
418 | #endif /* CONFIG_BOOT_ROOT_NFS */ | |
419 | ||
d3b8c1a7 JL |
420 | /* |
421 | * BOOTP options | |
10a36a98 | 422 | */ |
d3b8c1a7 JL |
423 | #define CONFIG_BOOTP_SUBNETMASK |
424 | #define CONFIG_BOOTP_GATEWAY | |
425 | #define CONFIG_BOOTP_HOSTNAME | |
426 | #define CONFIG_BOOTP_BOOTPATH | |
427 | #define CONFIG_BOOTP_BOOTFILESIZE | |
428 | #define CONFIG_BOOTP_DNS | |
429 | #define CONFIG_BOOTP_DNS2 | |
430 | #define CONFIG_BOOTP_SEND_HOSTNAME | |
431 | ||
fe8c2806 | 432 | |
10a36a98 | 433 | /* undef this to save memory */ |
6d0f6bcf | 434 | #define CONFIG_SYS_LONGHELP |
fe8c2806 | 435 | |
10a36a98 | 436 | /* Monitor Command Prompt */ |
6d0f6bcf | 437 | #define CONFIG_SYS_PROMPT "=> " |
fe8c2806 | 438 | |
6d0f6bcf JCPV |
439 | #undef CONFIG_SYS_HUSH_PARSER |
440 | #ifdef CONFIG_SYS_HUSH_PARSER | |
441 | #define CONFIG_SYS_PROMPT_HUSH_PS2 "> " | |
1d0350ed WD |
442 | #endif |
443 | ||
10a36a98 WD |
444 | /* When CONFIG_TIMESTAMP is selected, the timestamp (date and time) |
445 | * of an image is printed by image commands like bootm or iminfo. | |
1d0350ed | 446 | */ |
10a36a98 | 447 | #define CONFIG_TIMESTAMP |
1d0350ed | 448 | |
10a36a98 WD |
449 | /* If this variable is defined, an environment variable named "ver" |
450 | * is created by U-Boot showing the U-Boot version. | |
451 | */ | |
452 | #define CONFIG_VERSION_VARIABLE | |
453 | ||
866e3089 JL |
454 | |
455 | /* | |
456 | * Command line configuration. | |
457 | */ | |
458 | #include <config_cmd_default.h> | |
459 | ||
460 | #define CONFIG_CMD_ASKENV | |
461 | #define CONFIG_CMD_ELF | |
462 | #define CONFIG_CMD_I2C | |
463 | #define CONFIG_CMD_IMMAP | |
464 | #define CONFIG_CMD_PING | |
465 | #define CONFIG_CMD_REGINFO | |
466 | #define CONFIG_CMD_SDRAM | |
467 | ||
468 | #undef CONFIG_CMD_KGDB | |
469 | ||
470 | #if defined(CONFIG_ETHER_ON_FCC) | |
471 | #define CONFIG_CMD_CMD_MII | |
472 | #endif | |
473 | ||
10a36a98 WD |
474 | |
475 | #undef CONFIG_WATCHDOG /* disable the watchdog */ | |
476 | ||
477 | /* Where do the internal registers live? */ | |
6d0f6bcf | 478 | #define CONFIG_SYS_IMMR 0xF0000000 |
10a36a98 WD |
479 | |
480 | /***************************************************************************** | |
481 | * | |
482 | * You should not have to modify any of the following settings | |
483 | * | |
484 | *****************************************************************************/ | |
fe8c2806 | 485 | |
10a36a98 WD |
486 | #define CONFIG_MPC8260 1 /* This is an MPC8260 CPU */ |
487 | #define CONFIG_SBC8260 1 /* on an EST SBC8260 Board */ | |
9c4c5ae3 | 488 | #define CONFIG_CPM2 1 /* Has a CPM2 */ |
fe8c2806 | 489 | |
fe8c2806 | 490 | |
10a36a98 WD |
491 | /* |
492 | * Miscellaneous configurable options | |
493 | */ | |
866e3089 | 494 | #if defined(CONFIG_CMD_KGDB) |
6d0f6bcf | 495 | # define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ |
fe8c2806 | 496 | #else |
6d0f6bcf | 497 | # define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ |
fe8c2806 WD |
498 | #endif |
499 | ||
10a36a98 | 500 | /* Print Buffer Size */ |
6d0f6bcf | 501 | #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT)+16) |
fe8c2806 | 502 | |
6d0f6bcf | 503 | #define CONFIG_SYS_MAXARGS 32 /* max number of command args */ |
fe8c2806 | 504 | |
6d0f6bcf | 505 | #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ |
fe8c2806 | 506 | |
6d0f6bcf JCPV |
507 | #define CONFIG_SYS_LOAD_ADDR 0x400000 /* default load address */ |
508 | #define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */ | |
10a36a98 | 509 | |
6d0f6bcf JCPV |
510 | #define CONFIG_SYS_ALT_MEMTEST /* Select full-featured memory test */ |
511 | #define CONFIG_SYS_MEMTEST_START 0x2000 /* memtest works from the end of */ | |
10a36a98 WD |
512 | /* the exception vector table */ |
513 | /* to the end of the DRAM */ | |
514 | /* less monitor and malloc area */ | |
6d0f6bcf JCPV |
515 | #define CONFIG_SYS_STACK_USAGE 0x10000 /* Reserve 64k for the stack usage */ |
516 | #define CONFIG_SYS_MEM_END_USAGE ( CONFIG_SYS_MONITOR_LEN \ | |
517 | + CONFIG_SYS_MALLOC_LEN \ | |
0e8d1586 | 518 | + CONFIG_ENV_SECT_SIZE \ |
6d0f6bcf | 519 | + CONFIG_SYS_STACK_USAGE ) |
10a36a98 | 520 | |
6d0f6bcf JCPV |
521 | #define CONFIG_SYS_MEMTEST_END ( CONFIG_SYS_SDRAM_SIZE * 1024 * 1024 \ |
522 | - CONFIG_SYS_MEM_END_USAGE ) | |
10a36a98 WD |
523 | |
524 | /* valid baudrates */ | |
6d0f6bcf | 525 | #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } |
fe8c2806 WD |
526 | |
527 | /* | |
10a36a98 WD |
528 | * Low Level Configuration Settings |
529 | * (address mappings, register initial values, etc.) | |
530 | * You should know what you are doing if you make changes here. | |
fe8c2806 | 531 | */ |
10a36a98 | 532 | |
6d0f6bcf JCPV |
533 | #define CONFIG_SYS_FLASH_BASE CONFIG_SYS_FLASH0_BASE |
534 | #define CONFIG_SYS_FLASH_SIZE CONFIG_SYS_FLASH0_SIZE | |
535 | #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_SDRAM0_BASE | |
536 | #define CONFIG_SYS_SDRAM_SIZE CONFIG_SYS_SDRAM0_SIZE | |
10a36a98 WD |
537 | |
538 | /*----------------------------------------------------------------------- | |
539 | * Hard Reset Configuration Words | |
540 | */ | |
6d0f6bcf JCPV |
541 | #if defined(CONFIG_SYS_SBC_BOOT_LOW) |
542 | # define CONFIG_SYS_SBC_HRCW_BOOT_FLAGS (HRCW_CIP | HRCW_BMS) | |
fe8c2806 | 543 | #else |
6d0f6bcf JCPV |
544 | # define CONFIG_SYS_SBC_HRCW_BOOT_FLAGS (0) |
545 | #endif /* defined(CONFIG_SYS_SBC_BOOT_LOW) */ | |
10a36a98 | 546 | |
6d0f6bcf JCPV |
547 | /* get the HRCW ISB field from CONFIG_SYS_IMMR */ |
548 | #define CONFIG_SYS_SBC_HRCW_IMMR ( ((CONFIG_SYS_IMMR & 0x10000000) >> 10) | \ | |
549 | ((CONFIG_SYS_IMMR & 0x01000000) >> 7) | \ | |
550 | ((CONFIG_SYS_IMMR & 0x00100000) >> 4) ) | |
10a36a98 | 551 | |
6d0f6bcf | 552 | #define CONFIG_SYS_HRCW_MASTER ( HRCW_BPS11 | \ |
10a36a98 | 553 | HRCW_DPPC11 | \ |
6d0f6bcf | 554 | CONFIG_SYS_SBC_HRCW_IMMR | \ |
10a36a98 WD |
555 | HRCW_MMR00 | \ |
556 | HRCW_LBPC11 | \ | |
557 | HRCW_APPC10 | \ | |
558 | HRCW_CS10PC00 | \ | |
6d0f6bcf JCPV |
559 | (CONFIG_SYS_SBC_MODCK_H & HRCW_MODCK_H1111) | \ |
560 | CONFIG_SYS_SBC_HRCW_BOOT_FLAGS ) | |
10a36a98 WD |
561 | |
562 | /* no slaves */ | |
6d0f6bcf JCPV |
563 | #define CONFIG_SYS_HRCW_SLAVE1 0 |
564 | #define CONFIG_SYS_HRCW_SLAVE2 0 | |
565 | #define CONFIG_SYS_HRCW_SLAVE3 0 | |
566 | #define CONFIG_SYS_HRCW_SLAVE4 0 | |
567 | #define CONFIG_SYS_HRCW_SLAVE5 0 | |
568 | #define CONFIG_SYS_HRCW_SLAVE6 0 | |
569 | #define CONFIG_SYS_HRCW_SLAVE7 0 | |
10a36a98 WD |
570 | |
571 | /*----------------------------------------------------------------------- | |
572 | * Definitions for initial stack pointer and data area (in DPRAM) | |
573 | */ | |
6d0f6bcf | 574 | #define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR |
553f0982 | 575 | #define CONFIG_SYS_INIT_RAM_SIZE 0x4000 /* Size of used area in DPRAM */ |
25ddd1fb | 576 | #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) |
6d0f6bcf | 577 | #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET |
10a36a98 WD |
578 | |
579 | /*----------------------------------------------------------------------- | |
580 | * Start addresses for the final memory configuration | |
581 | * (Set up by the startup code) | |
6d0f6bcf JCPV |
582 | * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 |
583 | * Note also that the logic that sets CONFIG_SYS_RAMBOOT is platform dependent. | |
10a36a98 | 584 | */ |
6d0f6bcf | 585 | #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH0_BASE |
10a36a98 | 586 | |
6d0f6bcf JCPV |
587 | #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE) |
588 | # define CONFIG_SYS_RAMBOOT | |
fe8c2806 | 589 | #endif |
10a36a98 | 590 | |
6d0f6bcf JCPV |
591 | #define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ |
592 | #define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ | |
fe8c2806 WD |
593 | |
594 | /* | |
595 | * For booting Linux, the board info and command line data | |
596 | * have to be in the first 8 MB of memory, since this is | |
597 | * the maximum mapped by the Linux kernel during initialization. | |
598 | */ | |
6d0f6bcf | 599 | #define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ |
10a36a98 WD |
600 | |
601 | /*----------------------------------------------------------------------- | |
602 | * FLASH and environment organization | |
603 | */ | |
6d0f6bcf JCPV |
604 | #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ |
605 | #define CONFIG_SYS_MAX_FLASH_SECT 16 /* max number of sectors on one chip */ | |
10a36a98 | 606 | |
6d0f6bcf JCPV |
607 | #define CONFIG_SYS_FLASH_ERASE_TOUT 8000 /* Timeout for Flash Erase (in ms) */ |
608 | #define CONFIG_SYS_FLASH_WRITE_TOUT 1 /* Timeout for Flash Write (in ms) */ | |
10a36a98 | 609 | |
6d0f6bcf | 610 | #ifndef CONFIG_SYS_RAMBOOT |
5a1aceb0 | 611 | # define CONFIG_ENV_IS_IN_FLASH 1 |
10a36a98 | 612 | |
0e8d1586 | 613 | # ifdef CONFIG_ENV_IN_OWN_SECT |
6d0f6bcf | 614 | # define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + 0x40000) |
0e8d1586 | 615 | # define CONFIG_ENV_SECT_SIZE 0x40000 |
10a36a98 | 616 | # else |
6d0f6bcf | 617 | # define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_SYS_MONITOR_LEN - CONFIG_ENV_SECT_SIZE) |
0e8d1586 JCPV |
618 | # define CONFIG_ENV_SIZE 0x1000 /* Total Size of Environment Sector */ |
619 | # define CONFIG_ENV_SECT_SIZE 0x10000 /* see README - env sect real size */ | |
620 | # endif /* CONFIG_ENV_IN_OWN_SECT */ | |
10a36a98 WD |
621 | |
622 | #else | |
9314cee6 | 623 | # define CONFIG_ENV_IS_IN_NVRAM 1 |
6d0f6bcf | 624 | # define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000) |
0e8d1586 | 625 | # define CONFIG_ENV_SIZE 0x200 |
6d0f6bcf | 626 | #endif /* CONFIG_SYS_RAMBOOT */ |
10a36a98 WD |
627 | |
628 | /*----------------------------------------------------------------------- | |
629 | * Cache Configuration | |
630 | */ | |
6d0f6bcf | 631 | #define CONFIG_SYS_CACHELINE_SIZE 32 /* For MPC8260 CPU */ |
fe8c2806 | 632 | |
866e3089 | 633 | #if defined(CONFIG_CMD_KGDB) |
6d0f6bcf | 634 | # define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */ |
fe8c2806 WD |
635 | #endif |
636 | ||
10a36a98 WD |
637 | /*----------------------------------------------------------------------- |
638 | * HIDx - Hardware Implementation-dependent Registers 2-11 | |
639 | *----------------------------------------------------------------------- | |
640 | * HID0 also contains cache control - initially enable both caches and | |
641 | * invalidate contents, then the final state leaves only the instruction | |
642 | * cache enabled. Note that Power-On and Hard reset invalidate the caches, | |
643 | * but Soft reset does not. | |
644 | * | |
645 | * HID1 has only read-only information - nothing to set. | |
646 | */ | |
6d0f6bcf | 647 | #define CONFIG_SYS_HID0_INIT (HID0_ICE |\ |
10a36a98 WD |
648 | HID0_DCE |\ |
649 | HID0_ICFI |\ | |
650 | HID0_DCI |\ | |
651 | HID0_IFEM |\ | |
652 | HID0_ABE) | |
653 | ||
6d0f6bcf | 654 | #define CONFIG_SYS_HID0_FINAL (HID0_ICE |\ |
10a36a98 WD |
655 | HID0_IFEM |\ |
656 | HID0_ABE |\ | |
657 | HID0_EMCP) | |
6d0f6bcf | 658 | #define CONFIG_SYS_HID2 0 |
10a36a98 WD |
659 | |
660 | /*----------------------------------------------------------------------- | |
661 | * RMR - Reset Mode Register | |
662 | *----------------------------------------------------------------------- | |
663 | */ | |
6d0f6bcf | 664 | #define CONFIG_SYS_RMR 0 |
10a36a98 WD |
665 | |
666 | /*----------------------------------------------------------------------- | |
667 | * BCR - Bus Configuration 4-25 | |
668 | *----------------------------------------------------------------------- | |
669 | */ | |
6d0f6bcf | 670 | #define CONFIG_SYS_BCR (BCR_ETM) |
10a36a98 WD |
671 | |
672 | /*----------------------------------------------------------------------- | |
673 | * SIUMCR - SIU Module Configuration 4-31 | |
674 | *----------------------------------------------------------------------- | |
675 | */ | |
676 | ||
6d0f6bcf | 677 | #define CONFIG_SYS_SIUMCR (SIUMCR_DPPC11 |\ |
10a36a98 WD |
678 | SIUMCR_L2CPC00 |\ |
679 | SIUMCR_APPC10 |\ | |
680 | SIUMCR_MMR00) | |
681 | ||
682 | ||
683 | /*----------------------------------------------------------------------- | |
684 | * SYPCR - System Protection Control 11-9 | |
685 | * SYPCR can only be written once after reset! | |
686 | *----------------------------------------------------------------------- | |
687 | * Watchdog & Bus Monitor Timer max, 60x Bus Monitor enable | |
688 | */ | |
689 | #if defined(CONFIG_WATCHDOG) | |
6d0f6bcf | 690 | #define CONFIG_SYS_SYPCR (SYPCR_SWTC |\ |
10a36a98 WD |
691 | SYPCR_BMT |\ |
692 | SYPCR_PBME |\ | |
693 | SYPCR_LBME |\ | |
694 | SYPCR_SWRI |\ | |
695 | SYPCR_SWP |\ | |
696 | SYPCR_SWE) | |
697 | #else | |
6d0f6bcf | 698 | #define CONFIG_SYS_SYPCR (SYPCR_SWTC |\ |
10a36a98 WD |
699 | SYPCR_BMT |\ |
700 | SYPCR_PBME |\ | |
701 | SYPCR_LBME |\ | |
702 | SYPCR_SWRI |\ | |
703 | SYPCR_SWP) | |
704 | #endif /* CONFIG_WATCHDOG */ | |
705 | ||
706 | /*----------------------------------------------------------------------- | |
707 | * TMCNTSC - Time Counter Status and Control 4-40 | |
708 | *----------------------------------------------------------------------- | |
709 | * Clear once per Second and Alarm Interrupt Status, Set 32KHz timersclk, | |
710 | * and enable Time Counter | |
711 | */ | |
6d0f6bcf | 712 | #define CONFIG_SYS_TMCNTSC (TMCNTSC_SEC |\ |
10a36a98 WD |
713 | TMCNTSC_ALR |\ |
714 | TMCNTSC_TCF |\ | |
715 | TMCNTSC_TCE) | |
716 | ||
717 | /*----------------------------------------------------------------------- | |
718 | * PISCR - Periodic Interrupt Status and Control 4-42 | |
719 | *----------------------------------------------------------------------- | |
720 | * Clear Periodic Interrupt Status, Set 32KHz timersclk, and enable | |
721 | * Periodic timer | |
722 | */ | |
6d0f6bcf | 723 | #define CONFIG_SYS_PISCR (PISCR_PS |\ |
10a36a98 WD |
724 | PISCR_PTF |\ |
725 | PISCR_PTE) | |
726 | ||
727 | /*----------------------------------------------------------------------- | |
728 | * SCCR - System Clock Control 9-8 | |
729 | *----------------------------------------------------------------------- | |
730 | */ | |
6d0f6bcf | 731 | #define CONFIG_SYS_SCCR 0 |
10a36a98 WD |
732 | |
733 | /*----------------------------------------------------------------------- | |
734 | * RCCR - RISC Controller Configuration 13-7 | |
735 | *----------------------------------------------------------------------- | |
736 | */ | |
6d0f6bcf | 737 | #define CONFIG_SYS_RCCR 0 |
10a36a98 | 738 | |
fe8c2806 | 739 | /* |
10a36a98 WD |
740 | * Initialize Memory Controller: |
741 | * | |
742 | * Bank Bus Machine PortSz Device | |
743 | * ---- --- ------- ------ ------ | |
744 | * 0 60x GPCM 32 bit FLASH (SIMM - 4MB) * | |
745 | * 1 60x GPCM 32 bit FLASH (SIMM - Unused) | |
746 | * 2 60x SDRAM 64 bit SDRAM (DIMM - 16MB or 64MB) | |
747 | * 3 60x SDRAM 64 bit SDRAM (DIMM - Unused) | |
748 | * 4 Local SDRAM 32 bit SDRAM (on board - 4MB) | |
749 | * 5 60x GPCM 8 bit EEPROM (8KB) | |
750 | * 6 60x GPCM 8 bit FLASH (on board - 2MB) * | |
751 | * 7 60x GPCM 8 bit LEDs, switches | |
752 | * | |
753 | * (*) This configuration requires the SBC8260 be configured | |
754 | * so that *CS0 goes to the FLASH SIMM, and *CS6 goes to | |
755 | * the on board FLASH. In other words, JP24 should have | |
756 | * pins 1 and 2 jumpered and pins 3 and 4 jumpered. | |
fe8c2806 | 757 | * |
fe8c2806 | 758 | */ |
fe8c2806 | 759 | |
10a36a98 WD |
760 | /*----------------------------------------------------------------------- |
761 | * BR0,BR1 - Base Register | |
762 | * Ref: Section 10.3.1 on page 10-14 | |
763 | * OR0,OR1 - Option Register | |
764 | * Ref: Section 10.3.2 on page 10-18 | |
765 | *----------------------------------------------------------------------- | |
766 | */ | |
767 | ||
768 | /* Bank 0,1 - FLASH SIMM | |
769 | * | |
770 | * This expects the FLASH SIMM to be connected to *CS0 | |
771 | * It consists of 4 AM29F080B parts. | |
772 | * | |
773 | * Note: For the 4 MB SIMM, *CS1 is unused. | |
774 | */ | |
775 | ||
776 | /* BR0 is configured as follows: | |
777 | * | |
778 | * - Base address of 0x40000000 | |
779 | * - 32 bit port size | |
780 | * - Data errors checking is disabled | |
781 | * - Read and write access | |
782 | * - GPCM 60x bus | |
783 | * - Access are handled by the memory controller according to MSEL | |
784 | * - Not used for atomic operations | |
785 | * - No data pipelining is done | |
786 | * - Valid | |
787 | */ | |
6d0f6bcf | 788 | #define CONFIG_SYS_BR0_PRELIM ((CONFIG_SYS_FLASH0_BASE & BRx_BA_MSK) |\ |
10a36a98 WD |
789 | BRx_PS_32 |\ |
790 | BRx_MS_GPCM_P |\ | |
791 | BRx_V) | |
792 | ||
793 | /* OR0 is configured as follows: | |
794 | * | |
795 | * - 4 MB | |
796 | * - *BCTL0 is asserted upon access to the current memory bank | |
797 | * - *CW / *WE are negated a quarter of a clock earlier | |
798 | * - *CS is output at the same time as the address lines | |
799 | * - Uses a clock cycle length of 5 | |
800 | * - *PSDVAL is generated internally by the memory controller | |
801 | * unless *GTA is asserted earlier externally. | |
802 | * - Relaxed timing is generated by the GPCM for accesses | |
803 | * initiated to this memory region. | |
804 | * - One idle clock is inserted between a read access from the | |
805 | * current bank and the next access. | |
806 | */ | |
6d0f6bcf | 807 | #define CONFIG_SYS_OR0_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH0_SIZE) |\ |
10a36a98 WD |
808 | ORxG_CSNT |\ |
809 | ORxG_ACS_DIV1 |\ | |
810 | ORxG_SCY_5_CLK |\ | |
811 | ORxG_TRLX |\ | |
812 | ORxG_EHTR) | |
813 | ||
814 | /*----------------------------------------------------------------------- | |
815 | * BR2,BR3 - Base Register | |
816 | * Ref: Section 10.3.1 on page 10-14 | |
817 | * OR2,OR3 - Option Register | |
818 | * Ref: Section 10.3.2 on page 10-16 | |
819 | *----------------------------------------------------------------------- | |
820 | */ | |
821 | ||
822 | /* Bank 2,3 - SDRAM DIMM | |
823 | * | |
824 | * 16MB DIMM: P/N | |
825 | * 64MB DIMM: P/N 1W-8864X8-4-P1-EST | |
826 | * | |
827 | * Note: *CS3 is unused for this DIMM | |
828 | */ | |
829 | ||
830 | /* With a 16 MB or 64 MB DIMM, the BR2 is configured as follows: | |
831 | * | |
832 | * - Base address of 0x00000000 | |
833 | * - 64 bit port size (60x bus only) | |
834 | * - Data errors checking is disabled | |
835 | * - Read and write access | |
836 | * - SDRAM 60x bus | |
837 | * - Access are handled by the memory controller according to MSEL | |
838 | * - Not used for atomic operations | |
839 | * - No data pipelining is done | |
840 | * - Valid | |
841 | */ | |
6d0f6bcf | 842 | #define CONFIG_SYS_BR2_PRELIM ((CONFIG_SYS_SDRAM0_BASE & BRx_BA_MSK) |\ |
10a36a98 WD |
843 | BRx_PS_64 |\ |
844 | BRx_MS_SDRAM_P |\ | |
845 | BRx_V) | |
846 | ||
6d0f6bcf | 847 | #define CONFIG_SYS_BR3_PRELIM ((CONFIG_SYS_SDRAM0_BASE & BRx_BA_MSK) |\ |
10a36a98 WD |
848 | BRx_PS_64 |\ |
849 | BRx_MS_SDRAM_P |\ | |
850 | BRx_V) | |
851 | ||
852 | /* With a 16 MB DIMM, the OR2 is configured as follows: | |
853 | * | |
854 | * - 16 MB | |
855 | * - 2 internal banks per device | |
856 | * - Row start address bit is A9 with PSDMR[PBI] = 0 | |
857 | * - 11 row address lines | |
858 | * - Back-to-back page mode | |
859 | * - Internal bank interleaving within save device enabled | |
860 | */ | |
6d0f6bcf JCPV |
861 | #if (CONFIG_SYS_SDRAM0_SIZE == 16) |
862 | #define CONFIG_SYS_OR2_PRELIM (MEG_TO_AM(CONFIG_SYS_SDRAM0_SIZE) |\ | |
10a36a98 WD |
863 | ORxS_BPD_2 |\ |
864 | ORxS_ROWST_PBI0_A9 |\ | |
865 | ORxS_NUMR_11) | |
fe8c2806 WD |
866 | #endif |
867 | ||
10a36a98 WD |
868 | /* With a 64 MB DIMM, the OR2 is configured as follows: |
869 | * | |
870 | * - 64 MB | |
871 | * - 4 internal banks per device | |
872 | * - Row start address bit is A8 with PSDMR[PBI] = 0 | |
873 | * - 12 row address lines | |
874 | * - Back-to-back page mode | |
875 | * - Internal bank interleaving within save device enabled | |
876 | */ | |
6d0f6bcf JCPV |
877 | #if (CONFIG_SYS_SDRAM0_SIZE == 64) |
878 | #define CONFIG_SYS_OR2_PRELIM (MEG_TO_AM(CONFIG_SYS_SDRAM0_SIZE) |\ | |
10a36a98 WD |
879 | ORxS_BPD_4 |\ |
880 | ORxS_ROWST_PBI0_A8 |\ | |
881 | ORxS_NUMR_12) | |
fe8c2806 | 882 | #endif |
fe8c2806 | 883 | |
10a36a98 WD |
884 | /*----------------------------------------------------------------------- |
885 | * PSDMR - 60x Bus SDRAM Mode Register | |
886 | * Ref: Section 10.3.3 on page 10-21 | |
887 | *----------------------------------------------------------------------- | |
888 | */ | |
889 | ||
890 | /* Address that the DIMM SPD memory lives at. | |
891 | */ | |
892 | #define SDRAM_SPD_ADDR 0x54 | |
893 | ||
6d0f6bcf | 894 | #if (CONFIG_SYS_SDRAM0_SIZE == 16) |
10a36a98 WD |
895 | /* With a 16 MB DIMM, the PSDMR is configured as follows: |
896 | * | |
897 | * - Bank Based Interleaving, | |
898 | * - Refresh Enable, | |
899 | * - Address Multiplexing where A5 is output on A14 pin | |
900 | * (A6 on A15, and so on), | |
901 | * - use address pins A16-A18 as bank select, | |
902 | * - A9 is output on SDA10 during an ACTIVATE command, | |
903 | * - earliest timing for ACTIVATE command after REFRESH command is 7 clocks, | |
904 | * - earliest timing for ACTIVATE or REFRESH command after PRECHARGE command | |
905 | * is 3 clocks, | |
906 | * - earliest timing for READ/WRITE command after ACTIVATE command is | |
907 | * 2 clocks, | |
908 | * - earliest timing for PRECHARGE after last data was read is 1 clock, | |
909 | * - earliest timing for PRECHARGE after last data was written is 1 clock, | |
910 | * - CAS Latency is 2. | |
911 | */ | |
6d0f6bcf | 912 | #define CONFIG_SYS_PSDMR (PSDMR_RFEN |\ |
10a36a98 WD |
913 | PSDMR_SDAM_A14_IS_A5 |\ |
914 | PSDMR_BSMA_A16_A18 |\ | |
915 | PSDMR_SDA10_PBI0_A9 |\ | |
916 | PSDMR_RFRC_7_CLK |\ | |
917 | PSDMR_PRETOACT_3W |\ | |
918 | PSDMR_ACTTORW_2W |\ | |
919 | PSDMR_LDOTOPRE_1C |\ | |
920 | PSDMR_WRC_1C |\ | |
921 | PSDMR_CL_2) | |
922 | #endif | |
923 | ||
6d0f6bcf | 924 | #if (CONFIG_SYS_SDRAM0_SIZE == 64) |
10a36a98 WD |
925 | /* With a 64 MB DIMM, the PSDMR is configured as follows: |
926 | * | |
927 | * - Bank Based Interleaving, | |
928 | * - Refresh Enable, | |
929 | * - Address Multiplexing where A5 is output on A14 pin | |
930 | * (A6 on A15, and so on), | |
931 | * - use address pins A14-A16 as bank select, | |
932 | * - A9 is output on SDA10 during an ACTIVATE command, | |
933 | * - earliest timing for ACTIVATE command after REFRESH command is 7 clocks, | |
934 | * - earliest timing for ACTIVATE or REFRESH command after PRECHARGE command | |
935 | * is 3 clocks, | |
936 | * - earliest timing for READ/WRITE command after ACTIVATE command is | |
937 | * 2 clocks, | |
938 | * - earliest timing for PRECHARGE after last data was read is 1 clock, | |
939 | * - earliest timing for PRECHARGE after last data was written is 1 clock, | |
940 | * - CAS Latency is 2. | |
941 | */ | |
6d0f6bcf | 942 | #define CONFIG_SYS_PSDMR (PSDMR_RFEN |\ |
10a36a98 WD |
943 | PSDMR_SDAM_A14_IS_A5 |\ |
944 | PSDMR_BSMA_A14_A16 |\ | |
945 | PSDMR_SDA10_PBI0_A9 |\ | |
946 | PSDMR_RFRC_7_CLK |\ | |
947 | PSDMR_PRETOACT_3W |\ | |
948 | PSDMR_ACTTORW_2W |\ | |
949 | PSDMR_LDOTOPRE_1C |\ | |
950 | PSDMR_WRC_1C |\ | |
951 | PSDMR_CL_2) | |
952 | #endif | |
953 | ||
954 | /* | |
955 | * Shoot for approximately 1MHz on the prescaler. | |
956 | */ | |
957 | #if (CONFIG_8260_CLKIN == (66 * 1000 * 1000)) | |
6d0f6bcf | 958 | #define CONFIG_SYS_MPTPR MPTPR_PTP_DIV64 |
10a36a98 | 959 | #elif (CONFIG_8260_CLKIN == (33 * 1000 * 1000)) |
6d0f6bcf | 960 | #define CONFIG_SYS_MPTPR MPTPR_PTP_DIV32 |
10a36a98 | 961 | #else |
6d0f6bcf JCPV |
962 | #warning "Unconfigured bus clock freq: check CONFIG_SYS_MPTPR and CONFIG_SYS_PSRT are OK" |
963 | #define CONFIG_SYS_MPTPR MPTPR_PTP_DIV32 | |
10a36a98 | 964 | #endif |
6d0f6bcf | 965 | #define CONFIG_SYS_PSRT 14 |
10a36a98 WD |
966 | |
967 | ||
968 | /* Bank 4 - On board SDRAM | |
969 | * | |
970 | * This is not implemented yet. | |
971 | */ | |
972 | ||
973 | /*----------------------------------------------------------------------- | |
974 | * BR6 - Base Register | |
975 | * Ref: Section 10.3.1 on page 10-14 | |
976 | * OR6 - Option Register | |
977 | * Ref: Section 10.3.2 on page 10-18 | |
978 | *----------------------------------------------------------------------- | |
979 | */ | |
980 | ||
981 | /* Bank 6 - On board FLASH | |
982 | * | |
983 | * This expects the on board FLASH SIMM to be connected to *CS6 | |
984 | * It consists of 1 AM29F016A part. | |
985 | */ | |
6d0f6bcf | 986 | #if (defined(CONFIG_SYS_FLASH1_BASE) && defined(CONFIG_SYS_FLASH1_SIZE)) |
10a36a98 WD |
987 | |
988 | /* BR6 is configured as follows: | |
989 | * | |
990 | * - Base address of 0x60000000 | |
991 | * - 8 bit port size | |
992 | * - Data errors checking is disabled | |
993 | * - Read and write access | |
994 | * - GPCM 60x bus | |
995 | * - Access are handled by the memory controller according to MSEL | |
996 | * - Not used for atomic operations | |
997 | * - No data pipelining is done | |
998 | * - Valid | |
999 | */ | |
6d0f6bcf | 1000 | # define CONFIG_SYS_BR6_PRELIM ((CONFIG_SYS_FLASH1_BASE & BRx_BA_MSK) |\ |
10a36a98 WD |
1001 | BRx_PS_8 |\ |
1002 | BRx_MS_GPCM_P |\ | |
1003 | BRx_V) | |
1004 | ||
1005 | /* OR6 is configured as follows: | |
1006 | * | |
1007 | * - 2 MB | |
1008 | * - *BCTL0 is asserted upon access to the current memory bank | |
1009 | * - *CW / *WE are negated a quarter of a clock earlier | |
1010 | * - *CS is output at the same time as the address lines | |
1011 | * - Uses a clock cycle length of 5 | |
1012 | * - *PSDVAL is generated internally by the memory controller | |
1013 | * unless *GTA is asserted earlier externally. | |
1014 | * - Relaxed timing is generated by the GPCM for accesses | |
1015 | * initiated to this memory region. | |
1016 | * - One idle clock is inserted between a read access from the | |
1017 | * current bank and the next access. | |
1018 | */ | |
6d0f6bcf | 1019 | # define CONFIG_SYS_OR6_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH1_SIZE) |\ |
10a36a98 WD |
1020 | ORxG_CSNT |\ |
1021 | ORxG_ACS_DIV1 |\ | |
1022 | ORxG_SCY_5_CLK |\ | |
1023 | ORxG_TRLX |\ | |
1024 | ORxG_EHTR) | |
6d0f6bcf | 1025 | #endif /* (defined(CONFIG_SYS_FLASH1_BASE) && defined(CONFIG_SYS_FLASH1_SIZE)) */ |
10a36a98 WD |
1026 | |
1027 | /*----------------------------------------------------------------------- | |
1028 | * BR7 - Base Register | |
1029 | * Ref: Section 10.3.1 on page 10-14 | |
1030 | * OR7 - Option Register | |
1031 | * Ref: Section 10.3.2 on page 10-18 | |
1032 | *----------------------------------------------------------------------- | |
1033 | */ | |
1034 | ||
1035 | /* Bank 7 - LEDs and switches | |
1036 | * | |
1037 | * LEDs are at 0x00001 (write only) | |
1038 | * switches are at 0x00001 (read only) | |
1039 | */ | |
6d0f6bcf | 1040 | #ifdef CONFIG_SYS_LED_BASE |
10a36a98 WD |
1041 | |
1042 | /* BR7 is configured as follows: | |
1043 | * | |
1044 | * - Base address of 0xA0000000 | |
1045 | * - 8 bit port size | |
1046 | * - Data errors checking is disabled | |
1047 | * - Read and write access | |
1048 | * - GPCM 60x bus | |
1049 | * - Access are handled by the memory controller according to MSEL | |
1050 | * - Not used for atomic operations | |
1051 | * - No data pipelining is done | |
1052 | * - Valid | |
1053 | */ | |
6d0f6bcf | 1054 | # define CONFIG_SYS_BR7_PRELIM ((CONFIG_SYS_LED_BASE & BRx_BA_MSK) |\ |
10a36a98 WD |
1055 | BRx_PS_8 |\ |
1056 | BRx_MS_GPCM_P |\ | |
1057 | BRx_V) | |
1058 | ||
1059 | /* OR7 is configured as follows: | |
1060 | * | |
1061 | * - 1 byte | |
1062 | * - *BCTL0 is asserted upon access to the current memory bank | |
1063 | * - *CW / *WE are negated a quarter of a clock earlier | |
1064 | * - *CS is output at the same time as the address lines | |
1065 | * - Uses a clock cycle length of 15 | |
1066 | * - *PSDVAL is generated internally by the memory controller | |
1067 | * unless *GTA is asserted earlier externally. | |
1068 | * - Relaxed timing is generated by the GPCM for accesses | |
1069 | * initiated to this memory region. | |
1070 | * - One idle clock is inserted between a read access from the | |
1071 | * current bank and the next access. | |
1072 | */ | |
6d0f6bcf | 1073 | # define CONFIG_SYS_OR7_PRELIM (ORxG_AM_MSK |\ |
10a36a98 WD |
1074 | ORxG_CSNT |\ |
1075 | ORxG_ACS_DIV1 |\ | |
1076 | ORxG_SCY_15_CLK |\ | |
1077 | ORxG_TRLX |\ | |
1078 | ORxG_EHTR) | |
6d0f6bcf | 1079 | #endif /* CONFIG_SYS_LED_BASE */ |
fe8c2806 | 1080 | #endif /* __CONFIG_H */ |