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9e3ed392 | 1 | /* |
2738bc8d | 2 | * Copyright 2007,2009 Wind River Systems <www.windriver.com> |
9e3ed392 JH |
3 | * Copyright 2007 Embedded Specialties, Inc. |
4 | * Copyright 2004, 2007 Freescale Semiconductor. | |
5 | * | |
1a459660 | 6 | * SPDX-License-Identifier: GPL-2.0+ |
9e3ed392 JH |
7 | */ |
8 | ||
9 | /* | |
10 | * sbc8548 board configuration file | |
2738bc8d | 11 | * Please refer to doc/README.sbc8548 for more info. |
9e3ed392 JH |
12 | */ |
13 | #ifndef __CONFIG_H | |
14 | #define __CONFIG_H | |
15 | ||
2738bc8d PG |
16 | /* |
17 | * Top level Makefile configuration choices | |
18 | */ | |
d24f2d32 | 19 | #ifdef CONFIG_PCI |
842033e6 | 20 | #define CONFIG_PCI_INDIRECT_BRIDGE |
2738bc8d PG |
21 | #define CONFIG_PCI1 |
22 | #endif | |
23 | ||
d24f2d32 | 24 | #ifdef CONFIG_66 |
2738bc8d PG |
25 | #define CONFIG_SYS_CLK_DIV 1 |
26 | #endif | |
27 | ||
d24f2d32 | 28 | #ifdef CONFIG_33 |
2738bc8d PG |
29 | #define CONFIG_SYS_CLK_DIV 2 |
30 | #endif | |
31 | ||
d24f2d32 | 32 | #ifdef CONFIG_PCIE |
2738bc8d PG |
33 | #define CONFIG_PCIE1 |
34 | #endif | |
35 | ||
36 | /* | |
37 | * High Level Configuration Options | |
38 | */ | |
9e3ed392 JH |
39 | #define CONFIG_BOOKE 1 /* BOOKE */ |
40 | #define CONFIG_E500 1 /* BOOKE e500 family */ | |
9e3ed392 JH |
41 | #define CONFIG_MPC8548 1 /* MPC8548 specific */ |
42 | #define CONFIG_SBC8548 1 /* SBC8548 board specific */ | |
43 | ||
f0aec4ea PG |
44 | /* |
45 | * If you want to boot from the SODIMM flash, instead of the soldered | |
46 | * on flash, set this, and change JP12, SW2:8 accordingly. | |
47 | */ | |
48 | #undef CONFIG_SYS_ALT_BOOT | |
49 | ||
2ae18241 | 50 | #ifndef CONFIG_SYS_TEXT_BASE |
f0aec4ea PG |
51 | #ifdef CONFIG_SYS_ALT_BOOT |
52 | #define CONFIG_SYS_TEXT_BASE 0xfff00000 | |
53 | #else | |
2ae18241 WD |
54 | #define CONFIG_SYS_TEXT_BASE 0xfffa0000 |
55 | #endif | |
f0aec4ea | 56 | #endif |
2ae18241 | 57 | |
9e3ed392 | 58 | #undef CONFIG_RIO |
fdc7eb90 PG |
59 | |
60 | #ifdef CONFIG_PCI | |
61 | #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ | |
62 | #define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */ | |
63 | #endif | |
64 | #ifdef CONFIG_PCIE1 | |
65 | #define CONFIG_FSL_PCIE_RESET 1 /* need PCIe reset errata */ | |
66 | #endif | |
9e3ed392 JH |
67 | |
68 | #define CONFIG_TSEC_ENET /* tsec ethernet support */ | |
69 | #define CONFIG_ENV_OVERWRITE | |
9e3ed392 | 70 | |
9e3ed392 JH |
71 | #define CONFIG_INTERRUPTS /* enable pci, srio, ddr interrupts */ |
72 | ||
e2b159d0 | 73 | #define CONFIG_FSL_LAW 1 /* Use common FSL init code */ |
9e3ed392 | 74 | |
2738bc8d PG |
75 | /* |
76 | * Below assumes that CCB:SYSCLK remains unchanged at 6:1 via SW2:[1-4] | |
77 | */ | |
78 | #ifndef CONFIG_SYS_CLK_DIV | |
79 | #define CONFIG_SYS_CLK_DIV 1 /* 2, if 33MHz PCI card installed */ | |
80 | #endif | |
81 | #define CONFIG_SYS_CLK_FREQ (66000000 / CONFIG_SYS_CLK_DIV) | |
9e3ed392 JH |
82 | |
83 | /* | |
84 | * These can be toggled for performance analysis, otherwise use default. | |
85 | */ | |
86 | #define CONFIG_L2_CACHE /* toggle L2 cache */ | |
87 | #define CONFIG_BTB /* toggle branch predition */ | |
9e3ed392 JH |
88 | |
89 | /* | |
90 | * Only possible on E500 Version 2 or newer cores. | |
91 | */ | |
92 | #define CONFIG_ENABLE_36BIT_PHYS 1 | |
93 | ||
94 | #define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */ | |
95 | ||
6d0f6bcf JCPV |
96 | #undef CONFIG_SYS_DRAM_TEST /* memory test, takes time */ |
97 | #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */ | |
98 | #define CONFIG_SYS_MEMTEST_END 0x00400000 | |
9e3ed392 | 99 | |
e46fedfe TT |
100 | #define CONFIG_SYS_CCSRBAR 0xe0000000 |
101 | #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR | |
9e3ed392 | 102 | |
33b9079b | 103 | /* DDR Setup */ |
5614e71b | 104 | #define CONFIG_SYS_FSL_DDR2 |
33b9079b | 105 | #undef CONFIG_FSL_DDR_INTERACTIVE |
7e44f2b7 PG |
106 | #undef CONFIG_DDR_ECC /* only for ECC DDR module */ |
107 | /* | |
108 | * A hardware errata caused the LBC SDRAM SPD and the DDR2 SPD | |
109 | * to collide, meaning you couldn't reliably read either. So | |
110 | * physically remove the LBC PC100 SDRAM module from the board | |
3e3262bd PG |
111 | * before enabling the two SPD options below, or check that you |
112 | * have the hardware fix on your board via "i2c probe" and looking | |
113 | * for a device at 0x53. | |
7e44f2b7 | 114 | */ |
33b9079b KG |
115 | #undef CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */ |
116 | #undef CONFIG_DDR_SPD | |
33b9079b KG |
117 | |
118 | #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER /* DDR controller or DMA? */ | |
119 | #define CONFIG_MEM_INIT_VALUE 0xDeadBeef | |
120 | ||
6d0f6bcf JCPV |
121 | #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 |
122 | #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE | |
33b9079b KG |
123 | #define CONFIG_VERY_BIG_RAM |
124 | ||
125 | #define CONFIG_NUM_DDR_CONTROLLERS 1 | |
126 | #define CONFIG_DIMM_SLOTS_PER_CTLR 1 | |
127 | #define CONFIG_CHIP_SELECTS_PER_CTRL 2 | |
9e3ed392 | 128 | |
3e3262bd PG |
129 | /* |
130 | * The hardware fix for the I2C address collision puts the DDR | |
131 | * SPD at 0x53, but if we are running on an older board w/o the | |
132 | * fix, it will still be at 0x51. We check 0x53 1st. | |
133 | */ | |
33b9079b | 134 | #define SPD_EEPROM_ADDRESS 0x51 /* CTLR 0 DIMM 0 */ |
3e3262bd | 135 | #define ALT_SPD_EEPROM_ADDRESS 0x53 /* CTLR 0 DIMM 0 */ |
9e3ed392 JH |
136 | |
137 | /* | |
138 | * Make sure required options are set | |
139 | */ | |
140 | #ifndef CONFIG_SPD_EEPROM | |
6d0f6bcf | 141 | #define CONFIG_SYS_SDRAM_SIZE 256 /* DDR is 256MB */ |
2a6b3b74 | 142 | #define CONFIG_SYS_DDR_CONTROL 0xc300c000 |
9e3ed392 JH |
143 | #endif |
144 | ||
145 | #undef CONFIG_CLOCKS_IN_MHZ | |
146 | ||
147 | /* | |
148 | * FLASH on the Local Bus | |
149 | * Two banks, one 8MB the other 64MB, using the CFI driver. | |
f0aec4ea PG |
150 | * JP12+SW2.8 are used to swap CS0 and CS6, defaults are to have |
151 | * CS0 the 8MB boot flash, and CS6 the 64MB flash. | |
152 | * | |
153 | * Default: | |
154 | * ec00_0000 efff_ffff 64MB SODIMM | |
155 | * ff80_0000 ffff_ffff 8MB soldered flash | |
9e3ed392 | 156 | * |
f0aec4ea PG |
157 | * Alternate: |
158 | * ef80_0000 efff_ffff 8MB soldered flash | |
159 | * fc00_0000 ffff_ffff 64MB SODIMM | |
160 | * | |
161 | * BR0_8M: | |
9e3ed392 JH |
162 | * Base address 0 = 0xff80_0000 = BR0[0:16] = 1111 1111 1000 0000 0 |
163 | * Port Size = 8 bits = BRx[19:20] = 01 | |
164 | * Use GPCM = BRx[24:26] = 000 | |
165 | * Valid = BRx[31] = 1 | |
166 | * | |
f0aec4ea PG |
167 | * BR0_64M: |
168 | * Base address 0 = 0xfc00_0000 = BR0[0:16] = 1111 1100 0000 0000 0 | |
9e3ed392 | 169 | * Port Size = 32 bits = BRx[19:20] = 11 |
f0aec4ea PG |
170 | * |
171 | * 0 4 8 12 16 20 24 28 | |
172 | * 1111 1111 1000 0000 0000 1000 0000 0001 = ff800801 BR0_8M | |
173 | * 1111 1100 0000 0000 0001 1000 0000 0001 = fc001801 BR0_64M | |
174 | */ | |
175 | #define CONFIG_SYS_BR0_8M 0xff800801 | |
176 | #define CONFIG_SYS_BR0_64M 0xfc001801 | |
177 | ||
178 | /* | |
179 | * BR6_8M: | |
180 | * Base address 6 = 0xef80_0000 = BR6[0:16] = 1110 1111 1000 0000 0 | |
181 | * Port Size = 8 bits = BRx[19:20] = 01 | |
9e3ed392 JH |
182 | * Use GPCM = BRx[24:26] = 000 |
183 | * Valid = BRx[31] = 1 | |
f0aec4ea PG |
184 | |
185 | * BR6_64M: | |
186 | * Base address 6 = 0xec00_0000 = BR6[0:16] = 1110 1100 0000 0000 0 | |
187 | * Port Size = 32 bits = BRx[19:20] = 11 | |
9e3ed392 JH |
188 | * |
189 | * 0 4 8 12 16 20 24 28 | |
f0aec4ea PG |
190 | * 1110 1111 1000 0000 0000 1000 0000 0001 = ef800801 BR6_8M |
191 | * 1110 1100 0000 0000 0001 1000 0000 0001 = ec001801 BR6_64M | |
192 | */ | |
193 | #define CONFIG_SYS_BR6_8M 0xef800801 | |
194 | #define CONFIG_SYS_BR6_64M 0xec001801 | |
195 | ||
196 | /* | |
197 | * OR0_8M: | |
9e3ed392 JH |
198 | * Addr Mask = 8M = OR1[0:16] = 1111 1111 1000 0000 0 |
199 | * XAM = OR0[17:18] = 11 | |
200 | * CSNT = OR0[20] = 1 | |
201 | * ACS = half cycle delay = OR0[21:22] = 11 | |
202 | * SCY = 6 = OR0[24:27] = 0110 | |
203 | * TRLX = use relaxed timing = OR0[29] = 1 | |
204 | * EAD = use external address latch delay = OR0[31] = 1 | |
205 | * | |
f0aec4ea PG |
206 | * OR0_64M: |
207 | * Addr Mask = 64M = OR1[0:16] = 1111 1100 0000 0000 0 | |
9e3ed392 | 208 | * |
f0aec4ea PG |
209 | * |
210 | * 0 4 8 12 16 20 24 28 | |
211 | * 1111 1111 1000 0000 0110 1110 0110 0101 = ff806e65 OR0_8M | |
212 | * 1111 1100 0000 0000 0110 1110 0110 0101 = fc006e65 OR0_64M | |
213 | */ | |
214 | #define CONFIG_SYS_OR0_8M 0xff806e65 | |
215 | #define CONFIG_SYS_OR0_64M 0xfc006e65 | |
216 | ||
217 | /* | |
218 | * OR6_8M: | |
219 | * Addr Mask = 8M = OR6[0:16] = 1111 1111 1000 0000 0 | |
9e3ed392 JH |
220 | * XAM = OR6[17:18] = 11 |
221 | * CSNT = OR6[20] = 1 | |
222 | * ACS = half cycle delay = OR6[21:22] = 11 | |
223 | * SCY = 6 = OR6[24:27] = 0110 | |
224 | * TRLX = use relaxed timing = OR6[29] = 1 | |
225 | * EAD = use external address latch delay = OR6[31] = 1 | |
226 | * | |
f0aec4ea PG |
227 | * OR6_64M: |
228 | * Addr Mask = 64M = OR6[0:16] = 1111 1100 0000 0000 0 | |
229 | * | |
9e3ed392 | 230 | * 0 4 8 12 16 20 24 28 |
f0aec4ea PG |
231 | * 1111 1111 1000 0000 0110 1110 0110 0101 = ff806e65 OR6_8M |
232 | * 1111 1100 0000 0000 0110 1110 0110 0101 = fc006e65 OR6_64M | |
9e3ed392 | 233 | */ |
f0aec4ea PG |
234 | #define CONFIG_SYS_OR6_8M 0xff806e65 |
235 | #define CONFIG_SYS_OR6_64M 0xfc006e65 | |
9e3ed392 | 236 | |
f0aec4ea | 237 | #ifndef CONFIG_SYS_ALT_BOOT /* JP12 in default position */ |
6d0f6bcf | 238 | #define CONFIG_SYS_BOOT_BLOCK 0xff800000 /* start of 8MB Flash */ |
3fd673cf | 239 | #define CONFIG_SYS_ALT_FLASH 0xec000000 /* 64MB "user" flash */ |
9e3ed392 | 240 | |
f0aec4ea PG |
241 | #define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_BR0_8M |
242 | #define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_OR0_8M | |
243 | ||
244 | #define CONFIG_SYS_BR6_PRELIM CONFIG_SYS_BR6_64M | |
245 | #define CONFIG_SYS_OR6_PRELIM CONFIG_SYS_OR6_64M | |
246 | #else /* JP12 in alternate position */ | |
247 | #define CONFIG_SYS_BOOT_BLOCK 0xfc000000 /* start 64MB Flash */ | |
248 | #define CONFIG_SYS_ALT_FLASH 0xef800000 /* 8MB soldered flash */ | |
9e3ed392 | 249 | |
f0aec4ea PG |
250 | #define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_BR0_64M |
251 | #define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_OR0_64M | |
252 | ||
253 | #define CONFIG_SYS_BR6_PRELIM CONFIG_SYS_BR6_8M | |
254 | #define CONFIG_SYS_OR6_PRELIM CONFIG_SYS_OR6_8M | |
255 | #endif | |
9e3ed392 | 256 | |
f0aec4ea | 257 | #define CONFIG_SYS_FLASH_BASE CONFIG_SYS_BOOT_BLOCK |
9b3ba24f PG |
258 | #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE, \ |
259 | CONFIG_SYS_ALT_FLASH} | |
260 | #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */ | |
261 | #define CONFIG_SYS_MAX_FLASH_SECT 256 /* sectors per device */ | |
6d0f6bcf JCPV |
262 | #undef CONFIG_SYS_FLASH_CHECKSUM |
263 | #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ | |
264 | #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ | |
9e3ed392 | 265 | |
14d0a02a | 266 | #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ |
9e3ed392 | 267 | |
00b1883a | 268 | #define CONFIG_FLASH_CFI_DRIVER |
6d0f6bcf JCPV |
269 | #define CONFIG_SYS_FLASH_CFI |
270 | #define CONFIG_SYS_FLASH_EMPTY_INFO | |
9e3ed392 JH |
271 | |
272 | /* CS5 = Local bus peripherals controlled by the EPLD */ | |
273 | ||
6d0f6bcf JCPV |
274 | #define CONFIG_SYS_BR5_PRELIM 0xf8000801 |
275 | #define CONFIG_SYS_OR5_PRELIM 0xff006e65 | |
276 | #define CONFIG_SYS_EPLD_BASE 0xf8000000 | |
277 | #define CONFIG_SYS_LED_DISP_BASE 0xf8000000 | |
278 | #define CONFIG_SYS_USER_SWITCHES_BASE 0xf8100000 | |
279 | #define CONFIG_SYS_BD_REV 0xf8300000 | |
280 | #define CONFIG_SYS_EEPROM_BASE 0xf8b00000 | |
9e3ed392 JH |
281 | |
282 | /* | |
11d5a629 | 283 | * SDRAM on the Local Bus (CS3 and CS4) |
7e44f2b7 PG |
284 | * Note that most boards have a hardware errata where both the |
285 | * LBC SDRAM and the DDR2 SDRAM decode at 0x51, making it impossible | |
286 | * to use CONFIG_DDR_SPD unless you physically remove the LBC DIMM. | |
3e3262bd | 287 | * A hardware workaround is also available, see README.sbc8548 file. |
9e3ed392 | 288 | */ |
6d0f6bcf | 289 | #define CONFIG_SYS_LBC_SDRAM_BASE 0xf0000000 /* Localbus SDRAM */ |
11d5a629 | 290 | #define CONFIG_SYS_LBC_SDRAM_SIZE 128 /* LBC SDRAM is 128MB */ |
9e3ed392 JH |
291 | |
292 | /* | |
11d5a629 | 293 | * Base Register 3 and Option Register 3 configure the 1st 1/2 SDRAM. |
6d0f6bcf | 294 | * The SDRAM base address, CONFIG_SYS_LBC_SDRAM_BASE, is 0xf0000000. |
9e3ed392 JH |
295 | * |
296 | * For BR3, need: | |
297 | * Base address of 0xf0000000 = BR[0:16] = 1111 0000 0000 0000 0 | |
298 | * port-size = 32-bits = BR2[19:20] = 11 | |
299 | * no parity checking = BR2[21:22] = 00 | |
300 | * SDRAM for MSEL = BR2[24:26] = 011 | |
301 | * Valid = BR[31] = 1 | |
302 | * | |
303 | * 0 4 8 12 16 20 24 28 | |
304 | * 1111 0000 0000 0000 0001 1000 0110 0001 = f0001861 | |
305 | * | |
306 | */ | |
307 | ||
6d0f6bcf | 308 | #define CONFIG_SYS_BR3_PRELIM 0xf0001861 |
9e3ed392 JH |
309 | |
310 | /* | |
11d5a629 | 311 | * The SDRAM size in MB, of 1/2 CONFIG_SYS_LBC_SDRAM_SIZE, is 64. |
9e3ed392 JH |
312 | * |
313 | * For OR3, need: | |
314 | * 64MB mask for AM, OR3[0:7] = 1111 1100 | |
315 | * XAM, OR3[17:18] = 11 | |
316 | * 10 columns OR3[19-21] = 011 | |
317 | * 12 rows OR3[23-25] = 011 | |
318 | * EAD set for extra time OR[31] = 0 | |
319 | * | |
320 | * 0 4 8 12 16 20 24 28 | |
321 | * 1111 1100 0000 0000 0110 1100 1100 0000 = fc006cc0 | |
322 | */ | |
323 | ||
6d0f6bcf | 324 | #define CONFIG_SYS_OR3_PRELIM 0xfc006cc0 |
9e3ed392 | 325 | |
11d5a629 PG |
326 | /* |
327 | * Base Register 4 and Option Register 4 configure the 2nd 1/2 SDRAM. | |
328 | * The base address, (SDRAM_BASE + 1/2*SIZE), is 0xf4000000. | |
329 | * | |
330 | * For BR4, need: | |
331 | * Base address of 0xf4000000 = BR[0:16] = 1111 0100 0000 0000 0 | |
332 | * port-size = 32-bits = BR2[19:20] = 11 | |
333 | * no parity checking = BR2[21:22] = 00 | |
334 | * SDRAM for MSEL = BR2[24:26] = 011 | |
335 | * Valid = BR[31] = 1 | |
336 | * | |
337 | * 0 4 8 12 16 20 24 28 | |
338 | * 1111 0000 0000 0000 0001 1000 0110 0001 = f4001861 | |
339 | * | |
340 | */ | |
341 | ||
342 | #define CONFIG_SYS_BR4_PRELIM 0xf4001861 | |
343 | ||
344 | /* | |
345 | * The SDRAM size in MB, of 1/2 CONFIG_SYS_LBC_SDRAM_SIZE, is 64. | |
346 | * | |
347 | * For OR4, need: | |
348 | * 64MB mask for AM, OR3[0:7] = 1111 1100 | |
349 | * XAM, OR3[17:18] = 11 | |
350 | * 10 columns OR3[19-21] = 011 | |
351 | * 12 rows OR3[23-25] = 011 | |
352 | * EAD set for extra time OR[31] = 0 | |
353 | * | |
354 | * 0 4 8 12 16 20 24 28 | |
355 | * 1111 1100 0000 0000 0110 1100 1100 0000 = fc006cc0 | |
356 | */ | |
357 | ||
358 | #define CONFIG_SYS_OR4_PRELIM 0xfc006cc0 | |
359 | ||
6d0f6bcf JCPV |
360 | #define CONFIG_SYS_LBC_LCRR 0x00000002 /* LB clock ratio reg */ |
361 | #define CONFIG_SYS_LBC_LBCR 0x00000000 /* LB config reg */ | |
362 | #define CONFIG_SYS_LBC_LSRT 0x20000000 /* LB sdram refresh timer */ | |
363 | #define CONFIG_SYS_LBC_MRTPR 0x00000000 /* LB refresh timer prescal*/ | |
9e3ed392 | 364 | |
9e3ed392 JH |
365 | /* |
366 | * Common settings for all Local Bus SDRAM commands. | |
9e3ed392 | 367 | */ |
b0fe93ed | 368 | #define CONFIG_SYS_LBC_LSDMR_COMMON ( LSDMR_RFCR16 \ |
5f4c6f0d PG |
369 | | LSDMR_BSMA1516 \ |
370 | | LSDMR_PRETOACT3 \ | |
371 | | LSDMR_ACTTORW3 \ | |
372 | | LSDMR_BUFCMD \ | |
b0fe93ed | 373 | | LSDMR_BL8 \ |
5f4c6f0d | 374 | | LSDMR_WRC2 \ |
b0fe93ed | 375 | | LSDMR_CL3 \ |
9e3ed392 JH |
376 | ) |
377 | ||
5f4c6f0d PG |
378 | #define CONFIG_SYS_LBC_LSDMR_PCHALL \ |
379 | (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_PCHALL) | |
380 | #define CONFIG_SYS_LBC_LSDMR_ARFRSH \ | |
381 | (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_ARFRSH) | |
382 | #define CONFIG_SYS_LBC_LSDMR_MRW \ | |
383 | (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_MRW) | |
384 | #define CONFIG_SYS_LBC_LSDMR_RFEN \ | |
385 | (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_RFEN) | |
386 | ||
6d0f6bcf JCPV |
387 | #define CONFIG_SYS_INIT_RAM_LOCK 1 |
388 | #define CONFIG_SYS_INIT_RAM_ADDR 0xe4010000 /* Initial RAM address */ | |
553f0982 | 389 | #define CONFIG_SYS_INIT_RAM_SIZE 0x4000 /* Size of used area in RAM */ |
9e3ed392 | 390 | |
6d0f6bcf | 391 | #define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000 /* relocate boot L2SRAM */ |
9e3ed392 | 392 | |
25ddd1fb | 393 | #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) |
6d0f6bcf | 394 | #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET |
9e3ed392 | 395 | |
dd9ca98f PG |
396 | /* |
397 | * For soldered on flash, (128kB/sector) we use 2 sectors for u-boot and | |
14d0a02a | 398 | * one for env+bootpg (CONFIG_SYS_TEXT_BASE=0xfffa_0000, 384kB total). For SODIMM |
dd9ca98f | 399 | * flash (512kB/sector) we use 1 sector for u-boot, and one for env+bootpg |
14d0a02a | 400 | * (CONFIG_SYS_TEXT_BASE=0xfff0_0000, 1MB total). This dynamically sets the right |
dd9ca98f PG |
401 | * thing for MONITOR_LEN in both cases. |
402 | */ | |
14d0a02a | 403 | #define CONFIG_SYS_MONITOR_LEN (~CONFIG_SYS_TEXT_BASE + 1) |
f0aec4ea | 404 | #define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc */ |
9e3ed392 JH |
405 | |
406 | /* Serial Port */ | |
407 | #define CONFIG_CONS_INDEX 1 | |
6d0f6bcf JCPV |
408 | #define CONFIG_SYS_NS16550_SERIAL |
409 | #define CONFIG_SYS_NS16550_REG_SIZE 1 | |
2738bc8d | 410 | #define CONFIG_SYS_NS16550_CLK (400000000 / CONFIG_SYS_CLK_DIV) |
9e3ed392 | 411 | |
6d0f6bcf | 412 | #define CONFIG_SYS_BAUDRATE_TABLE \ |
9e3ed392 JH |
413 | {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200} |
414 | ||
6d0f6bcf JCPV |
415 | #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500) |
416 | #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600) | |
9e3ed392 | 417 | |
9e3ed392 JH |
418 | /* |
419 | * I2C | |
420 | */ | |
00f792e0 HS |
421 | #define CONFIG_SYS_I2C |
422 | #define CONFIG_SYS_I2C_FSL | |
423 | #define CONFIG_SYS_FSL_I2C_SPEED 400000 | |
424 | #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F | |
425 | #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 | |
6d0f6bcf | 426 | #define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 |
9e3ed392 JH |
427 | |
428 | /* | |
429 | * General PCI | |
430 | * Memory space is mapped 1-1, but I/O space must start from 0. | |
431 | */ | |
fdc7eb90 | 432 | #define CONFIG_SYS_PCI_VIRT 0x80000000 /* 1G PCI TLB */ |
6d0f6bcf | 433 | #define CONFIG_SYS_PCI_PHYS 0x80000000 /* 1G PCI TLB */ |
9e3ed392 | 434 | |
fdc7eb90 PG |
435 | #define CONFIG_SYS_PCI1_MEM_VIRT 0x80000000 |
436 | #define CONFIG_SYS_PCI1_MEM_BUS 0x80000000 | |
437 | #define CONFIG_SYS_PCI1_MEM_PHYS 0x80000000 | |
6d0f6bcf | 438 | #define CONFIG_SYS_PCI1_MEM_SIZE 0x20000000 /* 512M */ |
fdc7eb90 PG |
439 | #define CONFIG_SYS_PCI1_IO_VIRT 0xe2000000 |
440 | #define CONFIG_SYS_PCI1_IO_BUS 0x00000000 | |
441 | #define CONFIG_SYS_PCI1_IO_PHYS 0xe2000000 | |
442 | #define CONFIG_SYS_PCI1_IO_SIZE 0x00800000 /* 8M */ | |
9e3ed392 JH |
443 | |
444 | #ifdef CONFIG_PCIE1 | |
fdc7eb90 PG |
445 | #define CONFIG_SYS_PCIE1_MEM_VIRT 0xa0000000 |
446 | #define CONFIG_SYS_PCIE1_MEM_BUS 0xa0000000 | |
447 | #define CONFIG_SYS_PCIE1_MEM_PHYS 0xa0000000 | |
6d0f6bcf | 448 | #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ |
fdc7eb90 PG |
449 | #define CONFIG_SYS_PCIE1_IO_VIRT 0xe2800000 |
450 | #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 | |
451 | #define CONFIG_SYS_PCIE1_IO_PHYS 0xe2800000 | |
452 | #define CONFIG_SYS_PCIE1_IO_SIZE 0x00800000 /* 8M */ | |
9e3ed392 JH |
453 | #endif |
454 | ||
455 | #ifdef CONFIG_RIO | |
456 | /* | |
457 | * RapidIO MMU | |
458 | */ | |
6d0f6bcf JCPV |
459 | #define CONFIG_SYS_RIO_MEM_BASE 0xC0000000 |
460 | #define CONFIG_SYS_RIO_MEM_SIZE 0x20000000 /* 512M */ | |
9e3ed392 JH |
461 | #endif |
462 | ||
9e3ed392 JH |
463 | #if defined(CONFIG_PCI) |
464 | ||
9e3ed392 JH |
465 | #define CONFIG_PCI_PNP /* do pci plug-and-play */ |
466 | ||
467 | #undef CONFIG_EEPRO100 | |
468 | #undef CONFIG_TULIP | |
469 | ||
fdc7eb90 | 470 | #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ |
9e3ed392 | 471 | |
9e3ed392 JH |
472 | #endif /* CONFIG_PCI */ |
473 | ||
9e3ed392 JH |
474 | #if defined(CONFIG_TSEC_ENET) |
475 | ||
9e3ed392 JH |
476 | #define CONFIG_MII 1 /* MII PHY management */ |
477 | #define CONFIG_TSEC1 1 | |
478 | #define CONFIG_TSEC1_NAME "eTSEC0" | |
479 | #define CONFIG_TSEC2 1 | |
480 | #define CONFIG_TSEC2_NAME "eTSEC1" | |
9e3ed392 JH |
481 | #undef CONFIG_MPC85XX_FEC |
482 | ||
58da8890 PG |
483 | #define TSEC1_PHY_ADDR 0x19 |
484 | #define TSEC2_PHY_ADDR 0x1a | |
9e3ed392 JH |
485 | |
486 | #define TSEC1_PHYIDX 0 | |
487 | #define TSEC2_PHYIDX 0 | |
bd93105f | 488 | |
9e3ed392 JH |
489 | #define TSEC1_FLAGS TSEC_GIGABIT |
490 | #define TSEC2_FLAGS TSEC_GIGABIT | |
9e3ed392 JH |
491 | |
492 | /* Options are: eTSEC[0-3] */ | |
493 | #define CONFIG_ETHPRIME "eTSEC0" | |
494 | #define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */ | |
495 | #endif /* CONFIG_TSEC_ENET */ | |
496 | ||
497 | /* | |
498 | * Environment | |
499 | */ | |
5a1aceb0 | 500 | #define CONFIG_ENV_IS_IN_FLASH 1 |
0e8d1586 | 501 | #define CONFIG_ENV_SIZE 0x2000 |
14d0a02a | 502 | #if CONFIG_SYS_TEXT_BASE == 0xfff00000 /* Boot from 64MB SODIMM */ |
dd9ca98f PG |
503 | #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + 0x80000) |
504 | #define CONFIG_ENV_SECT_SIZE 0x80000 /* 512K(one sector) for env */ | |
14d0a02a | 505 | #elif CONFIG_SYS_TEXT_BASE == 0xfffa0000 /* Boot from 8MB soldered flash */ |
dd9ca98f PG |
506 | #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + 0x40000) |
507 | #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K(one sector) for env */ | |
508 | #else | |
509 | #warning undefined environment size/location. | |
510 | #endif | |
9e3ed392 JH |
511 | |
512 | #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ | |
6d0f6bcf | 513 | #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ |
9e3ed392 JH |
514 | |
515 | /* | |
516 | * BOOTP options | |
517 | */ | |
518 | #define CONFIG_BOOTP_BOOTFILESIZE | |
519 | #define CONFIG_BOOTP_BOOTPATH | |
520 | #define CONFIG_BOOTP_GATEWAY | |
521 | #define CONFIG_BOOTP_HOSTNAME | |
522 | ||
9e3ed392 JH |
523 | /* |
524 | * Command line configuration. | |
525 | */ | |
199e262e | 526 | #define CONFIG_CMD_REGINFO |
9e3ed392 JH |
527 | |
528 | #if defined(CONFIG_PCI) | |
529 | #define CONFIG_CMD_PCI | |
530 | #endif | |
531 | ||
9e3ed392 JH |
532 | #undef CONFIG_WATCHDOG /* watchdog disabled */ |
533 | ||
534 | /* | |
535 | * Miscellaneous configurable options | |
536 | */ | |
ad22f927 | 537 | #define CONFIG_CMDLINE_EDITING /* undef to save memory */ |
5be58f5f | 538 | #define CONFIG_AUTO_COMPLETE /* add autocompletion support */ |
6d0f6bcf JCPV |
539 | #define CONFIG_SYS_LONGHELP /* undef to save memory */ |
540 | #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ | |
9e3ed392 | 541 | #if defined(CONFIG_CMD_KGDB) |
6d0f6bcf | 542 | #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ |
9e3ed392 | 543 | #else |
6d0f6bcf | 544 | #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ |
9e3ed392 | 545 | #endif |
6d0f6bcf JCPV |
546 | #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ |
547 | #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ | |
548 | #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ | |
9e3ed392 JH |
549 | |
550 | /* | |
551 | * For booting Linux, the board info and command line data | |
552 | * have to be in the first 8 MB of memory, since this is | |
553 | * the maximum mapped by the Linux kernel during initialization. | |
554 | */ | |
6d0f6bcf | 555 | #define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux*/ |
9e3ed392 | 556 | |
9e3ed392 JH |
557 | #if defined(CONFIG_CMD_KGDB) |
558 | #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ | |
9e3ed392 JH |
559 | #endif |
560 | ||
561 | /* | |
562 | * Environment Configuration | |
563 | */ | |
9e3ed392 JH |
564 | #if defined(CONFIG_TSEC_ENET) |
565 | #define CONFIG_HAS_ETH0 | |
9e3ed392 | 566 | #define CONFIG_HAS_ETH1 |
9e3ed392 JH |
567 | #endif |
568 | ||
569 | #define CONFIG_IPADDR 192.168.0.55 | |
570 | ||
571 | #define CONFIG_HOSTNAME sbc8548 | |
8b3637c6 | 572 | #define CONFIG_ROOTPATH "/opt/eldk/ppc_85xx" |
b3f44c21 | 573 | #define CONFIG_BOOTFILE "/uImage" |
9e3ed392 JH |
574 | #define CONFIG_UBOOTPATH /u-boot.bin /* TFTP server */ |
575 | ||
576 | #define CONFIG_SERVERIP 192.168.0.2 | |
577 | #define CONFIG_GATEWAYIP 192.168.0.1 | |
578 | #define CONFIG_NETMASK 255.255.255.0 | |
579 | ||
580 | #define CONFIG_LOADADDR 1000000 /*default location for tftp and bootm*/ | |
581 | ||
9e3ed392 JH |
582 | #undef CONFIG_BOOTARGS /* the boot command will set bootargs*/ |
583 | ||
584 | #define CONFIG_BAUDRATE 115200 | |
585 | ||
586 | #define CONFIG_EXTRA_ENV_SETTINGS \ | |
5368c55d MV |
587 | "netdev=eth0\0" \ |
588 | "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ | |
589 | "tftpflash=tftpboot $loadaddr $uboot; " \ | |
590 | "protect off " __stringify(CONFIG_SYS_TEXT_BASE) " +$filesize; " \ | |
591 | "erase " __stringify(CONFIG_SYS_TEXT_BASE) " +$filesize; " \ | |
592 | "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) " $filesize; " \ | |
593 | "protect on " __stringify(CONFIG_SYS_TEXT_BASE) " +$filesize; " \ | |
594 | "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) " $filesize\0" \ | |
595 | "consoledev=ttyS0\0" \ | |
596 | "ramdiskaddr=2000000\0" \ | |
597 | "ramdiskfile=uRamdisk\0" \ | |
598 | "fdtaddr=c00000\0" \ | |
599 | "fdtfile=sbc8548.dtb\0" | |
9e3ed392 JH |
600 | |
601 | #define CONFIG_NFSBOOTCOMMAND \ | |
602 | "setenv bootargs root=/dev/nfs rw " \ | |
603 | "nfsroot=$serverip:$rootpath " \ | |
604 | "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ | |
605 | "console=$consoledev,$baudrate $othbootargs;" \ | |
606 | "tftp $loadaddr $bootfile;" \ | |
607 | "tftp $fdtaddr $fdtfile;" \ | |
608 | "bootm $loadaddr - $fdtaddr" | |
609 | ||
9e3ed392 JH |
610 | #define CONFIG_RAMBOOTCOMMAND \ |
611 | "setenv bootargs root=/dev/ram rw " \ | |
612 | "console=$consoledev,$baudrate $othbootargs;" \ | |
613 | "tftp $ramdiskaddr $ramdiskfile;" \ | |
614 | "tftp $loadaddr $bootfile;" \ | |
615 | "tftp $fdtaddr $fdtfile;" \ | |
616 | "bootm $loadaddr $ramdiskaddr $fdtaddr" | |
617 | ||
618 | #define CONFIG_BOOTCOMMAND CONFIG_RAMBOOTCOMMAND | |
619 | ||
620 | #endif /* __CONFIG_H */ |