projects / people / ms / u-boot.git / blame
| Commit | Line | Data |
|---|---|---|
| 887e2ec9 | 1 | /* |
| fc84a849 | 2 | * (C) Copyright 2006-2008 |
| 887e2ec9 SR |
3 | * Stefan Roese, DENX Software Engineering, sr@denx.de. |
| 4 | * | |
| 5 | * (C) Copyright 2006 | |
| 6 | * Jacqueline Pira-Ferriol, AMCC/IBM, jpira-ferriol@fr.ibm.com | |
| 7 | * Alain Saurel, AMCC/IBM, alain.saurel@fr.ibm.com | |
| 8 | * | |
| 9 | * This program is free software; you can redistribute it and/or | |
| 10 | * modify it under the terms of the GNU General Public License as | |
| 11 | * published by the Free Software Foundation; either version 2 of | |
| 12 | * the License, or (at your option) any later version. | |
| 13 | * | |
| 14 | * This program is distributed in the hope that it will be useful, | |
| 15 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
| 16 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
| 17 | * GNU General Public License for more details. | |
| 18 | * | |
| 19 | * You should have received a copy of the GNU General Public License | |
| 20 | * along with this program; if not, write to the Free Software | |
| 21 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | |
| 22 | * MA 02111-1307 USA | |
| 23 | */ | |
| 24 | ||
| 214398d9 | 25 | /* |
| e802594b | 26 | * sequoia.h - configuration for Sequoia & Rainier boards |
| 214398d9 | 27 | */ |
| 887e2ec9 SR |
28 | #ifndef __CONFIG_H |
| 29 | #define __CONFIG_H | |
| 30 | ||
| 214398d9 | 31 | /* |
| 887e2ec9 | 32 | * High Level Configuration Options |
| 214398d9 | 33 | */ |
| e802594b | 34 | /* This config file is used for Sequoia (440EPx) and Rainier (440GRx) */ |
| 854bc8da | 35 | #ifndef CONFIG_RAINIER |
| 214398d9 | 36 | #define CONFIG_440EPX 1 /* Specific PPC440EPx */ |
| 72675dc6 | 37 | #define CONFIG_HOSTNAME sequoia |
| 854bc8da | 38 | #else |
| 214398d9 | 39 | #define CONFIG_440GRX 1 /* Specific PPC440GRx */ |
| 72675dc6 | 40 | #define CONFIG_HOSTNAME rainier |
| 854bc8da | 41 | #endif |
| 214398d9 LJ |
42 | #define CONFIG_440 1 /* ... PPC440 family */ |
| 43 | #define CONFIG_4xx 1 /* ... PPC4xx family */ | |
| 72675dc6 SR |
44 | |
| 45 | /* | |
| 46 | * Include common defines/options for all AMCC eval boards | |
| 47 | */ | |
| 48 | #include "amcc-common.h" | |
| 49 | ||
| e3b8c78b | 50 | /* Detect Sequoia PLL input clock automatically via CPLD bit */ |
| 6d0f6bcf | 51 | #define CONFIG_SYS_CLK_FREQ ((in8(CONFIG_SYS_BCSR_BASE + 3) & 0x80) ? \ |
| 193b4a3b | 52 | 33333333 : 33000000) |
| 887e2ec9 | 53 | |
| bc778812 AG |
54 | /* |
| 55 | * Define this if you want support for video console with radeon 9200 pci card | |
| 56 | * Also set TEXT_BASE to 0xFFF80000 in board/amcc/sequoia/config.mk in this case | |
| 57 | */ | |
| 58 | #undef CONFIG_VIDEO | |
| 59 | ||
| 60 | #ifdef CONFIG_VIDEO | |
| d25dfe08 SR |
61 | /* |
| 62 | * 44x dcache supported is working now on sequoia, but we don't enable | |
| 63 | * it yet since it needs further testing | |
| 64 | */ | |
| 214398d9 | 65 | #define CONFIG_4xx_DCACHE /* enable dcache */ |
| d25dfe08 SR |
66 | #endif |
| 67 | ||
| 214398d9 LJ |
68 | #define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */ |
| 69 | #define CONFIG_MISC_INIT_R 1 /* Call misc_init_r */ | |
| 887e2ec9 | 70 | |
| 214398d9 LJ |
71 | /* |
| 72 | * Base addresses -- Note these are effective addresses where the actual | |
| 73 | * resources get mapped (not physical addresses). | |
| 74 | */ | |
| 6d0f6bcf JCPV |
75 | #define CONFIG_SYS_TLB_FOR_BOOT_FLASH 0x0003 |
| 76 | #define CONFIG_SYS_BOOT_BASE_ADDR 0xf0000000 | |
| 77 | #define CONFIG_SYS_FLASH_BASE 0xfc000000 /* start of FLASH */ | |
| 78 | #define CONFIG_SYS_NAND_ADDR 0xd0000000 /* NAND Flash */ | |
| 79 | #define CONFIG_SYS_OCM_BASE 0xe0010000 /* ocm */ | |
| 80 | #define CONFIG_SYS_OCM_DATA_ADDR CONFIG_SYS_OCM_BASE | |
| 81 | #define CONFIG_SYS_PCI_BASE 0xe0000000 /* Internal PCI regs */ | |
| 82 | #define CONFIG_SYS_PCI_MEMBASE 0x80000000 /* mapped pci memory */ | |
| 83 | #define CONFIG_SYS_PCI_MEMBASE1 CONFIG_SYS_PCI_MEMBASE + 0x10000000 | |
| 84 | #define CONFIG_SYS_PCI_MEMBASE2 CONFIG_SYS_PCI_MEMBASE1 + 0x10000000 | |
| 85 | #define CONFIG_SYS_PCI_MEMBASE3 CONFIG_SYS_PCI_MEMBASE2 + 0x10000000 | |
| 887e2ec9 | 86 | |
| 6d0f6bcf JCPV |
87 | #define CONFIG_SYS_USB2D0_BASE 0xe0000100 |
| 88 | #define CONFIG_SYS_USB_DEVICE 0xe0000000 | |
| 89 | #define CONFIG_SYS_USB_HOST 0xe0000400 | |
| 90 | #define CONFIG_SYS_BCSR_BASE 0xc0000000 | |
| 887e2ec9 | 91 | |
| 214398d9 | 92 | /* |
| 887e2ec9 | 93 | * Initial RAM & stack pointer |
| 214398d9 | 94 | */ |
| 887e2ec9 | 95 | /* 440EPx/440GRx have 16KB of internal SRAM, so no need for D-Cache */ |
| 6d0f6bcf JCPV |
96 | #define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_OCM_BASE /* OCM */ |
| 97 | #define CONFIG_SYS_INIT_RAM_END (4 << 10) | |
| 98 | #define CONFIG_SYS_GBL_DATA_SIZE 256 /* num bytes initial data */ | |
| 99 | #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE) | |
| 800eb096 | 100 | #define CONFIG_SYS_INIT_SP_OFFSET (CONFIG_SYS_GBL_DATA_OFFSET - 0x4) |
| 887e2ec9 | 101 | |
| 214398d9 | 102 | /* |
| 887e2ec9 | 103 | * Serial Port |
| 214398d9 | 104 | */ |
| 550650dd | 105 | #define CONFIG_CONS_INDEX 1 /* Use UART0 */ |
| 6d0f6bcf | 106 | #define CONFIG_SYS_EXT_SERIAL_CLOCK 11059200 /* ext. 11.059MHz clk */ |
| 887e2ec9 | 107 | |
| 214398d9 | 108 | /* |
| 887e2ec9 | 109 | * Environment |
| 214398d9 | 110 | */ |
| d873133f SR |
111 | #if defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL) |
| 112 | #define CONFIG_ENV_IS_IN_NAND /* use NAND for environ vars */ | |
| 113 | #define CONFIG_ENV_IS_EMBEDDED /* use embedded environment */ | |
| 114 | #elif defined(CONFIG_SYS_RAMBOOT) | |
| 115 | #define CONFIG_ENV_IS_NOWHERE /* Store env in memory only */ | |
| 116 | #define CONFIG_ENV_SIZE (8 << 10) | |
| 117 | /* | |
| 118 | * In RAM-booting version, we have no environment storage. So we need to | |
| 119 | * provide at least preliminary MAC addresses for the 4xx EMAC driver to | |
| 120 | * register the interfaces. Those two addresses are generated via the | |
| 121 | * tools/gen_eth_addr tool and should only be used in a closed laboratory | |
| 122 | * environment. | |
| 123 | */ | |
| 124 | #define CONFIG_ETHADDR 4a:56:49:22:3e:43 | |
| 125 | #define CONFIG_ETH1ADDR 02:93:53:d5:06:98 | |
| 887e2ec9 | 126 | #else |
| d873133f | 127 | #define CONFIG_ENV_IS_IN_FLASH /* use FLASH for environ vars */ |
| 887e2ec9 | 128 | #endif |
| 887e2ec9 | 129 | |
| d873133f | 130 | #if defined(CONFIG_CMD_FLASH) |
| 214398d9 | 131 | /* |
| 887e2ec9 | 132 | * FLASH related |
| 214398d9 | 133 | */ |
| 6d0f6bcf | 134 | #define CONFIG_SYS_FLASH_CFI /* The flash is CFI compatible */ |
| 00b1883a | 135 | #define CONFIG_FLASH_CFI_DRIVER /* Use common CFI driver */ |
| 887e2ec9 | 136 | |
| 6d0f6bcf | 137 | #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE } |
| 887e2ec9 | 138 | |
| 6d0f6bcf JCPV |
139 | #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ |
| 140 | #define CONFIG_SYS_MAX_FLASH_SECT 512 /* max number of sectors on one chip */ | |
| 887e2ec9 | 141 | |
| 6d0f6bcf JCPV |
142 | #define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ |
| 143 | #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ | |
| 887e2ec9 | 144 | |
| 6d0f6bcf JCPV |
145 | #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 /* use buffered writes (20x faster) */ |
| 146 | #define CONFIG_SYS_FLASH_PROTECTION 1 /* use hardware flash protection */ | |
| 887e2ec9 | 147 | |
| 6d0f6bcf JCPV |
148 | #define CONFIG_SYS_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */ |
| 149 | #define CONFIG_SYS_FLASH_QUIET_TEST 1 /* don't warn upon unknown flash */ | |
| 887e2ec9 | 150 | |
| 5a1aceb0 | 151 | #ifdef CONFIG_ENV_IS_IN_FLASH |
| 0e8d1586 | 152 | #define CONFIG_ENV_SECT_SIZE 0x20000 /* size of one complete sector */ |
| 6d0f6bcf | 153 | #define CONFIG_ENV_ADDR ((-CONFIG_SYS_MONITOR_LEN)-CONFIG_ENV_SECT_SIZE) |
| 0e8d1586 | 154 | #define CONFIG_ENV_SIZE 0x2000 /* Total Size of Environment Sector */ |
| 887e2ec9 SR |
155 | |
| 156 | /* Address and size of Redundant Environment Sector */ | |
| 0e8d1586 JCPV |
157 | #define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR-CONFIG_ENV_SECT_SIZE) |
| 158 | #define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE) | |
| 887e2ec9 | 159 | #endif |
| d873133f | 160 | #endif /* CONFIG_CMD_FLASH */ |
| 887e2ec9 | 161 | |
| 887e2ec9 SR |
162 | /* |
| 163 | * IPL (Initial Program Loader, integrated inside CPU) | |
| 164 | * Will load first 4k from NAND (SPL) into cache and execute it from there. | |
| 165 | * | |
| 166 | * SPL (Secondary Program Loader) | |
| 167 | * Will load special U-Boot version (NUB) from NAND and execute it. This SPL | |
| 168 | * has to fit into 4kByte. It sets up the CPU and configures the SDRAM | |
| 169 | * controller and the NAND controller so that the special U-Boot image can be | |
| 170 | * loaded from NAND to SDRAM. | |
| 171 | * | |
| 172 | * NUB (NAND U-Boot) | |
| 173 | * This NAND U-Boot (NUB) is a special U-Boot version which can be started | |
| 174 | * from RAM. Therefore it mustn't (re-)configure the SDRAM controller. | |
| 175 | * | |
| 176 | * On 440EPx the SPL is copied to SDRAM before the NAND controller is | |
| 177 | * set up. While still running from cache, I experienced problems accessing | |
| 178 | * the NAND controller. sr - 2006-08-25 | |
| 179 | */ | |
| 6d0f6bcf JCPV |
180 | #define CONFIG_SYS_NAND_BOOT_SPL_SRC 0xfffff000 /* SPL location */ |
| 181 | #define CONFIG_SYS_NAND_BOOT_SPL_SIZE (4 << 10) /* SPL size */ | |
| 182 | #define CONFIG_SYS_NAND_BOOT_SPL_DST (CONFIG_SYS_OCM_BASE + (12 << 10)) /* Copy SPL here */ | |
| 183 | #define CONFIG_SYS_NAND_U_BOOT_DST 0x01000000 /* Load NUB to this addr */ | |
| 184 | #define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_NAND_U_BOOT_DST /* Start NUB from */ | |
| 214398d9 | 185 | /* this addr */ |
| 6d0f6bcf | 186 | #define CONFIG_SYS_NAND_BOOT_SPL_DELTA (CONFIG_SYS_NAND_BOOT_SPL_SRC - CONFIG_SYS_NAND_BOOT_SPL_DST) |
| 887e2ec9 SR |
187 | |
| 188 | /* | |
| 189 | * Define the partitioning of the NAND chip (only RAM U-Boot is needed here) | |
| 190 | */ | |
| 6d0f6bcf JCPV |
191 | #define CONFIG_SYS_NAND_U_BOOT_OFFS (16 << 10) /* Offset to RAM U-Boot image */ |
| 192 | #define CONFIG_SYS_NAND_U_BOOT_SIZE (512 << 10) /* Size of RAM U-Boot image */ | |
| 887e2ec9 SR |
193 | |
| 194 | /* | |
| 195 | * Now the NAND chip has to be defined (no autodetection used!) | |
| 196 | */ | |
| 6d0f6bcf JCPV |
197 | #define CONFIG_SYS_NAND_PAGE_SIZE 512 /* NAND chip page size */ |
| 198 | #define CONFIG_SYS_NAND_BLOCK_SIZE (16 << 10) /* NAND chip block size */ | |
| 199 | #define CONFIG_SYS_NAND_PAGE_COUNT 32 /* NAND chip page count */ | |
| 200 | #define CONFIG_SYS_NAND_BAD_BLOCK_POS 5 /* Location of bad block marker */ | |
| 201 | #undef CONFIG_SYS_NAND_4_ADDR_CYCLE /* No fourth addr used (<=32MB) */ | |
| 202 | ||
| 203 | #define CONFIG_SYS_NAND_ECCSIZE 256 | |
| 204 | #define CONFIG_SYS_NAND_ECCBYTES 3 | |
| 205 | #define CONFIG_SYS_NAND_ECCSTEPS (CONFIG_SYS_NAND_PAGE_SIZE / CONFIG_SYS_NAND_ECCSIZE) | |
| 206 | #define CONFIG_SYS_NAND_OOBSIZE 16 | |
| 207 | #define CONFIG_SYS_NAND_ECCTOTAL (CONFIG_SYS_NAND_ECCBYTES * CONFIG_SYS_NAND_ECCSTEPS) | |
| 208 | #define CONFIG_SYS_NAND_ECCPOS {0, 1, 2, 3, 6, 7} | |
| 9d909604 | 209 | |
| 51bfee19 | 210 | #ifdef CONFIG_ENV_IS_IN_NAND |
| d12ae808 SR |
211 | /* |
| 212 | * For NAND booting the environment is embedded in the U-Boot image. Please take | |
| 213 | * look at the file board/amcc/sequoia/u-boot-nand.lds for details. | |
| 214 | */ | |
| 6d0f6bcf JCPV |
215 | #define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE |
| 216 | #define CONFIG_ENV_OFFSET (CONFIG_SYS_NAND_U_BOOT_OFFS + CONFIG_ENV_SIZE) | |
| 0e8d1586 | 217 | #define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE) |
| 887e2ec9 SR |
218 | #endif |
| 219 | ||
| 214398d9 | 220 | /* |
| 887e2ec9 | 221 | * DDR SDRAM |
| 214398d9 | 222 | */ |
| 6d0f6bcf | 223 | #define CONFIG_SYS_MBYTES_SDRAM (256) /* 256MB */ |
| d873133f SR |
224 | #if !defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL) && \ |
| 225 | !defined(CONFIG_SYS_RAMBOOT) | |
| 214398d9 | 226 | #define CONFIG_DDR_DATA_EYE /* use DDR2 optimization */ |
| 02388983 | 227 | #endif |
| 6d0f6bcf | 228 | #define CONFIG_SYS_MEM_TOP_HIDE (4 << 10) /* don't use last 4kbytes */ |
| 14f73ca6 | 229 | /* 440EPx errata CHIP 11 */ |
| 887e2ec9 | 230 | |
| 214398d9 | 231 | /* |
| 887e2ec9 | 232 | * I2C |
| 214398d9 | 233 | */ |
| 6d0f6bcf | 234 | #define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */ |
| 887e2ec9 | 235 | |
| 6d0f6bcf JCPV |
236 | #define CONFIG_SYS_I2C_MULTI_EEPROMS |
| 237 | #define CONFIG_SYS_I2C_EEPROM_ADDR (0xa8>>1) | |
| 238 | #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 | |
| 239 | #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 | |
| 240 | #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 | |
| 887e2ec9 | 241 | |
| cfc25874 SR |
242 | /* I2C bootstrap EEPROM */ |
| 243 | #define CONFIG_4xx_CONFIG_I2C_EEPROM_ADDR 0x52 | |
| 244 | #define CONFIG_4xx_CONFIG_I2C_EEPROM_OFFSET 0 | |
| 245 | #define CONFIG_4xx_CONFIG_BLOCKSIZE 16 | |
| 246 | ||
| 887e2ec9 | 247 | /* I2C SYSMON (LM75, AD7414 is almost compatible) */ |
| 214398d9 LJ |
248 | #define CONFIG_DTT_LM75 1 /* ON Semi's LM75 */ |
| 249 | #define CONFIG_DTT_AD7414 1 /* use AD7414 */ | |
| 250 | #define CONFIG_DTT_SENSORS {0} /* Sensor addresses */ | |
| 6d0f6bcf JCPV |
251 | #define CONFIG_SYS_DTT_MAX_TEMP 70 |
| 252 | #define CONFIG_SYS_DTT_LOW_TEMP -30 | |
| 253 | #define CONFIG_SYS_DTT_HYSTERESIS 3 | |
| 887e2ec9 | 254 | |
| 72675dc6 SR |
255 | /* |
| 256 | * Default environment variables | |
| 257 | */ | |
| 887e2ec9 | 258 | #define CONFIG_EXTRA_ENV_SETTINGS \ |
| 72675dc6 SR |
259 | CONFIG_AMCC_DEF_ENV \ |
| 260 | CONFIG_AMCC_DEF_ENV_POWERPC \ | |
| 261 | CONFIG_AMCC_DEF_ENV_PPC_OLD \ | |
| 262 | CONFIG_AMCC_DEF_ENV_NOR_UPD \ | |
| 263 | CONFIG_AMCC_DEF_ENV_NAND_UPD \ | |
| 4ef62514 SR |
264 | "kernel_addr=FC000000\0" \ |
| 265 | "ramdisk_addr=FC180000\0" \ | |
| 887e2ec9 | 266 | "" |
| 887e2ec9 SR |
267 | |
| 268 | #define CONFIG_M88E1111_PHY 1 | |
| 269 | #define CONFIG_IBM_EMAC4_V4 1 | |
| 887e2ec9 SR |
270 | #define CONFIG_PHY_ADDR 0 /* PHY address, See schematics */ |
| 271 | ||
| 214398d9 | 272 | #define CONFIG_PHY_RESET 1 /* reset phy upon startup */ |
| 887e2ec9 SR |
273 | #define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */ |
| 274 | ||
| 275 | #define CONFIG_HAS_ETH0 | |
| 887e2ec9 SR |
276 | #define CONFIG_HAS_ETH1 1 /* add support for "eth1addr" */ |
| 277 | #define CONFIG_PHY1_ADDR 1 | |
| 278 | ||
| 279 | /* USB */ | |
| 854bc8da | 280 | #ifdef CONFIG_440EPX |
| 559e2c87 CZ |
281 | |
| 282 | #undef CONFIG_USB_EHCI /* OHCI by default */ | |
| 283 | ||
| 284 | #ifdef CONFIG_USB_EHCI | |
| 285 | #define CONFIG_USB_EHCI_PPC4XX | |
| 286 | #define CONFIG_SYS_PPC4XX_USB_ADDR 0xe0000300 | |
| 287 | #define CONFIG_EHCI_HCD_INIT_AFTER_RESET | |
| 288 | #define CONFIG_EHCI_MMIO_BIG_ENDIAN | |
| 289 | #define CONFIG_EHCI_DESC_BIG_ENDIAN | |
| 290 | #ifdef CONFIG_4xx_DCACHE | |
| 291 | #define CONFIG_EHCI_DCACHE | |
| 292 | #endif | |
| 293 | #else /* CONFIG_USB_EHCI */ | |
| 2d146843 | 294 | #define CONFIG_USB_OHCI_NEW |
| 6d0f6bcf | 295 | #define CONFIG_SYS_OHCI_BE_CONTROLLER |
| 2d146843 | 296 | |
| 6d0f6bcf JCPV |
297 | #undef CONFIG_SYS_USB_OHCI_BOARD_INIT |
| 298 | #define CONFIG_SYS_USB_OHCI_CPU_INIT 1 | |
| 299 | #define CONFIG_SYS_USB_OHCI_REGS_BASE CONFIG_SYS_USB_HOST | |
| 300 | #define CONFIG_SYS_USB_OHCI_SLOT_NAME "ppc440" | |
| 301 | #define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 15 | |
| 559e2c87 | 302 | #endif |
| 887e2ec9 | 303 | |
| 559e2c87 | 304 | #define CONFIG_USB_STORAGE |
| 887e2ec9 SR |
305 | /* Comment this out to enable USB 1.1 device */ |
| 306 | #define USB_2_0_DEVICE | |
| 307 | ||
| 854bc8da SR |
308 | #endif /* CONFIG_440EPX */ |
| 309 | ||
| 887e2ec9 SR |
310 | /* Partitions */ |
| 311 | #define CONFIG_MAC_PARTITION | |
| 312 | #define CONFIG_DOS_PARTITION | |
| 313 | #define CONFIG_ISO_PARTITION | |
| 314 | ||
| 079a136c | 315 | /* |
| 72675dc6 | 316 | * Commands additional to the ones defined in amcc-common.h |
| 079a136c | 317 | */ |
| cfc25874 | 318 | #define CONFIG_CMD_CHIP_CONFIG |
| 46da1e96 | 319 | #define CONFIG_CMD_DTT |
| 46da1e96 | 320 | #define CONFIG_CMD_FAT |
| 46da1e96 | 321 | #define CONFIG_CMD_NAND |
| 46da1e96 | 322 | #define CONFIG_CMD_PCI |
| 46da1e96 JL |
323 | #define CONFIG_CMD_SDRAM |
| 324 | ||
| 325 | #ifdef CONFIG_440EPX | |
| 326 | #define CONFIG_CMD_USB | |
| 327 | #endif | |
| 328 | ||
| 9de469bd | 329 | #ifndef CONFIG_RAINIER |
| 6d0f6bcf | 330 | #define CONFIG_SYS_POST_FPU_ON CONFIG_SYS_POST_FPU |
| 9de469bd | 331 | #else |
| 6d0f6bcf | 332 | #define CONFIG_SYS_POST_FPU_ON 0 |
| 9de469bd | 333 | #endif |
| 887e2ec9 | 334 | |
| 9a929170 SR |
335 | /* |
| 336 | * Don't run the memory POST on the NAND-booting version. It will | |
| 337 | * overwrite part of the U-Boot image which is already loaded from NAND | |
| 338 | * to SDRAM. | |
| 339 | */ | |
| d873133f | 340 | #if defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_SYS_RAMBOOT) |
| 9a929170 SR |
341 | #define CONFIG_SYS_POST_MEMORY_ON 0 |
| 342 | #else | |
| 343 | #define CONFIG_SYS_POST_MEMORY_ON CONFIG_SYS_POST_MEMORY | |
| 344 | #endif | |
| 345 | ||
| a11e0696 | 346 | /* POST support */ |
| 6d0f6bcf JCPV |
347 | #define CONFIG_POST (CONFIG_SYS_POST_CACHE | \ |
| 348 | CONFIG_SYS_POST_CPU | \ | |
| 349 | CONFIG_SYS_POST_ETHER | \ | |
| 9a929170 | 350 | CONFIG_SYS_POST_FPU_ON | \ |
| 6d0f6bcf | 351 | CONFIG_SYS_POST_I2C | \ |
| 9a929170 | 352 | CONFIG_SYS_POST_MEMORY_ON | \ |
| 6d0f6bcf JCPV |
353 | CONFIG_SYS_POST_SPR | \ |
| 354 | CONFIG_SYS_POST_UART) | |
| 355 | ||
| a11e0696 | 356 | #define CONFIG_LOGBUFFER |
| 6d0f6bcf | 357 | #define CONFIG_SYS_POST_CACHE_ADDR 0x7fff0000 /* free virtual address */ |
| a11e0696 | 358 | |
| 6d0f6bcf | 359 | #define CONFIG_SYS_CONSOLE_IS_IN_ENV /* Otherwise it catches logbuffer as output */ |
| a11e0696 | 360 | |
| 887e2ec9 SR |
361 | #define CONFIG_SUPPORT_VFAT |
| 362 | ||
| 214398d9 | 363 | /* |
| 887e2ec9 | 364 | * PCI stuff |
| 214398d9 | 365 | */ |
| 887e2ec9 | 366 | /* General PCI */ |
| 214398d9 LJ |
367 | #define CONFIG_PCI /* include pci support */ |
| 368 | #define CONFIG_PCI_PNP /* do pci plug-and-play */ | |
| 6d0f6bcf | 369 | #define CONFIG_SYS_PCI_CACHE_LINE_SIZE 0 /* to avoid problems with PNP */ |
| 214398d9 | 370 | #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ |
| 6d0f6bcf JCPV |
371 | #define CONFIG_SYS_PCI_TARGBASE 0x80000000 /* PCIaddr mapped to */ |
| 372 | /* CONFIG_SYS_PCI_MEMBASE */ | |
| 887e2ec9 | 373 | /* Board-specific PCI */ |
| 6d0f6bcf JCPV |
374 | #define CONFIG_SYS_PCI_TARGET_INIT |
| 375 | #define CONFIG_SYS_PCI_MASTER_INIT | |
| a760b020 | 376 | #define CONFIG_SYS_PCI_BOARD_FIXUP_IRQ |
| 887e2ec9 | 377 | |
| 6d0f6bcf JCPV |
378 | #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x10e8 /* AMCC */ |
| 379 | #define CONFIG_SYS_PCI_SUBSYS_ID 0xcafe /* Whatever */ | |
| 887e2ec9 | 380 | |
| 214398d9 | 381 | /* |
| 887e2ec9 | 382 | * External Bus Controller (EBC) Setup |
| 214398d9 | 383 | */ |
| 887e2ec9 SR |
384 | |
| 385 | /* | |
| 386 | * On Sequoia CS0 and CS3 are switched when configuring for NAND booting | |
| 387 | */ | |
| d873133f SR |
388 | #if !defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL) && \ |
| 389 | !defined(CONFIG_SYS_RAMBOOT) | |
| 6d0f6bcf | 390 | #define CONFIG_SYS_NAND_CS 3 /* NAND chip connected to CSx */ |
| 214398d9 | 391 | /* Memory Bank 0 (NOR-FLASH) initialization */ |
| 6d0f6bcf JCPV |
392 | #define CONFIG_SYS_EBC_PB0AP 0x03017200 |
| 393 | #define CONFIG_SYS_EBC_PB0CR (CONFIG_SYS_FLASH_BASE | 0xda000) | |
| 887e2ec9 | 394 | |
| 214398d9 | 395 | /* Memory Bank 3 (NAND-FLASH) initialization */ |
| 6d0f6bcf JCPV |
396 | #define CONFIG_SYS_EBC_PB3AP 0x018003c0 |
| 397 | #define CONFIG_SYS_EBC_PB3CR (CONFIG_SYS_NAND_ADDR | 0x1c000) | |
| 887e2ec9 | 398 | #else |
| 6d0f6bcf | 399 | #define CONFIG_SYS_NAND_CS 0 /* NAND chip connected to CSx */ |
| 214398d9 | 400 | /* Memory Bank 3 (NOR-FLASH) initialization */ |
| 6d0f6bcf JCPV |
401 | #define CONFIG_SYS_EBC_PB3AP 0x03017200 |
| 402 | #define CONFIG_SYS_EBC_PB3CR (CONFIG_SYS_FLASH_BASE | 0xda000) | |
| 887e2ec9 | 403 | |
| 214398d9 | 404 | /* Memory Bank 0 (NAND-FLASH) initialization */ |
| 6d0f6bcf JCPV |
405 | #define CONFIG_SYS_EBC_PB0AP 0x018003c0 |
| 406 | #define CONFIG_SYS_EBC_PB0CR (CONFIG_SYS_NAND_ADDR | 0x1c000) | |
| 887e2ec9 SR |
407 | #endif |
| 408 | ||
| 214398d9 | 409 | /* Memory Bank 2 (CPLD) initialization */ |
| 6d0f6bcf JCPV |
410 | #define CONFIG_SYS_EBC_PB2AP 0x24814580 |
| 411 | #define CONFIG_SYS_EBC_PB2CR (CONFIG_SYS_BCSR_BASE | 0x38000) | |
| 887e2ec9 | 412 | |
| 6d0f6bcf | 413 | #define CONFIG_SYS_BCSR5_PCI66EN 0x80 |
| 5a5958b7 | 414 | |
| 214398d9 | 415 | /* |
| 43a2b0e7 | 416 | * NAND FLASH |
| 214398d9 | 417 | */ |
| 6d0f6bcf | 418 | #define CONFIG_SYS_MAX_NAND_DEVICE 1 |
| 6d0f6bcf JCPV |
419 | #define CONFIG_SYS_NAND_BASE (CONFIG_SYS_NAND_ADDR + CONFIG_SYS_NAND_CS) |
| 420 | #define CONFIG_SYS_NAND_SELECT_DEVICE 1 /* nand driver supports mutipl. chips */ | |
| 43a2b0e7 | 421 | |
| 214398d9 | 422 | /* |
| b05e8bf5 LJ |
423 | * PPC440 GPIO Configuration |
| 424 | */ | |
| 425 | /* test-only: take GPIO init from pcs440ep ???? in config file */ | |
| 6d0f6bcf | 426 | #define CONFIG_SYS_4xx_GPIO_TABLE { /* Out GPIO Alternate1 Alternate2 Alternate3 */ \ |
| b05e8bf5 LJ |
427 | { \ |
| 428 | /* GPIO Core 0 */ \ | |
| 429 | {GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, /* GPIO0 EBC_ADDR(7) DMA_REQ(2) */ \ | |
| 430 | {GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, /* GPIO1 EBC_ADDR(6) DMA_ACK(2) */ \ | |
| 431 | {GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO2 EBC_ADDR(5) DMA_EOT/TC(2) */ \ | |
| 432 | {GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO3 EBC_ADDR(4) DMA_REQ(3) */ \ | |
| 433 | {GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO4 EBC_ADDR(3) DMA_ACK(3) */ \ | |
| 434 | {GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO5 EBC_ADDR(2) DMA_EOT/TC(3) */ \ | |
| 435 | {GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO6 EBC_CS_N(1) */ \ | |
| 436 | {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO7 EBC_CS_N(2) */ \ | |
| 437 | {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO8 EBC_CS_N(3) */ \ | |
| 438 | {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO9 EBC_CS_N(4) */ \ | |
| 439 | {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO10 EBC_CS_N(5) */ \ | |
| 440 | {GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO11 EBC_BUS_ERR */ \ | |
| 441 | {GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO12 */ \ | |
| 442 | {GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO13 */ \ | |
| 443 | {GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO14 */ \ | |
| 444 | {GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO15 */ \ | |
| 445 | {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_1}, /* GPIO16 GMCTxD(4) */ \ | |
| 446 | {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_1}, /* GPIO17 GMCTxD(5) */ \ | |
| 447 | {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_1}, /* GPIO18 GMCTxD(6) */ \ | |
| 448 | {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_1}, /* GPIO19 GMCTxD(7) */ \ | |
| 449 | {GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO20 RejectPkt0 */ \ | |
| 450 | {GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO21 RejectPkt1 */ \ | |
| 451 | {GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO22 */ \ | |
| 452 | {GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO23 SCPD0 */ \ | |
| 453 | {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_1}, /* GPIO24 GMCTxD(2) */ \ | |
| 454 | {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_1}, /* GPIO25 GMCTxD(3) */ \ | |
| 455 | {GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO26 */ \ | |
| 456 | {GPIO0_BASE, GPIO_IN , GPIO_ALT2, GPIO_OUT_0}, /* GPIO27 EXT_EBC_REQ USB2D_RXERROR */ \ | |
| 457 | {GPIO0_BASE, GPIO_OUT, GPIO_ALT2, GPIO_OUT_1}, /* GPIO28 USB2D_TXVALID */ \ | |
| 458 | {GPIO0_BASE, GPIO_OUT, GPIO_ALT2, GPIO_OUT_1}, /* GPIO29 EBC_EXT_HDLA USB2D_PAD_SUSPNDM */ \ | |
| 459 | {GPIO0_BASE, GPIO_OUT, GPIO_ALT2, GPIO_OUT_1}, /* GPIO30 EBC_EXT_ACK USB2D_XCVRSELECT*/ \ | |
| 460 | {GPIO0_BASE, GPIO_OUT, GPIO_ALT2, GPIO_OUT_1}, /* GPIO31 EBC_EXR_BUSREQ USB2D_TERMSELECT*/ \ | |
| 461 | }, \ | |
| 462 | { \ | |
| 463 | /* GPIO Core 1 */ \ | |
| 464 | {GPIO1_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_1}, /* GPIO32 USB2D_OPMODE0 EBC_DATA(2) */ \ | |
| 465 | {GPIO1_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_1}, /* GPIO33 USB2D_OPMODE1 EBC_DATA(3) */ \ | |
| eab10073 SF |
466 | {GPIO1_BASE, GPIO_IN , GPIO_ALT2, GPIO_OUT_0}, /* GPIO34 UART0_8PIN_DCD_N UART1_DSR_CTS_N UART2_SOUT*/ \ |
| 467 | {GPIO1_BASE, GPIO_OUT, GPIO_ALT2, GPIO_OUT_1}, /* GPIO35 UART0_8PIN_DSR_N UART1_RTS_DTR_N UART2_SIN*/ \ | |
| 468 | {GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO36 UART0_CTS_N EBC_DATA(0) UART3_SIN*/ \ | |
| 469 | {GPIO1_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_1}, /* GPIO37 UART0_RTS_N EBC_DATA(1) UART3_SOUT*/ \ | |
| 470 | {GPIO1_BASE, GPIO_OUT, GPIO_ALT2, GPIO_OUT_1}, /* GPIO38 UART0_8PIN_DTR_N UART1_SOUT */ \ | |
| 471 | {GPIO1_BASE, GPIO_IN , GPIO_ALT2, GPIO_OUT_0}, /* GPIO39 UART0_8PIN_RI_N UART1_SIN */ \ | |
| b05e8bf5 LJ |
472 | {GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO40 UIC_IRQ(0) */ \ |
| 473 | {GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO41 UIC_IRQ(1) */ \ | |
| 474 | {GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO42 UIC_IRQ(2) */ \ | |
| 475 | {GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO43 UIC_IRQ(3) */ \ | |
| 476 | {GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO44 UIC_IRQ(4) DMA_ACK(1) */ \ | |
| 477 | {GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO45 UIC_IRQ(6) DMA_EOT/TC(1) */ \ | |
| 478 | {GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO46 UIC_IRQ(7) DMA_REQ(0) */ \ | |
| 479 | {GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO47 UIC_IRQ(8) DMA_ACK(0) */ \ | |
| 480 | {GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO48 UIC_IRQ(9) DMA_EOT/TC(0) */ \ | |
| 481 | {GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO49 Unselect via TraceSelect Bit */ \ | |
| 482 | {GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO50 Unselect via TraceSelect Bit */ \ | |
| 483 | {GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO51 Unselect via TraceSelect Bit */ \ | |
| 484 | {GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO52 Unselect via TraceSelect Bit */ \ | |
| 485 | {GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO53 Unselect via TraceSelect Bit */ \ | |
| 486 | {GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO54 Unselect via TraceSelect Bit */ \ | |
| 487 | {GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO55 Unselect via TraceSelect Bit */ \ | |
| 488 | {GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO56 Unselect via TraceSelect Bit */ \ | |
| 489 | {GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO57 Unselect via TraceSelect Bit */ \ | |
| 490 | {GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO58 Unselect via TraceSelect Bit */ \ | |
| 491 | {GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO59 Unselect via TraceSelect Bit */ \ | |
| 492 | {GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO60 Unselect via TraceSelect Bit */ \ | |
| 493 | {GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO61 Unselect via TraceSelect Bit */ \ | |
| 494 | {GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO62 Unselect via TraceSelect Bit */ \ | |
| 495 | {GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO63 Unselect via TraceSelect Bit */ \ | |
| 496 | } \ | |
| 497 | } | |
| 498 | ||
| bc778812 AG |
499 | #ifdef CONFIG_VIDEO |
| 500 | #define CONFIG_BIOSEMU /* x86 bios emulator for vga bios */ | |
| 501 | #define CONFIG_ATI_RADEON_FB /* use radeon framebuffer driver */ | |
| 502 | #define VIDEO_IO_OFFSET 0xe8000000 | |
| 6d0f6bcf | 503 | #define CONFIG_SYS_ISA_IO_BASE_ADDRESS VIDEO_IO_OFFSET |
| bc778812 AG |
504 | #define CONFIG_VIDEO_SW_CURSOR |
| 505 | #define CONFIG_VIDEO_LOGO | |
| 506 | #define CONFIG_CFB_CONSOLE | |
| 507 | #define CONFIG_SPLASH_SCREEN | |
| 508 | #define CONFIG_VGA_AS_SINGLE_DEVICE | |
| 509 | #define CONFIG_CMD_BMP | |
| 510 | #endif | |
| 511 | ||
| 214398d9 | 512 | #endif /* __CONFIG_H */ |