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5095ee08 PM |
1 | /* |
2 | * Copyright (C) 2012 Altera Corporation <www.altera.com> | |
3 | * | |
4 | * SPDX-License-Identifier: GPL-2.0+ | |
5 | */ | |
6 | #ifndef __CONFIG_SOCFPGA_CYCLONE5_COMMON_H__ | |
7 | #define __CONFIG_SOCFPGA_CYCLONE5_COMMON_H__ | |
8 | ||
9 | #define CONFIG_SYS_GENERIC_BOARD | |
10 | ||
11 | /* Virtual target or real hardware */ | |
12 | #undef CONFIG_SOCFPGA_VIRTUAL_TARGET | |
13 | ||
14 | #define CONFIG_ARMV7 | |
15 | #define CONFIG_SYS_THUMB_BUILD | |
16 | ||
17 | #define CONFIG_SOCFPGA | |
18 | ||
19 | /* | |
20 | * High level configuration | |
21 | */ | |
22 | #define CONFIG_DISPLAY_CPUINFO | |
23 | #define CONFIG_DISPLAY_BOARDINFO | |
24 | #define CONFIG_BOARD_EARLY_INIT_F | |
fc520894 | 25 | #define CONFIG_ARCH_EARLY_INIT_R |
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26 | #define CONFIG_SYS_NO_FLASH |
27 | #define CONFIG_CLOCKS | |
28 | ||
29 | #define CONFIG_FIT | |
30 | #define CONFIG_OF_LIBFDT | |
31 | #define CONFIG_SYS_BOOTMAPSZ (64 * 1024 * 1024) | |
32 | ||
33 | #define CONFIG_TIMESTAMP /* Print image info with timestamp */ | |
34 | ||
35 | /* | |
36 | * Memory configurations | |
37 | */ | |
38 | #define CONFIG_NR_DRAM_BANKS 1 | |
39 | #define PHYS_SDRAM_1 0x0 | |
40 | #define CONFIG_SYS_MALLOC_LEN (10 * 1024 * 1024) | |
41 | #define CONFIG_SYS_MEMTEST_START PHYS_SDRAM_1 | |
42 | #define CONFIG_SYS_MEMTEST_END PHYS_SDRAM_1_SIZE | |
43 | ||
44 | #define CONFIG_SYS_INIT_RAM_ADDR 0xFFFF0000 | |
45 | #define CONFIG_SYS_INIT_RAM_SIZE (0x10000 - 0x100) | |
46 | #define CONFIG_SYS_INIT_SP_ADDR \ | |
47 | (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_RAM_SIZE - \ | |
48 | GENERATED_GBL_DATA_SIZE) | |
49 | ||
50 | #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 | |
51 | #ifdef CONFIG_SOCFPGA_VIRTUAL_TARGET | |
52 | #define CONFIG_SYS_TEXT_BASE 0x08000040 | |
53 | #else | |
54 | #define CONFIG_SYS_TEXT_BASE 0x01000040 | |
55 | #endif | |
56 | ||
57 | /* | |
58 | * U-Boot general configurations | |
59 | */ | |
60 | #define CONFIG_SYS_LONGHELP | |
61 | #define CONFIG_SYS_CBSIZE 1024 /* Console I/O buffer size */ | |
62 | #define CONFIG_SYS_PBSIZE \ | |
63 | (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) | |
64 | /* Print buffer size */ | |
65 | #define CONFIG_SYS_MAXARGS 32 /* Max number of command args */ | |
66 | #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE | |
67 | /* Boot argument buffer size */ | |
68 | #define CONFIG_VERSION_VARIABLE /* U-BOOT version */ | |
69 | #define CONFIG_AUTO_COMPLETE /* Command auto complete */ | |
70 | #define CONFIG_CMDLINE_EDITING /* Command history etc */ | |
71 | #define CONFIG_SYS_HUSH_PARSER | |
72 | ||
73 | /* | |
74 | * Cache | |
75 | */ | |
76 | #define CONFIG_SYS_ARM_CACHE_WRITEALLOC | |
77 | #define CONFIG_SYS_CACHELINE_SIZE 32 | |
78 | #define CONFIG_SYS_L2_PL310 | |
79 | #define CONFIG_SYS_PL310_BASE SOCFPGA_MPUL2_ADDRESS | |
80 | ||
81 | /* | |
82 | * Ethernet on SoC (EMAC) | |
83 | */ | |
84 | #if defined(CONFIG_CMD_NET) && !defined(CONFIG_SOCFPGA_VIRTUAL_TARGET) | |
85 | #define CONFIG_DESIGNWARE_ETH | |
86 | #define CONFIG_NET_MULTI | |
87 | #define CONFIG_DW_ALTDESCRIPTOR | |
88 | #define CONFIG_MII | |
89 | #define CONFIG_AUTONEG_TIMEOUT (15 * CONFIG_SYS_HZ) | |
90 | #define CONFIG_PHYLIB | |
91 | #define CONFIG_PHY_GIGE | |
92 | #endif | |
93 | ||
94 | /* | |
95 | * FPGA Driver | |
96 | */ | |
97 | #ifdef CONFIG_CMD_FPGA | |
98 | #define CONFIG_FPGA | |
99 | #define CONFIG_FPGA_ALTERA | |
100 | #define CONFIG_FPGA_SOCFPGA | |
101 | #define CONFIG_FPGA_COUNT 1 | |
102 | #endif | |
103 | ||
104 | /* | |
105 | * L4 OSC1 Timer 0 | |
106 | */ | |
107 | /* This timer uses eosc1, whose clock frequency is fixed at any condition. */ | |
108 | #define CONFIG_SYS_TIMERBASE SOCFPGA_OSC1TIMER0_ADDRESS | |
109 | #define CONFIG_SYS_TIMER_COUNTS_DOWN | |
110 | #define CONFIG_SYS_TIMER_COUNTER (CONFIG_SYS_TIMERBASE + 0x4) | |
111 | #ifdef CONFIG_SOCFPGA_VIRTUAL_TARGET | |
112 | #define CONFIG_SYS_TIMER_RATE 2400000 | |
113 | #else | |
114 | #define CONFIG_SYS_TIMER_RATE 25000000 | |
115 | #endif | |
116 | ||
117 | /* | |
118 | * L4 Watchdog | |
119 | */ | |
120 | #ifdef CONFIG_HW_WATCHDOG | |
121 | #define CONFIG_DESIGNWARE_WATCHDOG | |
122 | #define CONFIG_DW_WDT_BASE SOCFPGA_L4WD0_ADDRESS | |
123 | #define CONFIG_DW_WDT_CLOCK_KHZ 25000 | |
124 | #define CONFIG_HW_WATCHDOG_TIMEOUT_MS 12000 | |
125 | #endif | |
126 | ||
127 | /* | |
128 | * MMC Driver | |
129 | */ | |
130 | #ifdef CONFIG_CMD_MMC | |
131 | #define CONFIG_MMC | |
132 | #define CONFIG_BOUNCE_BUFFER | |
133 | #define CONFIG_GENERIC_MMC | |
134 | #define CONFIG_DWMMC | |
135 | #define CONFIG_SOCFPGA_DWMMC | |
136 | #define CONFIG_SOCFPGA_DWMMC_FIFO_DEPTH 1024 | |
137 | #define CONFIG_SOCFPGA_DWMMC_DRVSEL 3 | |
138 | #define CONFIG_SOCFPGA_DWMMC_SMPSEL 0 | |
139 | /* FIXME */ | |
140 | /* using smaller max blk cnt to avoid flooding the limited stack we have */ | |
141 | #define CONFIG_SYS_MMC_MAX_BLK_COUNT 256 /* FIXME -- SPL only? */ | |
142 | #endif | |
143 | ||
144 | /* | |
145 | * Serial Driver | |
146 | */ | |
147 | #define CONFIG_SYS_NS16550 | |
148 | #define CONFIG_SYS_NS16550_SERIAL | |
149 | #define CONFIG_SYS_NS16550_REG_SIZE -4 | |
150 | #define CONFIG_SYS_NS16550_COM1 SOCFPGA_UART0_ADDRESS | |
151 | #ifdef CONFIG_SOCFPGA_VIRTUAL_TARGET | |
152 | #define CONFIG_SYS_NS16550_CLK 1000000 | |
153 | #else | |
154 | #define CONFIG_SYS_NS16550_CLK 100000000 | |
155 | #endif | |
156 | #define CONFIG_CONS_INDEX 1 | |
157 | #define CONFIG_BAUDRATE 115200 | |
158 | ||
20cadbbe MV |
159 | /* |
160 | * USB | |
161 | */ | |
162 | #ifdef CONFIG_CMD_USB | |
163 | #define CONFIG_USB_DWC2 | |
164 | #define CONFIG_USB_STORAGE | |
165 | /* | |
166 | * NOTE: User must define either of the following to select which | |
167 | * of the two USB controllers available on SoCFPGA to use. | |
168 | * The DWC2 driver doesn't support multiple USB controllers. | |
169 | * #define CONFIG_USB_DWC2_REG_ADDR SOCFPGA_USB0_ADDRESS | |
170 | * #define CONFIG_USB_DWC2_REG_ADDR SOCFPGA_USB1_ADDRESS | |
171 | */ | |
172 | #endif | |
173 | ||
5095ee08 PM |
174 | /* |
175 | * U-Boot environment | |
176 | */ | |
177 | #define CONFIG_SYS_CONSOLE_IS_IN_ENV | |
178 | #define CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE | |
179 | #define CONFIG_SYS_CONSOLE_ENV_OVERWRITE | |
180 | #define CONFIG_ENV_IS_NOWHERE | |
181 | #define CONFIG_ENV_SIZE 4096 | |
182 | ||
183 | /* | |
184 | * SPL | |
34584d19 MV |
185 | * |
186 | * SRAM Memory layout: | |
187 | * | |
188 | * 0xFFFF_0000 ...... Start of SRAM | |
189 | * 0xFFFF_xxxx ...... Top of stack (grows down) | |
190 | * 0xFFFF_yyyy ...... Malloc area | |
191 | * 0xFFFF_zzzz ...... Global Data | |
192 | * 0xFFFF_FF00 ...... End of SRAM | |
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193 | */ |
194 | #define CONFIG_SPL_FRAMEWORK | |
195 | #define CONFIG_SPL_BOARD_INIT | |
196 | #define CONFIG_SPL_RAM_DEVICE | |
34584d19 MV |
197 | #define CONFIG_SPL_TEXT_BASE CONFIG_SYS_INIT_RAM_ADDR |
198 | #define CONFIG_SYS_SPL_MALLOC_START CONFIG_SYS_INIT_SP_ADDR | |
199 | #define CONFIG_SYS_SPL_MALLOC_SIZE (5 * 1024) | |
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200 | |
201 | #define CHUNKSZ_CRC32 (1 * 1024) /* FIXME: ewww */ | |
202 | #define CONFIG_CRC32_VERIFY | |
203 | ||
204 | /* Linker script for SPL */ | |
205 | #define CONFIG_SPL_LDSCRIPT "arch/arm/cpu/armv7/socfpga/u-boot-spl.lds" | |
206 | ||
207 | #define CONFIG_SPL_LIBCOMMON_SUPPORT | |
208 | #define CONFIG_SPL_LIBGENERIC_SUPPORT | |
209 | #define CONFIG_SPL_WATCHDOG_SUPPORT | |
210 | #define CONFIG_SPL_SERIAL_SUPPORT | |
211 | ||
212 | #ifdef CONFIG_SPL_BUILD | |
213 | #undef CONFIG_PARTITIONS | |
214 | #endif | |
215 | ||
216 | #endif /* __CONFIG_SOCFPGA_CYCLONE5_COMMON_H__ */ |