[people/ms/u-boot.git] / include / configs / socfpga_sr1500.h

/*
 * Copyright (C) 2015 Stefan Roese <sr@denx.de>
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */
#ifndef __CONFIG_SOCFPGA_SR1500_H__
#define __CONFIG_SOCFPGA_SR1500_H__

#include <asm/arch/base_addr_ac5.h>

#define CONFIG_BOARD_EARLY_INIT_F

#define CONFIG_SYS_NO_FLASH
#define CONFIG_DOS_PARTITION
#define CONFIG_FAT_WRITE

#define CONFIG_HW_WATCHDOG

/* U-Boot Commands */
#define CONFIG_CMD_ASKENV
#define CONFIG_CMD_BOOTZ
#define CONFIG_CMD_CACHE
#define CONFIG_CMD_EXT4
#define CONFIG_CMD_EXT4_WRITE
#define CONFIG_CMD_FAT
#define CONFIG_CMD_FS_GENERIC
#define CONFIG_CMD_GREPENV
#define CONFIG_CMD_MII
#define CONFIG_CMD_MMC

/* Memory configurations */
#define PHYS_SDRAM_1_SIZE		0x40000000	/* 1GiB on SR1500 */

/* Booting Linux */
#define CONFIG_BOOTDELAY	3
#define CONFIG_BOOTFILE		"uImage"
#define CONFIG_BOOTARGS		"console=ttyS0" __stringify(CONFIG_BAUDRATE)
#define CONFIG_BOOTCOMMAND	"run mmcload; run mmcboot"
#define CONFIG_LOADADDR		0x01000000
#define CONFIG_SYS_LOAD_ADDR	CONFIG_LOADADDR
#define CONFIG_SYS_CONSOLE_INFO_QUIET	/* don't print console @ startup */

/* Ethernet on SoC (EMAC) */
#define CONFIG_PHY_INTERFACE_MODE	PHY_INTERFACE_MODE_RGMII
/* The PHY is autodetected, so no MII PHY address is needed here */
#define CONFIG_PHY_MARVELL
#define PHY_ANEG_TIMEOUT	8000

#define CONFIG_EXTRA_ENV_SETTINGS \
	"verify=n\0" \
	"loadaddr=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \
	"ramboot=setenv bootargs " CONFIG_BOOTARGS ";" \
		"bootm ${loadaddr} - ${fdt_addr}\0" \
	"bootimage=zImage\0" \
	"fdt_addr=100\0" \
	"fdtimage=socfpga.dtb\0" \
		"fsloadcmd=ext2load\0" \
	"bootm ${loadaddr} - ${fdt_addr}\0" \
	"mmcroot=/dev/mmcblk0p2\0" \
	"mmcboot=setenv bootargs " CONFIG_BOOTARGS \
		" root=${mmcroot} rw rootwait;" \
		"bootz ${loadaddr} - ${fdt_addr}\0" \
	"mmcload=mmc rescan;" \
		"load mmc 0:1 ${loadaddr} ${bootimage};" \
		"load mmc 0:1 ${fdt_addr} ${fdtimage}\0" \
	"qspiload=sf probe && mtdparts default && run ubiload\0" \
	"qspiboot=setenv bootargs " CONFIG_BOOTARGS \
		" ubi.mtd=1,64 root=ubi0:rootfs rw rootfstype=ubifs;"\
		"bootz ${loadaddr} - ${fdt_addr}\0" \
	"ubiload=ubi part UBI && ubifsmount ubi0 && " \
		"ubifsload ${loadaddr} /boot/${bootimage} && " \
		"ubifsload ${fdt_addr} /boot/${fdtimage}\0"

/* Environment */
#define CONFIG_ENV_IS_IN_SPI_FLASH

/* Enable SPI NOR flash reset, needed for SPI booting */
#define CONFIG_SPI_N25Q256A_RESET

/*
 * Bootcounter
 */
#define CONFIG_BOOTCOUNT_LIMIT
/* last 2 lwords in OCRAM */
#define CONFIG_SYS_BOOTCOUNT_ADDR	0xfffffff8
#define CONFIG_SYS_BOOTCOUNT_BE

/* Environment setting for SPI flash */
#define CONFIG_SYS_REDUNDAND_ENVIRONMENT
#define CONFIG_ENV_SECT_SIZE	(64 * 1024)
#define CONFIG_ENV_SIZE		(16 * 1024)
#define CONFIG_ENV_OFFSET	0x000e0000
#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + CONFIG_ENV_SECT_SIZE)
#define CONFIG_ENV_SPI_BUS	0
#define CONFIG_ENV_SPI_CS	0
#define CONFIG_ENV_SPI_MODE	SPI_MODE_3
#define CONFIG_ENV_SPI_MAX_HZ	100000000	/* Use max of 100MHz */
#define CONFIG_SF_DEFAULT_SPEED	100000000

/*
 * The QSPI NOR flash layout on SR1500:
 *
 * 0000.0000 - 0003.ffff: SPL (4 times)
 * 0004.0000 - 000d.ffff: U-Boot
 * 000e.0000 - 000e.ffff: env1
 * 000f.0000 - 000f.ffff: env2
 */

/* The rest of the configuration is shared */
#include <configs/socfpga_common.h>

#endif	/* __CONFIG_SOCFPGA_SR1500_H__ */
Commit	Line	Data
ae9996c8 SR	1	/*
	2	* Copyright (C) 2015 Stefan Roese <sr@denx.de>
	3	*
	4	* SPDX-License-Identifier: GPL-2.0+
	5	*/
	6	#ifndef __CONFIG_SOCFPGA_SR1500_H__
	7	#define __CONFIG_SOCFPGA_SR1500_H__
	8
	9	#include <asm/arch/base_addr_ac5.h>
	10
	11	#define CONFIG_BOARD_EARLY_INIT_F
	12
	13	#define CONFIG_SYS_NO_FLASH
	14	#define CONFIG_DOS_PARTITION
	15	#define CONFIG_FAT_WRITE
	16
	17	#define CONFIG_HW_WATCHDOG
	18
	19	/* U-Boot Commands */
	20	#define CONFIG_CMD_ASKENV
	21	#define CONFIG_CMD_BOOTZ
	22	#define CONFIG_CMD_CACHE
ae9996c8 SR	23	#define CONFIG_CMD_EXT4
	24	#define CONFIG_CMD_EXT4_WRITE
	25	#define CONFIG_CMD_FAT
	26	#define CONFIG_CMD_FS_GENERIC
ae9996c8	27	#define CONFIG_CMD_GREPENV
ae9996c8 SR	28	#define CONFIG_CMD_MII
ae9996c8 SR	29	#define CONFIG_CMD_MMC
ae9996c8 SR	30
	31	/* Memory configurations */
	32	#define PHYS_SDRAM_1_SIZE 0x40000000 /* 1GiB on SR1500 */
	33
	34	/* Booting Linux */
	35	#define CONFIG_BOOTDELAY 3
	36	#define CONFIG_BOOTFILE "uImage"
	37	#define CONFIG_BOOTARGS "console=ttyS0" __stringify(CONFIG_BAUDRATE)
	38	#define CONFIG_BOOTCOMMAND "run mmcload; run mmcboot"
	39	#define CONFIG_LOADADDR 0x01000000
	40	#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
	41	#define CONFIG_SYS_CONSOLE_INFO_QUIET /* don't print console @ startup */
	42
	43	/* Ethernet on SoC (EMAC) */
	44	#define CONFIG_PHY_INTERFACE_MODE PHY_INTERFACE_MODE_RGMII
	45	/* The PHY is autodetected, so no MII PHY address is needed here */
	46	#define CONFIG_PHY_MARVELL
	47	#define PHY_ANEG_TIMEOUT 8000
	48
ae9996c8 SR	49	#define CONFIG_EXTRA_ENV_SETTINGS \
ae9996c8 SR	50	"verify=n\0" \
f6060ce4	51	"loadaddr=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \
ae9996c8 SR	52	"ramboot=setenv bootargs " CONFIG_BOOTARGS ";" \
	53	"bootm ${loadaddr} - ${fdt_addr}\0" \
	54	"bootimage=zImage\0" \
	55	"fdt_addr=100\0" \
	56	"fdtimage=socfpga.dtb\0" \
	57	"fsloadcmd=ext2load\0" \
	58	"bootm ${loadaddr} - ${fdt_addr}\0" \
	59	"mmcroot=/dev/mmcblk0p2\0" \
	60	"mmcboot=setenv bootargs " CONFIG_BOOTARGS \
	61	" root=${mmcroot} rw rootwait;" \
	62	"bootz ${loadaddr} - ${fdt_addr}\0" \
	63	"mmcload=mmc rescan;" \
	64	"load mmc 0:1 ${loadaddr} ${bootimage};" \
	65	"load mmc 0:1 ${fdt_addr} ${fdtimage}\0" \
b3bb1110	66	"qspiload=sf probe && mtdparts default && run ubiload\0" \
ae9996c8	67	"qspiboot=setenv bootargs " CONFIG_BOOTARGS \
94f53a7d CLS	68	" ubi.mtd=1,64 root=ubi0:rootfs rw rootfstype=ubifs;"\
94f53a7d CLS	69	"bootz ${loadaddr} - ${fdt_addr}\0" \
eb45022c CLS	70	"ubiload=ubi part UBI && ubifsmount ubi0 && " \
	71	"ubifsload ${loadaddr} /boot/${bootimage} && " \
	72	"ubifsload ${fdt_addr} /boot/${fdtimage}\0"
ae9996c8 SR	73
	74	/* Environment */
	75	#define CONFIG_ENV_IS_IN_SPI_FLASH
	76
	77	/* Enable SPI NOR flash reset, needed for SPI booting */
	78	#define CONFIG_SPI_N25Q256A_RESET
	79
	80	/*
	81	* Bootcounter
	82	*/
	83	#define CONFIG_BOOTCOUNT_LIMIT
	84	/* last 2 lwords in OCRAM */
	85	#define CONFIG_SYS_BOOTCOUNT_ADDR 0xfffffff8
	86	#define CONFIG_SYS_BOOTCOUNT_BE
	87
ae9996c8	88	/* Environment setting for SPI flash */
ae9996c8 SR	89	#define CONFIG_SYS_REDUNDAND_ENVIRONMENT
	90	#define CONFIG_ENV_SECT_SIZE (64 * 1024)
	91	#define CONFIG_ENV_SIZE (16 * 1024)
93d9fc26	92	#define CONFIG_ENV_OFFSET 0x000e0000
ae9996c8 SR	93	#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + CONFIG_ENV_SECT_SIZE)
	94	#define CONFIG_ENV_SPI_BUS 0
	95	#define CONFIG_ENV_SPI_CS 0
	96	#define CONFIG_ENV_SPI_MODE SPI_MODE_3
93d9fc26 SR	97	#define CONFIG_ENV_SPI_MAX_HZ 100000000 /* Use max of 100MHz */
	98	#define CONFIG_SF_DEFAULT_SPEED 100000000
	99
	100	/*
	101	* The QSPI NOR flash layout on SR1500:
	102	*
	103	* 0000.0000 - 0003.ffff: SPL (4 times)
	104	* 0004.0000 - 000d.ffff: U-Boot
	105	* 000e.0000 - 000e.ffff: env1
	106	* 000f.0000 - 000f.ffff: env2
	107	*/
ae9996c8	108
b72041cc MV	109	/* The rest of the configuration is shared */
	110	#include <configs/socfpga_common.h>
	111
ae9996c8	112	#endif /* __CONFIG_SOCFPGA_SR1500_H__ */