[people/ms/u-boot.git] / include / configs / sorcery.h

/*
 * (C) Copyright 2004
 * TsiChung Liew, Freescale Software Engineering, Tsi-Chung.Liew@freescale.
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */

#ifndef __CONFIG_H
#define __CONFIG_H

/*
 * High Level Configuration Options
 * (easy to change)
 */
#define CONFIG_MPC8220		1
#define CONFIG_SORCERY		1	/* Sorcery board */

#define CONFIG_HIGH_BATS	1	/* High BATs supported */

/* Input clock running at 60Mhz, read Hid1 for the CPU multiplier to
   determine the CPU speed. */
#define CONFIG_SYS_MPC8220_CLKIN	60000000 /* ... running at 60MHz */
#define CONFIG_SYS_MPC8220_SYSPLL_VCO_MULTIPLIER 8 /* VCO multiplier can't be read from any register */

#define BOOTFLAG_COLD		0x01	/* Normal Power-On: Boot from FLASH */
#define BOOTFLAG_WARM		0x02	/* Software reboot	*/

/*
 * Serial console configuration
 */
#define CONFIG_PSC_CONSOLE	1	/* console is on PSC */

#define CONFIG_BAUDRATE		115200	    /* ... at 115200 bps */
#define CONFIG_SYS_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200, 230400 }

/* PCI */
#define CONFIG_PCI              1
#define CONFIG_PCI_PNP          1

#define CONFIG_PCI_MEM_BUS      0x80000000
#define CONFIG_PCI_MEM_PHYS     CONFIG_PCI_MEM_BUS
#define CONFIG_PCI_MEM_SIZE     0x10000000

#define CONFIG_PCI_IO_BUS	0x71000000
#define CONFIG_PCI_IO_PHYS	CONFIG_PCI_IO_BUS
#define CONFIG_PCI_IO_SIZE	0x01000000

#define CONFIG_PCI_CFG_BUS	0x70000000
#define CONFIG_PCI_CFG_PHYS	CONFIG_PCI_CFG_BUS
#define CONFIG_PCI_CFG_SIZE	0x01000000


/*
 * BOOTP options
 */
#define CONFIG_BOOTP_BOOTFILESIZE
#define CONFIG_BOOTP_BOOTPATH
#define CONFIG_BOOTP_GATEWAY
#define CONFIG_BOOTP_HOSTNAME


/*
 * Command line configuration.
 */
#include <config_cmd_default.h>

#define CONFIG_CMD_BOOTD
#define CONFIG_CMD_CACHE
#define CONFIG_CMD_DHCP
#define CONFIG_CMD_DIAG
#define CONFIG_CMD_ELF
#define CONFIG_CMD_I2C
#define CONFIG_CMD_NET
#define CONFIG_CMD_NFS
#define CONFIG_CMD_PCI
#define CONFIG_CMD_PING
#define CONFIG_CMD_REGINFO
#define CONFIG_CMD_SDRAM
#define CONFIG_CMD_SNTP


/*
 * Default Environment
 */
#define CONFIG_BOOTDELAY	5    /* autoboot after 5 seconds */
#define CONFIG_HOSTNAME		sorcery

#define CONFIG_PREBOOT	"echo;"	\
	"echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
	"echo"

#undef	CONFIG_BOOTARGS

#define	CONFIG_EXTRA_ENV_SETTINGS					\
	"netdev=eth0\0"							\
	"nfsargs=setenv bootargs root=/dev/nfs rw "			\
		"nfsroot=$serverip:$rootpath\0"				\
	"ramargs=setenv bootargs root=/dev/ram rw\0"			\
	"addip=setenv bootargs $bootargs "				\
		"ip=$ipaddr:$serverip:$gatewayip:$netmask"		\
		":$hostname:$netdev:off panic=1\0"			\
	"flash_nfs=run nfsargs addip;"					\
		"bootm $kernel_addr\0"					\
	"flash_self=run ramargs addip;"					\
		"bootm $kernel_addr $ramdisk_addr\0"			\
	"net_nfs=tftp 200000 $bootfile;run nfsargs addip;bootm\0"	\
	"rootpath=/opt/eldk/ppc_82xx\0"					\
	"bootfile=/tftpboot/sorcery/uImage\0"				\
	"kernel_addr=FFE00000\0"					\
	"ramdisk_addr=FFB00000\0"					\
	""
#define CONFIG_BOOTCOMMAND	"run flash_self"

#define CONFIG_TIMESTAMP		/* Print image info with timestamp */

#define CONFIG_NET_MULTI
#define CONFIG_EEPRO100

/*
 * I2C configuration
 */
#define CONFIG_HARD_I2C		1
#define CONFIG_SYS_I2C_MODULE		1
#define CONFIG_SYS_I2C_SPEED		100000 /* 100 kHz */
#define CONFIG_SYS_I2C_SLAVE		0x7F

/* Use the HUSH parser */
#define CONFIG_SYS_HUSH_PARSER
#ifdef	CONFIG_SYS_HUSH_PARSER
#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
#endif

/*
 * Flexbus Chipselect configuration
 * Beware: Some CS# seem to be mandatory (if these CS# are not set,
 * board can hang-up in unpredictable place).
 * Sorcery_Memory_Map v0.3 is possibly wrong with CPLD CS#
 */

/* Flash */
#define CONFIG_SYS_CS0_BASE		0xf800
#define CONFIG_SYS_CS0_MASK		0x08000000 /* 128 MB (two chips) */
#define CONFIG_SYS_CS0_CTRL		0x001019c0

/* NVM */
#define CONFIG_SYS_CS1_BASE		0xf7e8
#define CONFIG_SYS_CS1_MASK		0x00040000 /* 256K */
#define CONFIG_SYS_CS1_CTRL		0x00101940 /* 8bit port size */

/* Atlas2 + Gemini */
#define CONFIG_SYS_CS2_BASE		0xf7e7
#define CONFIG_SYS_CS2_MASK		0x00010000 /* 64K*/
#define CONFIG_SYS_CS2_CTRL		0x001011c0 /* 16bit port size */

/* CAN Controller */
#define CONFIG_SYS_CS3_BASE		0xf7e6
#define CONFIG_SYS_CS3_MASK		0x00010000 /* 64K */
#define CONFIG_SYS_CS3_CTRL		0x00102140 /* 8Bit port size */

/* Foreign interface */
#define CONFIG_SYS_CS4_BASE		0xf7e5
#define CONFIG_SYS_CS4_MASK		0x00010000 /* 64K */
#define CONFIG_SYS_CS4_CTRL		0x00101dc0 /* 16bit port size */

/* CPLD */
#define CONFIG_SYS_CS5_BASE		0xf7e4
#define CONFIG_SYS_CS5_MASK		0x00010000 /* 64K */
#define CONFIG_SYS_CS5_CTRL		0x001000c0 /* 16bit port size */

#define CONFIG_SYS_FLASH0_BASE		(CONFIG_SYS_CS0_BASE << 16)
#define CONFIG_SYS_FLASH_BASE		(CONFIG_SYS_FLASH0_BASE)

#define CONFIG_SYS_MAX_FLASH_BANKS	2	/* max num of flash banks */
#define CONFIG_SYS_MAX_FLASH_SECT	512	/* max num of sects on one chip */

#define CONFIG_FLASH_CFI_DRIVER
#define CONFIG_SYS_FLASH_CFI
#define CONFIG_SYS_FLASH_BANKS_LIST	{ CONFIG_SYS_FLASH_BASE,  \
				CONFIG_SYS_FLASH_BASE+0x04000000 } /* two banks */

/*
 * Environment settings
 */
#define CONFIG_ENV_IS_IN_FLASH	1
#define CONFIG_ENV_ADDR		(CONFIG_SYS_FLASH_BASE + 0x8000000 - 0x40000)
#define CONFIG_ENV_SIZE		0x4000                       /* 16K */
#define CONFIG_ENV_SECT_SIZE	0x20000
#define CONFIG_ENV_ADDR_REDUND	(CONFIG_ENV_ADDR + 0x20000)
#define CONFIG_ENV_SIZE_REDUND	CONFIG_ENV_SIZE

#define CONFIG_ENV_OVERWRITE	1

#if defined CONFIG_ENV_IS_IN_FLASH
#undef CONFIG_ENV_IS_IN_NVRAM
#undef CONFIG_ENV_IS_IN_EEPROM
#elif defined CONFIG_ENV_IS_IN_NVRAM
#undef CONFIG_ENV_IS_IN_FLASH
#undef CONFIG_ENV_IS_IN_EEPROM
#elif defined CONFIG_ENV_IS_IN_EEPROM
#undef CONFIG_ENV_IS_IN_NVRAM
#undef CONFIG_ENV_IS_IN_FLASH
#endif

/*
 * Memory map
 */
#define CONFIG_SYS_MBAR		0xF0000000
#define CONFIG_SYS_SDRAM_BASE		0x00000000
#define CONFIG_SYS_DEFAULT_MBAR	0x80000000
#define CONFIG_SYS_SRAM_BASE		(CONFIG_SYS_MBAR + 0x20000)
#define CONFIG_SYS_SRAM_SIZE		0x8000

/* Use SRAM until RAM will be available */
#define CONFIG_SYS_INIT_RAM_ADDR	(CONFIG_SYS_MBAR + 0x20000)
#define CONFIG_SYS_INIT_RAM_END	0x8000	/* End of used area in DPRAM */

#define CONFIG_SYS_GBL_DATA_SIZE	128	/* size in bytes reserved for initial data */
#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET

#define CONFIG_SYS_MONITOR_BASE	TEXT_BASE
#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
#   define CONFIG_SYS_RAMBOOT		1
#endif

#define CONFIG_SYS_MONITOR_LEN		(256 << 10) /* Reserve 256 kB for Monitor   */
#define CONFIG_SYS_MALLOC_LEN		(128 << 10) /* Reserve 128 kB for malloc()  */
#define CONFIG_SYS_BOOTMAPSZ		(8 << 20)   /* Initial Memory map for Linux */

/* SDRAM configuration (for SPD) */
#define CONFIG_SYS_SDRAM_TOTAL_BANKS		1
#define CONFIG_SYS_SDRAM_SPD_I2C_ADDR		0x50		/* 7bit */
#define CONFIG_SYS_SDRAM_SPD_SIZE		0x100
#define CONFIG_SYS_SDRAM_CAS_LATENCY		5		/* (CL=2.5)x2 */

/* SDRAM drive strength register (for SSTL_2 class II)*/
#define CONFIG_SYS_SDRAM_DRIVE_STRENGTH	((DRIVE_STRENGTH_HIGH << SDRAMDS_SBE_SHIFT) | \
					 (DRIVE_STRENGTH_HIGH << SDRAMDS_SBC_SHIFT) | \
					 (DRIVE_STRENGTH_HIGH << SDRAMDS_SBA_SHIFT) | \
					 (DRIVE_STRENGTH_HIGH << SDRAMDS_SBS_SHIFT) | \
					 (DRIVE_STRENGTH_HIGH << SDRAMDS_SBD_SHIFT))

/*
 * Ethernet configuration
 */
#define CONFIG_MPC8220_FEC	1
#define CONFIG_FEC_10MBIT	1 /* Workaround for FEC 100Mbit problem */
#define CONFIG_PHY_ADDR		0x1F
#define CONFIG_MII		1

/*
 * Miscellaneous configurable options
 */
#define CONFIG_SYS_LONGHELP			    /* undef to save memory	*/
#define CONFIG_SYS_PROMPT		"=> "	    /* Monitor Command Prompt	*/
#if defined(CONFIG_CMD_KGDB)
#define CONFIG_SYS_CBSIZE		1024	    /* Console I/O Buffer Size	*/
#else
#define CONFIG_SYS_CBSIZE		256	    /* Console I/O Buffer Size	*/
#endif
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)	/* Print Buffer Size */
#define CONFIG_SYS_MAXARGS		16	    /* max number of command args   */
#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE  /* Boot Argument Buffer Size    */

#define CONFIG_SYS_MEMTEST_START	0x00100000  /* memtest works on */
#define CONFIG_SYS_MEMTEST_END		0x00f00000  /* 1 ... 15 MB in DRAM  */

#define CONFIG_SYS_LOAD_ADDR		0x100000    /* default load address */

#define CONFIG_SYS_HZ			1000	    /* decrementer freq: 1 ms ticks */

#define CONFIG_SYS_CACHELINE_SIZE	32	/* For MPC8220 CPUs */
#if defined(CONFIG_CMD_KGDB)
#  define CONFIG_SYS_CACHELINE_SHIFT	5	/* log base 2 of the above value */
#endif

/*
 * Various low-level settings
 */
#define CONFIG_SYS_HID0_INIT		0
#define CONFIG_SYS_HID0_FINAL		0

/*
#define CONFIG_SYS_HID0_INIT           HID0_ICE | HID0_ICFI
#define CONFIG_SYS_HID0_FINAL          HID0_ICE
*/

#endif /* __CONFIG_H */
Commit	Line	Data
12b43d51 WD	1	/*
	2	* (C) Copyright 2004
	3	* TsiChung Liew, Freescale Software Engineering, Tsi-Chung.Liew@freescale.
	4	*
	5	* See file CREDITS for list of people who contributed to this
	6	* project.
	7	*
	8	* This program is free software; you can redistribute it and/or
	9	* modify it under the terms of the GNU General Public License as
	10	* published by the Free Software Foundation; either version 2 of
	11	* the License, or (at your option) any later version.
	12	*
	13	* This program is distributed in the hope that it will be useful,
	14	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	15	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	16	* GNU General Public License for more details.
	17	*
	18	* You should have received a copy of the GNU General Public License
	19	* along with this program; if not, write to the Free Software
	20	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	21	* MA 02111-1307 USA
	22	*/
	23
	24	#ifndef __CONFIG_H
	25	#define __CONFIG_H
	26
	27	/*
	28	* High Level Configuration Options
	29	* (easy to change)
	30	*/
	31	#define CONFIG_MPC8220 1
	32	#define CONFIG_SORCERY 1 /* Sorcery board */
	33
31d82672 BB	34	#define CONFIG_HIGH_BATS 1 /* High BATs supported */
31d82672 BB	35
12b43d51 WD	36	/* Input clock running at 60Mhz, read Hid1 for the CPU multiplier to
12b43d51 WD	37	determine the CPU speed. */
6d0f6bcf JCPV	38	#define CONFIG_SYS_MPC8220_CLKIN 60000000 /* ... running at 60MHz */
6d0f6bcf JCPV	39	#define CONFIG_SYS_MPC8220_SYSPLL_VCO_MULTIPLIER 8 /* VCO multiplier can't be read from any register */
12b43d51 WD	40
	41	#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
	42	#define BOOTFLAG_WARM 0x02 /* Software reboot */
	43
12b43d51 WD	44	/*
	45	* Serial console configuration
	46	*/
	47	#define CONFIG_PSC_CONSOLE 1 /* console is on PSC */
	48
	49	#define CONFIG_BAUDRATE 115200 /* ... at 115200 bps */
6d0f6bcf	50	#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 }
12b43d51	51
7680c140 WD	52	/* PCI */
	53	#define CONFIG_PCI 1
	54	#define CONFIG_PCI_PNP 1
	55
	56	#define CONFIG_PCI_MEM_BUS 0x80000000
	57	#define CONFIG_PCI_MEM_PHYS CONFIG_PCI_MEM_BUS
	58	#define CONFIG_PCI_MEM_SIZE 0x10000000
	59
	60	#define CONFIG_PCI_IO_BUS 0x71000000
	61	#define CONFIG_PCI_IO_PHYS CONFIG_PCI_IO_BUS
	62	#define CONFIG_PCI_IO_SIZE 0x01000000
	63
	64	#define CONFIG_PCI_CFG_BUS 0x70000000
	65	#define CONFIG_PCI_CFG_PHYS CONFIG_PCI_CFG_BUS
	66	#define CONFIG_PCI_CFG_SIZE 0x01000000
	67
46da1e96	68
079a136c JL	69	/*
	70	* BOOTP options
	71	*/
	72	#define CONFIG_BOOTP_BOOTFILESIZE
	73	#define CONFIG_BOOTP_BOOTPATH
	74	#define CONFIG_BOOTP_GATEWAY
	75	#define CONFIG_BOOTP_HOSTNAME
	76
	77
12b43d51	78	/*
46da1e96	79	* Command line configuration.
12b43d51	80	*/
46da1e96 JL	81	#include <config_cmd_default.h>
	82
	83	#define CONFIG_CMD_BOOTD
	84	#define CONFIG_CMD_CACHE
	85	#define CONFIG_CMD_DHCP
	86	#define CONFIG_CMD_DIAG
	87	#define CONFIG_CMD_ELF
	88	#define CONFIG_CMD_I2C
	89	#define CONFIG_CMD_NET
	90	#define CONFIG_CMD_NFS
	91	#define CONFIG_CMD_PCI
	92	#define CONFIG_CMD_PING
	93	#define CONFIG_CMD_REGINFO
	94	#define CONFIG_CMD_SDRAM
	95	#define CONFIG_CMD_SNTP
	96
12b43d51 WD	97
	98	/*
	99	* Default Environment
	100	*/
	101	#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
	102	#define CONFIG_HOSTNAME sorcery
	103
	104	#define CONFIG_PREBOOT "echo;" \
32bf3d14	105	"echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
12b43d51 WD	106	"echo"
	107
	108	#undef CONFIG_BOOTARGS
	109
	110	#define CONFIG_EXTRA_ENV_SETTINGS \
	111	"netdev=eth0\0" \
	112	"nfsargs=setenv bootargs root=/dev/nfs rw " \
	113	"nfsroot=$serverip:$rootpath\0" \
	114	"ramargs=setenv bootargs root=/dev/ram rw\0" \
	115	"addip=setenv bootargs $bootargs " \
	116	"ip=$ipaddr:$serverip:$gatewayip:$netmask" \
	117	":$hostname:$netdev:off panic=1\0" \
	118	"flash_nfs=run nfsargs addip;" \
	119	"bootm $kernel_addr\0" \
	120	"flash_self=run ramargs addip;" \
	121	"bootm $kernel_addr $ramdisk_addr\0" \
	122	"net_nfs=tftp 200000 $bootfile;run nfsargs addip;bootm\0" \
	123	"rootpath=/opt/eldk/ppc_82xx\0" \
	124	"bootfile=/tftpboot/sorcery/uImage\0" \
	125	"kernel_addr=FFE00000\0" \
	126	"ramdisk_addr=FFB00000\0" \
	127	""
	128	#define CONFIG_BOOTCOMMAND "run flash_self"
	129
	130	#define CONFIG_TIMESTAMP /* Print image info with timestamp */
	131
	132	#define CONFIG_NET_MULTI
7680c140	133	#define CONFIG_EEPRO100
12b43d51 WD	134
	135	/*
	136	* I2C configuration
	137	*/
	138	#define CONFIG_HARD_I2C 1
6d0f6bcf JCPV	139	#define CONFIG_SYS_I2C_MODULE 1
	140	#define CONFIG_SYS_I2C_SPEED 100000 /* 100 kHz */
	141	#define CONFIG_SYS_I2C_SLAVE 0x7F
12b43d51 WD	142
12b43d51 WD	143	/* Use the HUSH parser */
6d0f6bcf JCPV	144	#define CONFIG_SYS_HUSH_PARSER
	145	#ifdef CONFIG_SYS_HUSH_PARSER
	146	#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
12b43d51 WD	147	#endif
	148
	149	/*
	150	* Flexbus Chipselect configuration
3c2b3d45 WD	151	* Beware: Some CS# seem to be mandatory (if these CS# are not set,
3c2b3d45 WD	152	* board can hang-up in unpredictable place).
12b43d51 WD	153	* Sorcery_Memory_Map v0.3 is possibly wrong with CPLD CS#
	154	*/
	155
	156	/* Flash */
6d0f6bcf JCPV	157	#define CONFIG_SYS_CS0_BASE 0xf800
	158	#define CONFIG_SYS_CS0_MASK 0x08000000 /* 128 MB (two chips) */
	159	#define CONFIG_SYS_CS0_CTRL 0x001019c0
12b43d51 WD	160
12b43d51 WD	161	/* NVM */
6d0f6bcf JCPV	162	#define CONFIG_SYS_CS1_BASE 0xf7e8
	163	#define CONFIG_SYS_CS1_MASK 0x00040000 /* 256K */
	164	#define CONFIG_SYS_CS1_CTRL 0x00101940 /* 8bit port size */
12b43d51 WD	165
12b43d51 WD	166	/* Atlas2 + Gemini */
6d0f6bcf JCPV	167	#define CONFIG_SYS_CS2_BASE 0xf7e7
	168	#define CONFIG_SYS_CS2_MASK 0x00010000 /* 64K*/
	169	#define CONFIG_SYS_CS2_CTRL 0x001011c0 /* 16bit port size */
12b43d51 WD	170
12b43d51 WD	171	/* CAN Controller */
6d0f6bcf JCPV	172	#define CONFIG_SYS_CS3_BASE 0xf7e6
	173	#define CONFIG_SYS_CS3_MASK 0x00010000 /* 64K */
	174	#define CONFIG_SYS_CS3_CTRL 0x00102140 /* 8Bit port size */
12b43d51 WD	175
12b43d51 WD	176	/* Foreign interface */
6d0f6bcf JCPV	177	#define CONFIG_SYS_CS4_BASE 0xf7e5
	178	#define CONFIG_SYS_CS4_MASK 0x00010000 /* 64K */
	179	#define CONFIG_SYS_CS4_CTRL 0x00101dc0 /* 16bit port size */
12b43d51	180
7680c140	181	/* CPLD */
6d0f6bcf JCPV	182	#define CONFIG_SYS_CS5_BASE 0xf7e4
	183	#define CONFIG_SYS_CS5_MASK 0x00010000 /* 64K */
	184	#define CONFIG_SYS_CS5_CTRL 0x001000c0 /* 16bit port size */
12b43d51	185
6d0f6bcf JCPV	186	#define CONFIG_SYS_FLASH0_BASE (CONFIG_SYS_CS0_BASE << 16)
6d0f6bcf JCPV	187	#define CONFIG_SYS_FLASH_BASE (CONFIG_SYS_FLASH0_BASE)
12b43d51	188
6d0f6bcf JCPV	189	#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max num of flash banks */
6d0f6bcf JCPV	190	#define CONFIG_SYS_MAX_FLASH_SECT 512 /* max num of sects on one chip */
12b43d51	191
00b1883a	192	#define CONFIG_FLASH_CFI_DRIVER
6d0f6bcf JCPV	193	#define CONFIG_SYS_FLASH_CFI
	194	#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE, \
	195	CONFIG_SYS_FLASH_BASE+0x04000000 } /* two banks */
12b43d51 WD	196
	197	/*
	198	* Environment settings
	199	*/
5a1aceb0	200	#define CONFIG_ENV_IS_IN_FLASH 1
6d0f6bcf	201	#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x8000000 - 0x40000)
0e8d1586 JCPV	202	#define CONFIG_ENV_SIZE 0x4000 /* 16K */
	203	#define CONFIG_ENV_SECT_SIZE 0x20000
	204	#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + 0x20000)
	205	#define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE
12b43d51 WD	206
	207	#define CONFIG_ENV_OVERWRITE 1
	208
5a1aceb0	209	#if defined CONFIG_ENV_IS_IN_FLASH
9314cee6	210	#undef CONFIG_ENV_IS_IN_NVRAM
bb1f8b4f	211	#undef CONFIG_ENV_IS_IN_EEPROM
9314cee6	212	#elif defined CONFIG_ENV_IS_IN_NVRAM
5a1aceb0	213	#undef CONFIG_ENV_IS_IN_FLASH
bb1f8b4f JCPV	214	#undef CONFIG_ENV_IS_IN_EEPROM
bb1f8b4f JCPV	215	#elif defined CONFIG_ENV_IS_IN_EEPROM
9314cee6	216	#undef CONFIG_ENV_IS_IN_NVRAM
5a1aceb0	217	#undef CONFIG_ENV_IS_IN_FLASH
12b43d51 WD	218	#endif
	219
	220	/*
	221	* Memory map
	222	*/
6d0f6bcf JCPV	223	#define CONFIG_SYS_MBAR 0xF0000000
	224	#define CONFIG_SYS_SDRAM_BASE 0x00000000
	225	#define CONFIG_SYS_DEFAULT_MBAR 0x80000000
	226	#define CONFIG_SYS_SRAM_BASE (CONFIG_SYS_MBAR + 0x20000)
	227	#define CONFIG_SYS_SRAM_SIZE 0x8000
12b43d51 WD	228
12b43d51 WD	229	/* Use SRAM until RAM will be available */
6d0f6bcf JCPV	230	#define CONFIG_SYS_INIT_RAM_ADDR (CONFIG_SYS_MBAR + 0x20000)
6d0f6bcf JCPV	231	#define CONFIG_SYS_INIT_RAM_END 0x8000 /* End of used area in DPRAM */
12b43d51	232
6d0f6bcf JCPV	233	#define CONFIG_SYS_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
	234	#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
	235	#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
12b43d51	236
6d0f6bcf JCPV	237	#define CONFIG_SYS_MONITOR_BASE TEXT_BASE
	238	#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
	239	# define CONFIG_SYS_RAMBOOT 1
12b43d51 WD	240	#endif
12b43d51 WD	241
6d0f6bcf JCPV	242	#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
	243	#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
	244	#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
12b43d51 WD	245
12b43d51 WD	246	/* SDRAM configuration (for SPD) */
6d0f6bcf JCPV	247	#define CONFIG_SYS_SDRAM_TOTAL_BANKS 1
	248	#define CONFIG_SYS_SDRAM_SPD_I2C_ADDR 0x50 /* 7bit */
	249	#define CONFIG_SYS_SDRAM_SPD_SIZE 0x100
	250	#define CONFIG_SYS_SDRAM_CAS_LATENCY 5 /* (CL=2.5)x2 */
12b43d51	251
7680c140	252	/* SDRAM drive strength register (for SSTL_2 class II)*/
6d0f6bcf	253	#define CONFIG_SYS_SDRAM_DRIVE_STRENGTH ((DRIVE_STRENGTH_HIGH << SDRAMDS_SBE_SHIFT) \| \
7680c140 WD	254	(DRIVE_STRENGTH_HIGH << SDRAMDS_SBC_SHIFT) \| \
	255	(DRIVE_STRENGTH_HIGH << SDRAMDS_SBA_SHIFT) \| \
	256	(DRIVE_STRENGTH_HIGH << SDRAMDS_SBS_SHIFT) \| \
	257	(DRIVE_STRENGTH_HIGH << SDRAMDS_SBD_SHIFT))
	258
12b43d51 WD	259	/*
	260	* Ethernet configuration
	261	*/
	262	#define CONFIG_MPC8220_FEC 1
	263	#define CONFIG_FEC_10MBIT 1 /* Workaround for FEC 100Mbit problem */
	264	#define CONFIG_PHY_ADDR 0x1F
f60ba0d3	265	#define CONFIG_MII 1
12b43d51 WD	266
	267	/*
	268	* Miscellaneous configurable options
	269	*/
6d0f6bcf JCPV	270	#define CONFIG_SYS_LONGHELP /* undef to save memory */
6d0f6bcf JCPV	271	#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
46da1e96	272	#if defined(CONFIG_CMD_KGDB)
6d0f6bcf	273	#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
12b43d51	274	#else
6d0f6bcf	275	#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
12b43d51	276	#endif
6d0f6bcf JCPV	277	#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
	278	#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
	279	#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
12b43d51	280
6d0f6bcf JCPV	281	#define CONFIG_SYS_MEMTEST_START 0x00100000 /* memtest works on */
6d0f6bcf JCPV	282	#define CONFIG_SYS_MEMTEST_END 0x00f00000 /* 1 ... 15 MB in DRAM */
12b43d51	283
6d0f6bcf	284	#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
12b43d51	285
6d0f6bcf	286	#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */
12b43d51	287
6d0f6bcf	288	#define CONFIG_SYS_CACHELINE_SIZE 32 /* For MPC8220 CPUs */
46da1e96	289	#if defined(CONFIG_CMD_KGDB)
6d0f6bcf	290	# define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */
46da1e96 JL	291	#endif
46da1e96 JL	292
12b43d51 WD	293	/*
	294	* Various low-level settings
	295	*/
6d0f6bcf JCPV	296	#define CONFIG_SYS_HID0_INIT 0
6d0f6bcf JCPV	297	#define CONFIG_SYS_HID0_FINAL 0
12b43d51	298
7680c140	299	/*
6d0f6bcf JCPV	300	#define CONFIG_SYS_HID0_INIT HID0_ICE \| HID0_ICFI
6d0f6bcf JCPV	301	#define CONFIG_SYS_HID0_FINAL HID0_ICE
7680c140 WD	302	*/
7680c140 WD	303
12b43d51	304	#endif /* __CONFIG_H */