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eece159c WD |
1 | /* |
2 | * (C) Copyright 2003-2005 | |
3 | * Wolfgang Denk, DENX Software Engineering, wd@denx.de. | |
4 | * | |
5 | * (C) Copyright 2004-2005 | |
6 | * Martin Krause, TQ-Systems GmbH, martin.krause@tqs.de | |
7 | * | |
8 | * See file CREDITS for list of people who contributed to this | |
9 | * project. | |
10 | * | |
11 | * This program is free software; you can redistribute it and/or | |
12 | * modify it under the terms of the GNU General Public License as | |
13 | * published by the Free Software Foundation; either version 2 of | |
14 | * the License, or (at your option) any later version. | |
15 | * | |
16 | * This program is distributed in the hope that it will be useful, | |
17 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
18 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
19 | * GNU General Public License for more details. | |
20 | * | |
21 | * You should have received a copy of the GNU General Public License | |
22 | * along with this program; if not, write to the Free Software | |
23 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | |
24 | * MA 02111-1307 USA | |
25 | */ | |
26 | ||
27 | #ifndef __CONFIG_H | |
28 | #define __CONFIG_H | |
29 | ||
30 | /* | |
31 | * High Level Configuration Options | |
32 | * (easy to change) | |
33 | */ | |
34 | ||
35 | #define CONFIG_MPC5xxx 1 /* This is an MPC5xxx CPU */ | |
36 | #define CONFIG_MPC5200 1 /* (more precisely an MPC5200 CPU) */ | |
37 | #define CONFIG_TQM5200 1 /* ... on TQM5200 module */ | |
38 | #undef CONFIG_TQM5200_REV100 /* define for revision 100 modules */ | |
39 | #define CONFIG_STK52XX 1 /* ... on a STK52XX base board */ | |
40 | #define CONFIG_STK52XX_REV100 1 /* define for revision 100 baseboards */ | |
41 | ||
6d0f6bcf | 42 | #define CONFIG_SYS_MPC5XXX_CLKIN 33000000 /* ... running at 33.000000MHz */ |
eece159c | 43 | |
31d82672 BB |
44 | #define CONFIG_HIGH_BATS 1 /* High BATs supported */ |
45 | ||
eece159c WD |
46 | /* |
47 | * Serial console configuration | |
48 | */ | |
49 | #define CONFIG_PSC_CONSOLE 6 /* console is on PSC6 */ | |
50 | #define CONFIG_BAUDRATE 115200 /* ... at 115200 bps */ | |
6d0f6bcf | 51 | #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 } |
eece159c WD |
52 | |
53 | #ifdef CONFIG_STK52XX | |
54 | #undef CONFIG_PS2KBD /* AT-PS/2 Keyboard */ | |
55 | #define CONFIG_PS2MULT /* .. on PS/2 Multiplexer */ | |
56 | #define CONFIG_PS2SERIAL 6 /* .. on PSC6 */ | |
6d0f6bcf | 57 | #define CONFIG_PS2MULT_DELAY (CONFIG_SYS_HZ/2) /* Initial delay */ |
eece159c WD |
58 | #define CONFIG_BOARD_EARLY_INIT_R |
59 | #endif /* CONFIG_STK52XX */ | |
60 | ||
61 | /* | |
62 | * PCI Mapping: | |
63 | * 0x40000000 - 0x4fffffff - PCI Memory | |
64 | * 0x50000000 - 0x50ffffff - PCI IO Space | |
65 | */ | |
66 | #ifdef CONFIG_STK52XX | |
67 | #define CONFIG_PCI 1 | |
68 | #define CONFIG_PCI_PNP 1 | |
69 | /* #define CONFIG_PCI_SCAN_SHOW 1 */ | |
70 | ||
71 | #define CONFIG_PCI_MEM_BUS 0x40000000 | |
72 | #define CONFIG_PCI_MEM_PHYS CONFIG_PCI_MEM_BUS | |
73 | #define CONFIG_PCI_MEM_SIZE 0x10000000 | |
74 | ||
75 | #define CONFIG_PCI_IO_BUS 0x50000000 | |
76 | #define CONFIG_PCI_IO_PHYS CONFIG_PCI_IO_BUS | |
77 | #define CONFIG_PCI_IO_SIZE 0x01000000 | |
78 | ||
79 | #define CONFIG_NET_MULTI 1 | |
80 | #define CONFIG_EEPRO100 1 | |
6d0f6bcf | 81 | #define CONFIG_SYS_RX_ETH_BUFFER 8 /* use 8 rx buffer on eepro100 */ |
eece159c WD |
82 | #define CONFIG_NS8382X 1 |
83 | #endif /* CONFIG_STK52XX */ | |
84 | ||
eece159c WD |
85 | /* |
86 | * Video console | |
87 | */ | |
88 | #if 1 | |
89 | #define CONFIG_VIDEO | |
90 | #define CONFIG_VIDEO_SM501 | |
91 | #define CONFIG_VIDEO_SM501_32BPP | |
92 | #define CONFIG_CFB_CONSOLE | |
93 | #define CONFIG_VIDEO_LOGO | |
94 | #define CONFIG_VGA_AS_SINGLE_DEVICE | |
95 | #define CONFIG_CONSOLE_EXTRA_INFO | |
96 | #define CONFIG_VIDEO_SW_CURSOR | |
97 | #define CONFIG_SPLASH_SCREEN | |
6d0f6bcf | 98 | #define CONFIG_SYS_CONSOLE_IS_IN_ENV |
eece159c WD |
99 | #endif |
100 | ||
eece159c WD |
101 | /* Partitions */ |
102 | #define CONFIG_MAC_PARTITION | |
103 | #define CONFIG_DOS_PARTITION | |
104 | #define CONFIG_ISO_PARTITION | |
105 | ||
106 | /* USB */ | |
107 | #ifdef CONFIG_STK52XX | |
108 | #define CONFIG_USB_OHCI | |
eece159c | 109 | #define CONFIG_USB_STORAGE |
eece159c WD |
110 | #endif |
111 | ||
112 | /* POST support */ | |
6d0f6bcf JCPV |
113 | #define CONFIG_POST (CONFIG_SYS_POST_MEMORY | \ |
114 | CONFIG_SYS_POST_CPU | \ | |
115 | CONFIG_SYS_POST_I2C) | |
eece159c WD |
116 | |
117 | #ifdef CONFIG_POST | |
eece159c WD |
118 | /* preserve space for the post_word at end of on-chip SRAM */ |
119 | #define MPC5XXX_SRAM_POST_SIZE MPC5XXX_SRAM_SIZE-4 | |
eece159c WD |
120 | #endif |
121 | ||
eece159c | 122 | |
079a136c JL |
123 | /* |
124 | * BOOTP options | |
125 | */ | |
126 | #define CONFIG_BOOTP_BOOTFILESIZE | |
127 | #define CONFIG_BOOTP_BOOTPATH | |
128 | #define CONFIG_BOOTP_GATEWAY | |
129 | #define CONFIG_BOOTP_HOSTNAME | |
130 | ||
131 | ||
eece159c | 132 | /* |
46da1e96 | 133 | * Command line configuration. |
eece159c | 134 | */ |
46da1e96 JL |
135 | #include <config_cmd_default.h> |
136 | ||
af075ee9 JL |
137 | #define CONFIG_CMD_ASKENV |
138 | #define CONFIG_CMD_DATE | |
139 | #define CONFIG_CMD_DHCP | |
140 | #define CONFIG_CMD_ECHO | |
141 | #define CONFIG_CMD_EEPROM | |
142 | #define CONFIG_CMD_I2C | |
143 | #define CONFIG_CMD_MII | |
144 | #define CONFIG_CMD_NFS | |
145 | #define CONFIG_CMD_PING | |
146 | #define CONFIG_CMD_REGINFO | |
147 | #define CONFIG_CMD_SNTP | |
148 | ||
46da1e96 JL |
149 | #if defined(CONFIG_MINIFAP) || defined(CONFIG_STK52XX) |
150 | #define CONFIG_CMD_IDE | |
151 | #define CONFIG_CMD_FAT | |
152 | #define CONFIG_CMD_EXT2 | |
153 | #endif | |
154 | ||
155 | #ifdef CONFIG_STK52XX | |
156 | #define CONFIG_CMD_USB | |
157 | #define CONFIG_CMD_FAT | |
158 | #endif | |
159 | ||
160 | #ifdef CONFIG_VIDEO | |
161 | #define CONFIG_CMD_BMP | |
162 | #endif | |
163 | ||
164 | #ifdef CONFIG_PCI | |
165 | #define CONFIG_CMD_PCI | |
f33fca22 | 166 | #define CONFIG_PCIAUTO_SKIP_HOST_BRIDGE 1 |
46da1e96 JL |
167 | #endif |
168 | ||
af075ee9 JL |
169 | #ifdef CONFIG_POST |
170 | #define CONFIG_CMD_DIAG | |
171 | #endif | |
46da1e96 | 172 | |
eece159c WD |
173 | |
174 | #define CONFIG_TIMESTAMP /* display image timestamps */ | |
175 | ||
14d0a02a | 176 | #if (CONFIG_SYS_TEXT_BASE == 0xFC000000) /* Boot low */ |
6d0f6bcf | 177 | # define CONFIG_SYS_LOWBOOT 1 |
eece159c WD |
178 | #endif |
179 | ||
180 | /* | |
181 | * Autobooting | |
182 | */ | |
183 | #define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ | |
184 | ||
185 | #define CONFIG_PREBOOT "echo;" \ | |
32bf3d14 | 186 | "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \ |
eece159c WD |
187 | "echo" |
188 | ||
189 | #undef CONFIG_BOOTARGS | |
190 | ||
eece159c WD |
191 | #define CONFIG_EXTRA_ENV_SETTINGS \ |
192 | "netdev=eth0\0" \ | |
193 | "rootpath=/opt/eldk/ppc_6xx\0" \ | |
194 | "ramargs=setenv bootargs root=/dev/ram rw\0" \ | |
195 | "nfsargs=setenv bootargs root=/dev/nfs rw " \ | |
fe126d8b WD |
196 | "nfsroot=${serverip}:${rootpath}\0" \ |
197 | "addip=setenv bootargs ${bootargs} " \ | |
198 | "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ | |
199 | ":${hostname}:${netdev}:off panic=1\0" \ | |
eece159c | 200 | "flash_self=run ramargs addip;" \ |
fe126d8b | 201 | "bootm ${kernel_addr} ${ramdisk_addr}\0" \ |
eece159c | 202 | "flash_nfs=run nfsargs addip;" \ |
fe126d8b WD |
203 | "bootm ${kernel_addr}\0" \ |
204 | "net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \ | |
eece159c | 205 | "bootfile=/tftpboot/tqm5200/uImage\0" \ |
fe126d8b | 206 | "load=tftp 200000 ${u-boot}\0" \ |
cd65a3dc | 207 | "u-boot=/tftpboot/tqm5200/u-boot.bin\0" \ |
eece159c WD |
208 | "update=protect off FC000000 FC05FFFF;" \ |
209 | "erase FC000000 FC05FFFF;" \ | |
fe126d8b | 210 | "cp.b 200000 FC000000 ${filesize};" \ |
eece159c WD |
211 | "protect on FC000000 FC05FFFF\0" \ |
212 | "" | |
213 | ||
214 | #define CONFIG_BOOTCOMMAND "run net_nfs" | |
215 | ||
216 | /* | |
217 | * IPB Bus clocking configuration. | |
218 | */ | |
6d0f6bcf | 219 | #define CONFIG_SYS_IPBCLK_EQUALS_XLBCLK /* define for 133MHz speed */ |
eece159c | 220 | |
6d0f6bcf | 221 | #if defined(CONFIG_SYS_IPBCLK_EQUALS_XLBCLK) |
eece159c WD |
222 | /* |
223 | * PCI Bus clocking configuration | |
224 | * | |
225 | * Actually a PCI Clock of 66 MHz is only set (in cpu_init.c) if | |
6d0f6bcf | 226 | * CONFIG_SYS_IPBCLK_EQUALS_XLBCLK is defined. This is because a PCI Clock |
c99512d6 | 227 | * of 66 MHz yet hasn't been tested with a IPB Bus Clock of 66 MHz. |
eece159c | 228 | */ |
6d0f6bcf | 229 | #define CONFIG_SYS_PCICLK_EQUALS_IPBCLK_DIV2 /* define for 66MHz speed */ |
eece159c WD |
230 | #endif |
231 | ||
232 | /* | |
233 | * I2C configuration | |
234 | */ | |
235 | #define CONFIG_HARD_I2C 1 /* I2C with hardware support */ | |
236 | #ifdef CONFIG_TQM5200_REV100 | |
6d0f6bcf | 237 | #define CONFIG_SYS_I2C_MODULE 1 /* Select I2C module #1 for rev. 100 board */ |
eece159c | 238 | #else |
6d0f6bcf | 239 | #define CONFIG_SYS_I2C_MODULE 2 /* Select I2C module #2 for all other revs */ |
eece159c WD |
240 | #endif |
241 | ||
242 | /* | |
243 | * I2C clock frequency | |
244 | * | |
245 | * Please notice, that the resulting clock frequency could differ from the | |
246 | * configured value. This is because the I2C clock is derived from system | |
247 | * clock over a frequency divider with only a few divider values. U-boot | |
6d0f6bcf | 248 | * calculates the best approximation for CONFIG_SYS_I2C_SPEED. However the calculated |
eece159c WD |
249 | * approximation allways lies below the configured value, never above. |
250 | */ | |
6d0f6bcf JCPV |
251 | #define CONFIG_SYS_I2C_SPEED 100000 /* 100 kHz */ |
252 | #define CONFIG_SYS_I2C_SLAVE 0x7F | |
eece159c WD |
253 | |
254 | /* | |
255 | * EEPROM configuration for onboard EEPROM M24C32 (M24C64 should work | |
256 | * also). For other EEPROMs configuration should be verified. On Mini-FAP the | |
257 | * EEPROM (24C64) is on the same I2C address (but on other I2C bus), so the | |
258 | * same configuration could be used. | |
259 | */ | |
6d0f6bcf JCPV |
260 | #define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* 1010000x */ |
261 | #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 | |
262 | #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 5 /* =32 Bytes per write */ | |
263 | #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 20 | |
eece159c WD |
264 | |
265 | /* | |
266 | * HW-Monitor configuration on Mini-FAP | |
267 | */ | |
268 | #if defined (CONFIG_MINIFAP) | |
6d0f6bcf | 269 | #define CONFIG_SYS_I2C_HWMON_ADDR 0x2C |
eece159c WD |
270 | #endif |
271 | ||
272 | /* List of I2C addresses to be verified by POST */ | |
eece159c | 273 | #if defined (CONFIG_MINIFAP) |
60aaaa07 PT |
274 | #undef CONFIG_SYS_POST_I2C_ADDRS |
275 | #define CONFIG_SYS_POST_I2C_ADDRS {CONFIG_SYS_I2C_EEPROM_ADDR, \ | |
276 | CONFIG_SYS_I2C_HWMON_ADDR, \ | |
277 | CONFIG_SYS_I2C_SLAVE} | |
eece159c WD |
278 | #endif |
279 | ||
280 | /* | |
281 | * Flash configuration | |
282 | */ | |
14d0a02a | 283 | #define CONFIG_SYS_FLASH_BASE CONFIG_SYS_TEXT_BASE /* 0xFC000000 */ |
eece159c WD |
284 | |
285 | /* use CFI flash driver if no module variant is spezified */ | |
6d0f6bcf | 286 | #define CONFIG_SYS_FLASH_CFI 1 /* Flash is CFI conformant */ |
00b1883a | 287 | #define CONFIG_FLASH_CFI_DRIVER 1 /* Use the common driver */ |
6d0f6bcf JCPV |
288 | #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_BOOTCS_START } |
289 | #define CONFIG_SYS_FLASH_EMPTY_INFO | |
290 | #define CONFIG_SYS_FLASH_SIZE 0x04000000 /* 64 MByte */ | |
291 | #define CONFIG_SYS_MAX_FLASH_SECT 512 /* max num of sects on one chip */ | |
292 | #undef CONFIG_SYS_FLASH_USE_BUFFER_WRITE /* not supported yet for AMD */ | |
293 | ||
294 | #if !defined(CONFIG_SYS_LOWBOOT) | |
295 | #define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x00760000 + 0x00800000) | |
296 | #else /* CONFIG_SYS_LOWBOOT */ | |
297 | #define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x00060000) | |
298 | #endif /* CONFIG_SYS_LOWBOOT */ | |
299 | #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of flash banks | |
eece159c | 300 | (= chip selects) */ |
6d0f6bcf JCPV |
301 | #define CONFIG_SYS_FLASH_ERASE_TOUT 240000 /* Flash Erase Timeout (in ms) */ |
302 | #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (in ms) */ | |
eece159c WD |
303 | |
304 | ||
305 | /* | |
306 | * Environment settings | |
307 | */ | |
5a1aceb0 | 308 | #define CONFIG_ENV_IS_IN_FLASH 1 |
0e8d1586 JCPV |
309 | #define CONFIG_ENV_SIZE 0x10000 |
310 | #define CONFIG_ENV_SECT_SIZE 0x20000 | |
311 | #define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE) | |
312 | #define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE) | |
eece159c WD |
313 | |
314 | /* | |
315 | * Memory map | |
316 | */ | |
6d0f6bcf JCPV |
317 | #define CONFIG_SYS_MBAR 0xF0000000 |
318 | #define CONFIG_SYS_SDRAM_BASE 0x00000000 | |
319 | #define CONFIG_SYS_DEFAULT_MBAR 0x80000000 | |
eece159c WD |
320 | |
321 | /* Use ON-Chip SRAM until RAM will be available */ | |
6d0f6bcf | 322 | #define CONFIG_SYS_INIT_RAM_ADDR MPC5XXX_SRAM |
eece159c WD |
323 | #ifdef CONFIG_POST |
324 | /* preserve space for the post_word at end of on-chip SRAM */ | |
553f0982 | 325 | #define CONFIG_SYS_INIT_RAM_SIZE MPC5XXX_SRAM_POST_SIZE |
eece159c | 326 | #else |
553f0982 | 327 | #define CONFIG_SYS_INIT_RAM_SIZE MPC5XXX_SRAM_SIZE |
eece159c WD |
328 | #endif |
329 | ||
330 | ||
25ddd1fb | 331 | #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) |
6d0f6bcf | 332 | #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET |
eece159c | 333 | |
14d0a02a | 334 | #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE |
6d0f6bcf JCPV |
335 | #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE) |
336 | # define CONFIG_SYS_RAMBOOT 1 | |
eece159c WD |
337 | #endif |
338 | ||
6d0f6bcf JCPV |
339 | #define CONFIG_SYS_MONITOR_LEN (384 << 10) /* Reserve 384 kB for Monitor */ |
340 | #define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ | |
341 | #define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ | |
eece159c WD |
342 | |
343 | /* | |
344 | * Ethernet configuration | |
345 | */ | |
346 | #define CONFIG_MPC5xxx_FEC 1 | |
347 | /* | |
348 | * Define CONFIG_FEC_10MBIT to force FEC at 10Mb | |
349 | */ | |
350 | /* #define CONFIG_FEC_10MBIT 1 */ | |
351 | #define CONFIG_PHY_ADDR 0x00 | |
352 | ||
353 | /* | |
354 | * GPIO configuration | |
355 | * | |
356 | * use pin gpio_wkup_6 as second SDRAM chip select (mem_cs1): | |
357 | * Bit 0 (mask: 0x80000000): 1 | |
358 | * use ALT CAN position: Bits 2-3 (mask: 0x30000000): | |
359 | * 00 -> No Alternatives, CAN1/2 on PSC2 according to PSC2 setting. | |
360 | * 01 -> CAN1 on I2C1, CAN2 on Tmr0/1. | |
361 | * Use for REV200 STK52XX boards. Do not use with REV100 modules | |
362 | * (because, there I2C1 is used as I2C bus) | |
363 | * use PSC1 as UART: Bits 28-31 (mask: 0x00000007): 0100 | |
364 | * use PSC2 as CAN: Bits 25:27 (mask: 0x00000030) | |
365 | * 000 -> All PSC2 pins are GIOPs | |
366 | * 001 -> CAN1/2 on PSC2 pins | |
367 | * Use for REV100 STK52xx boards | |
368 | * use PSC6: | |
369 | * on STK52xx: | |
370 | * use as UART. Pins PSC6_0 to PSC6_3 are used. | |
371 | * Bits 9:11 (mask: 0x00700000): | |
372 | * 101 -> PSC6 : Extended POST test is not available | |
373 | * on MINI-FAP and TQM5200_IB: | |
374 | * use PSC6_0 to PSC6_3 as GPIO: Bits 9:11 (mask: 0x00700000): | |
375 | * 000 -> PSC6 could not be used as UART, CODEC or IrDA | |
376 | * GPIO on PSC6_3 is used in post_hotkeys_pressed() to enable extended POST | |
377 | * tests. | |
378 | */ | |
379 | #if defined (CONFIG_MINIFAP) | |
6d0f6bcf | 380 | # define CONFIG_SYS_GPS_PORT_CONFIG 0x91000004 |
eece159c WD |
381 | #elif defined (CONFIG_STK52XX) |
382 | # if defined (CONFIG_STK52XX_REV100) | |
6d0f6bcf | 383 | # define CONFIG_SYS_GPS_PORT_CONFIG 0x81500014 |
eece159c WD |
384 | # else /* STK52xx REV200 and above */ |
385 | # if defined (CONFIG_TQM5200_REV100) | |
386 | # error TQM5200 REV100 not supported on STK52XX REV200 or above | |
387 | # else/* TQM5200 REV200 and above */ | |
6d0f6bcf | 388 | # define CONFIG_SYS_GPS_PORT_CONFIG 0x91500004 |
eece159c WD |
389 | # endif |
390 | # endif | |
391 | #else /* TMQ5200 Inbetriebnahme-Board */ | |
6d0f6bcf | 392 | # define CONFIG_SYS_GPS_PORT_CONFIG 0x81000004 |
eece159c WD |
393 | #endif |
394 | ||
395 | /* | |
396 | * RTC configuration | |
397 | */ | |
398 | #define CONFIG_RTC_MPC5200 1 /* use internal MPC5200 RTC */ | |
399 | ||
400 | /* | |
401 | * Miscellaneous configurable options | |
402 | */ | |
6d0f6bcf JCPV |
403 | #define CONFIG_SYS_LONGHELP /* undef to save memory */ |
404 | #define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ | |
46da1e96 | 405 | #if defined(CONFIG_CMD_KGDB) |
6d0f6bcf | 406 | #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ |
eece159c | 407 | #else |
6d0f6bcf | 408 | #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ |
eece159c | 409 | #endif |
6d0f6bcf JCPV |
410 | #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ |
411 | #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ | |
412 | #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ | |
eece159c WD |
413 | |
414 | /* Enable an alternate, more extensive memory test */ | |
6d0f6bcf | 415 | #define CONFIG_SYS_ALT_MEMTEST |
eece159c | 416 | |
6d0f6bcf JCPV |
417 | #define CONFIG_SYS_MEMTEST_START 0x00100000 /* memtest works on */ |
418 | #define CONFIG_SYS_MEMTEST_END 0x00f00000 /* 1 ... 15 MB in DRAM */ | |
eece159c | 419 | |
6d0f6bcf | 420 | #define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */ |
eece159c | 421 | |
6d0f6bcf | 422 | #define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */ |
eece159c | 423 | |
6d0f6bcf | 424 | #define CONFIG_SYS_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */ |
46da1e96 | 425 | #if defined(CONFIG_CMD_KGDB) |
6d0f6bcf | 426 | # define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */ |
46da1e96 JL |
427 | #endif |
428 | ||
eece159c | 429 | /* |
079a136c | 430 | * Enable loopw command. |
eece159c WD |
431 | */ |
432 | #define CONFIG_LOOPW | |
433 | ||
434 | /* | |
435 | * Various low-level settings | |
436 | */ | |
6d0f6bcf JCPV |
437 | #define CONFIG_SYS_HID0_INIT HID0_ICE | HID0_ICFI |
438 | #define CONFIG_SYS_HID0_FINAL HID0_ICE | |
eece159c | 439 | |
6d0f6bcf JCPV |
440 | #define CONFIG_SYS_BOOTCS_START CONFIG_SYS_FLASH_BASE |
441 | #define CONFIG_SYS_BOOTCS_SIZE CONFIG_SYS_FLASH_SIZE | |
442 | #ifdef CONFIG_SYS_PCICLK_EQUALS_IPBCLK_DIV2 | |
443 | #define CONFIG_SYS_BOOTCS_CFG 0x0008DF30 /* for pci_clk = 66 MHz */ | |
eece159c | 444 | #else |
6d0f6bcf | 445 | #define CONFIG_SYS_BOOTCS_CFG 0x0004DF30 /* for pci_clk = 33 MHz */ |
eece159c | 446 | #endif |
6d0f6bcf JCPV |
447 | #define CONFIG_SYS_CS0_START CONFIG_SYS_FLASH_BASE |
448 | #define CONFIG_SYS_CS0_SIZE CONFIG_SYS_FLASH_SIZE | |
eece159c | 449 | |
eece159c | 450 | #define CONFIG_LAST_STAGE_INIT |
eece159c WD |
451 | |
452 | /* | |
453 | * SRAM - Do not map below 2 GB in address space, because this area is used | |
454 | * for SDRAM autosizing. | |
455 | */ | |
6d0f6bcf JCPV |
456 | #define CONFIG_SYS_CS2_START 0xE5000000 |
457 | #define CONFIG_SYS_CS2_SIZE 0x100000 /* 1 MByte */ | |
458 | #define CONFIG_SYS_CS2_CFG 0x0004D930 | |
eece159c WD |
459 | |
460 | /* | |
461 | * Grafic controller - Do not map below 2 GB in address space, because this | |
462 | * area is used for SDRAM autosizing. | |
463 | */ | |
eece159c | 464 | #define SM501_FB_BASE 0xE0000000 |
6d0f6bcf JCPV |
465 | #define CONFIG_SYS_CS1_START (SM501_FB_BASE) |
466 | #define CONFIG_SYS_CS1_SIZE 0x4000000 /* 64 MByte */ | |
467 | #define CONFIG_SYS_CS1_CFG 0x8F48FF70 | |
468 | #define SM501_MMIO_BASE CONFIG_SYS_CS1_START + 0x03E00000 | |
eece159c | 469 | |
6d0f6bcf JCPV |
470 | #define CONFIG_SYS_CS_BURST 0x00000000 |
471 | #define CONFIG_SYS_CS_DEADCYCLE 0x33333311 /* 1 dead cycle for flash and SM501 */ | |
eece159c | 472 | |
6d0f6bcf | 473 | #define CONFIG_SYS_RESET_ADDRESS 0xff000000 |
eece159c WD |
474 | |
475 | /*----------------------------------------------------------------------- | |
476 | * USB stuff | |
477 | *----------------------------------------------------------------------- | |
478 | */ | |
479 | #define CONFIG_USB_CLOCK 0x0001BBBB | |
480 | #define CONFIG_USB_CONFIG 0x00001000 | |
481 | ||
482 | /*----------------------------------------------------------------------- | |
483 | * IDE/ATA stuff Supports IDE harddisk | |
484 | *----------------------------------------------------------------------- | |
485 | */ | |
486 | ||
487 | #undef CONFIG_IDE_8xx_PCCARD /* Use IDE with PC Card Adapter */ | |
488 | ||
489 | #undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */ | |
490 | #undef CONFIG_IDE_LED /* LED for ide not supported */ | |
491 | ||
492 | #define CONFIG_IDE_RESET /* reset for ide supported */ | |
493 | #define CONFIG_IDE_PREINIT | |
494 | ||
6d0f6bcf JCPV |
495 | #define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE bus */ |
496 | #define CONFIG_SYS_IDE_MAXDEVICE 2 /* max. 2 drives per IDE bus */ | |
eece159c | 497 | |
6d0f6bcf | 498 | #define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000 |
eece159c | 499 | |
6d0f6bcf | 500 | #define CONFIG_SYS_ATA_BASE_ADDR MPC5XXX_ATA |
eece159c WD |
501 | |
502 | /* Offset for data I/O */ | |
6d0f6bcf | 503 | #define CONFIG_SYS_ATA_DATA_OFFSET (0x0060) |
eece159c WD |
504 | |
505 | /* Offset for normal register accesses */ | |
6d0f6bcf | 506 | #define CONFIG_SYS_ATA_REG_OFFSET (CONFIG_SYS_ATA_DATA_OFFSET) |
eece159c WD |
507 | |
508 | /* Offset for alternate registers */ | |
6d0f6bcf | 509 | #define CONFIG_SYS_ATA_ALT_OFFSET (0x005C) |
eece159c WD |
510 | |
511 | /* Interval between registers */ | |
6d0f6bcf | 512 | #define CONFIG_SYS_ATA_STRIDE 4 |
eece159c WD |
513 | |
514 | #endif /* __CONFIG_H */ |