[people/ms/u-boot.git] / include / configs / stm32f746-disco.h

/*
 * (C) Copyright 2016
 * Vikas Manocha, <vikas.manocha@st.com>
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

#ifndef __CONFIG_H
#define __CONFIG_H

#define CONFIG_SYS_FLASH_BASE		0x08000000
#define CONFIG_SYS_INIT_SP_ADDR		0x20050000

#ifdef CONFIG_SUPPORT_SPL
#define CONFIG_SYS_TEXT_BASE		0x08008000
#define CONFIG_SYS_LOAD_ADDR		0x08008000
#else
#define CONFIG_SYS_TEXT_BASE		CONFIG_SYS_FLASH_BASE
#define CONFIG_SYS_LOAD_ADDR		0xC0400000
#define CONFIG_LOADADDR			0xC0400000
#endif

/*
 * Configuration of the external SDRAM memory
 */
#define CONFIG_NR_DRAM_BANKS		1

#define CONFIG_SYS_MAX_FLASH_SECT	8
#define CONFIG_SYS_MAX_FLASH_BANKS	1

#define CONFIG_ENV_SIZE			(8 << 10)

#define CONFIG_STM32_FLASH

#define CONFIG_DW_GMAC_DEFAULT_DMA_PBL	(8)
#define CONFIG_DW_ALTDESCRIPTOR
#define CONFIG_MII
#define CONFIG_PHY_SMSC

#define CONFIG_STM32_HSE_HZ		25000000
#define CONFIG_SYS_CLK_FREQ		200000000 /* 200 MHz */
#define CONFIG_SYS_HZ_CLOCK		1000000	/* Timer is clocked at 1MHz */

#define CONFIG_CMDLINE_TAG
#define CONFIG_SETUP_MEMORY_TAGS
#define CONFIG_INITRD_TAG
#define CONFIG_REVISION_TAG

#define CONFIG_SYS_CBSIZE		1024

#define CONFIG_SYS_MAXARGS		16
#define CONFIG_SYS_MALLOC_LEN		(1 * 1024 * 1024)

#define CONFIG_BOOTCOMMAND						\
	"run bootcmd_romfs"

#define CONFIG_EXTRA_ENV_SETTINGS \
	"bootargs_romfs=uclinux.physaddr=0x08180000 root=/dev/mtdblock0\0" \
	"bootcmd_romfs=setenv bootargs ${bootargs} ${bootargs_romfs};" \
	"bootm 0x08044000 - 0x08042000\0"


/*
 * Command line configuration.
 */
#define CONFIG_SYS_LONGHELP
#define CONFIG_AUTO_COMPLETE
#define CONFIG_CMDLINE_EDITING
#define CONFIG_CMD_CACHE
#define CONFIG_BOARD_LATE_INIT
#define CONFIG_DISPLAY_BOARDINFO

/* For SPL */
#ifdef CONFIG_SUPPORT_SPL
#define CONFIG_SPL_STACK		CONFIG_SYS_INIT_SP_ADDR
#define CONFIG_SPL_FRAMEWORK
#define CONFIG_SPL_BOARD_INIT
#define CONFIG_SPL_TEXT_BASE		CONFIG_SYS_FLASH_BASE
#define CONFIG_SYS_MONITOR_LEN		(512 * 1024)
#define CONFIG_SYS_SPL_LEN		0x00008000
#define CONFIG_SYS_UBOOT_START		0x080083FD
#define CONFIG_SYS_UBOOT_BASE		(CONFIG_SYS_FLASH_BASE + \
					 CONFIG_SYS_SPL_LEN)

/* DT blob (fdt) address */
#define CONFIG_SYS_FDT_BASE		(CONFIG_SYS_FLASH_BASE + \
					0x1C0000)
#endif
/* For SPL ends */

#endif /* __CONFIG_H */
Commit	Line	Data
e66c49fa VM	1	/*
	2	* (C) Copyright 2016
	3	* Vikas Manocha, <vikas.manocha@st.com>
	4	*
	5	* SPDX-License-Identifier: GPL-2.0+
	6	*/
	7
	8	#ifndef __CONFIG_H
	9	#define __CONFIG_H
	10
e66c49fa VM	11	#define CONFIG_SYS_FLASH_BASE 0x08000000
e66c49fa VM	12	#define CONFIG_SYS_INIT_SP_ADDR 0x20050000
b9747696 VM	13
b9747696 VM	14	#ifdef CONFIG_SUPPORT_SPL
1a73bd84 VM	15	#define CONFIG_SYS_TEXT_BASE 0x08008000
1a73bd84 VM	16	#define CONFIG_SYS_LOAD_ADDR 0x08008000
b9747696 VM	17	#else
b9747696 VM	18	#define CONFIG_SYS_TEXT_BASE CONFIG_SYS_FLASH_BASE
1a73bd84 VM	19	#define CONFIG_SYS_LOAD_ADDR 0xC0400000
1a73bd84 VM	20	#define CONFIG_LOADADDR 0xC0400000
b9747696	21	#endif
e66c49fa	22
e66c49fa VM	23	/*
	24	* Configuration of the external SDRAM memory
	25	*/
	26	#define CONFIG_NR_DRAM_BANKS 1
e66c49fa	27
adcc90b4 VM	28	#define CONFIG_SYS_MAX_FLASH_SECT 8
adcc90b4 VM	29	#define CONFIG_SYS_MAX_FLASH_BANKS 1
e66c49fa	30
e66c49fa VM	31	#define CONFIG_ENV_SIZE (8 << 10)
e66c49fa VM	32
adcc90b4	33	#define CONFIG_STM32_FLASH
e66c49fa	34
b20b70fc MK	35	#define CONFIG_DW_GMAC_DEFAULT_DMA_PBL (8)
	36	#define CONFIG_DW_ALTDESCRIPTOR
	37	#define CONFIG_MII
fc0d3dbc	38	#define CONFIG_PHY_SMSC
b20b70fc	39
ba0a3c16 TN	40	#define CONFIG_STM32_HSE_HZ 25000000
ba0a3c16 TN	41	#define CONFIG_SYS_CLK_FREQ 200000000 /* 200 MHz */
e66c49fa VM	42	#define CONFIG_SYS_HZ_CLOCK 1000000 /* Timer is clocked at 1MHz */
	43
	44	#define CONFIG_CMDLINE_TAG
	45	#define CONFIG_SETUP_MEMORY_TAGS
	46	#define CONFIG_INITRD_TAG
	47	#define CONFIG_REVISION_TAG
	48
	49	#define CONFIG_SYS_CBSIZE 1024
e66c49fa VM	50
e66c49fa VM	51	#define CONFIG_SYS_MAXARGS 16
b20b70fc	52	#define CONFIG_SYS_MALLOC_LEN (1 * 1024 * 1024)
e66c49fa	53
e66c49fa VM	54	#define CONFIG_BOOTCOMMAND \
	55	"run bootcmd_romfs"
	56
	57	#define CONFIG_EXTRA_ENV_SETTINGS \
	58	"bootargs_romfs=uclinux.physaddr=0x08180000 root=/dev/mtdblock0\0" \
	59	"bootcmd_romfs=setenv bootargs ${bootargs} ${bootargs_romfs};" \
	60	"bootm 0x08044000 - 0x08042000\0"
	61
e66c49fa VM	62
	63	/*
	64	* Command line configuration.
	65	*/
	66	#define CONFIG_SYS_LONGHELP
e66c49fa VM	67	#define CONFIG_AUTO_COMPLETE
e66c49fa VM	68	#define CONFIG_CMDLINE_EDITING
dc11d83a	69	#define CONFIG_CMD_CACHE
2f80a9f7	70	#define CONFIG_BOARD_LATE_INIT
a241c241	71	#define CONFIG_DISPLAY_BOARDINFO
b9747696 VM	72
	73	/* For SPL */
	74	#ifdef CONFIG_SUPPORT_SPL
	75	#define CONFIG_SPL_STACK CONFIG_SYS_INIT_SP_ADDR
	76	#define CONFIG_SPL_FRAMEWORK
	77	#define CONFIG_SPL_BOARD_INIT
	78	#define CONFIG_SPL_TEXT_BASE CONFIG_SYS_FLASH_BASE
	79	#define CONFIG_SYS_MONITOR_LEN (512 * 1024)
	80	#define CONFIG_SYS_SPL_LEN 0x00008000
1a73bd84	81	#define CONFIG_SYS_UBOOT_START 0x080083FD
b9747696 VM	82	#define CONFIG_SYS_UBOOT_BASE (CONFIG_SYS_FLASH_BASE + \
b9747696 VM	83	CONFIG_SYS_SPL_LEN)
55a3ef71	84
55a3ef71	85	/* DT blob (fdt) address */
55a3ef71 VM	86	#define CONFIG_SYS_FDT_BASE (CONFIG_SYS_FLASH_BASE + \
55a3ef71 VM	87	0x1C0000)
b9747696 VM	88	#endif
	89	/* For SPL ends */
	90
e66c49fa	91	#endif /* __CONFIG_H */