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9fa32b12 VM |
1 | /* |
2 | * (C) Copyright 2014 | |
3 | * Vikas Manocha, STMicroelectronics, <vikas.manocha@st.com> | |
4 | * | |
5 | * SPDX-License-Identifier: GPL-2.0+ | |
6 | */ | |
7 | ||
8 | #ifndef __CONFIG_STV0991_H | |
9 | #define __CONFIG_STV0991_H | |
9fa32b12 | 10 | #define CONFIG_SYS_DCACHE_OFF |
9fa32b12 VM |
11 | #define CONFIG_SYS_EXCEPTION_VECTORS_HIGH |
12 | #define CONFIG_BOARD_EARLY_INIT_F | |
2ce4eaf4 | 13 | |
9fa32b12 VM |
14 | #define CONFIG_SYS_CORTEX_R4 |
15 | ||
9fa32b12 VM |
16 | #define CONFIG_SYS_NO_FLASH |
17 | ||
18 | /* ram memory-related information */ | |
19 | #define CONFIG_NR_DRAM_BANKS 1 | |
20 | #define PHYS_SDRAM_1 0x00000000 | |
21 | #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 | |
22 | #define PHYS_SDRAM_1_SIZE 0x00198000 | |
23 | ||
24 | #define CONFIG_ENV_SIZE 0x10000 | |
137d5b91 VM |
25 | #define CONFIG_ENV_IS_IN_SPI_FLASH |
26 | #define CONFIG_ENV_SECT_SIZE CONFIG_ENV_SIZE | |
27 | #define CONFIG_ENV_OFFSET 0x30000 | |
9fa32b12 VM |
28 | #define CONFIG_ENV_ADDR \ |
29 | (PHYS_SDRAM_1_SIZE - CONFIG_ENV_SIZE) | |
30 | #define CONFIG_SYS_MAXARGS 16 | |
31 | #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 16 * 1024) | |
32 | ||
33 | /* serial port (PL011) configuration */ | |
9fa32b12 | 34 | #define CONFIG_BAUDRATE 115200 |
39e4795a | 35 | #define CONFIG_PL01X_SERIAL |
9fa32b12 VM |
36 | |
37 | /* user interface */ | |
c55e7591 | 38 | #define CONFIG_SYS_CBSIZE 1024 |
9fa32b12 VM |
39 | #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE \ |
40 | +sizeof(CONFIG_SYS_PROMPT) + 16) | |
41 | ||
42 | /* MISC */ | |
43 | #define CONFIG_SYS_LOAD_ADDR 0x00000000 | |
498b7c2e | 44 | #define CONFIG_SYS_INIT_RAM_SIZE 0x8000 |
9fa32b12 VM |
45 | #define CONFIG_SYS_INIT_RAM_ADDR 0x00190000 |
46 | #define CONFIG_SYS_INIT_SP_OFFSET \ | |
47 | (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) | |
a187559e | 48 | /* U-Boot Load Address */ |
9fa32b12 VM |
49 | #define CONFIG_SYS_TEXT_BASE 0x00010000 |
50 | #define CONFIG_SYS_INIT_SP_ADDR \ | |
51 | (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) | |
52 | ||
2ce4eaf4 VM |
53 | /* GMAC related configs */ |
54 | ||
55 | #define CONFIG_MII | |
2ce4eaf4 VM |
56 | #define CONFIG_DW_ALTDESCRIPTOR |
57 | #define CONFIG_PHY_MICREL | |
58 | ||
59 | /* Command support defines */ | |
2ce4eaf4 VM |
60 | #define CONFIG_PHY_RESET_DELAY 10000 /* in usec */ |
61 | ||
c55e7591 VM |
62 | #define CONFIG_SYS_MEMTEST_START 0x0000 |
63 | #define CONFIG_SYS_MEMTEST_END 1024*1024 | |
c55e7591 VM |
64 | |
65 | /* Misc configuration */ | |
66 | #define CONFIG_SYS_LONGHELP | |
67 | #define CONFIG_CMDLINE_EDITING | |
68 | ||
c55e7591 | 69 | #define CONFIG_BOOTCOMMAND "go 0x40040000" |
d126e016 | 70 | |
e67abcaa VM |
71 | /* |
72 | + * QSPI support | |
73 | + */ | |
74 | #ifdef CONFIG_OF_CONTROL /* QSPI is controlled via DT */ | |
e67abcaa VM |
75 | #define CONFIG_CQSPI_DECODER 0 |
76 | #define CONFIG_CQSPI_REF_CLK ((30/4)/2)*1000*1000 | |
e67abcaa | 77 | |
e67abcaa VM |
78 | #endif |
79 | ||
9fa32b12 | 80 | #endif /* __CONFIG_H */ |