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ee52b188 YS |
1 | /* |
2 | * Copyright 2011-2012 Freescale Semiconductor, Inc. | |
3 | * | |
1a459660 | 4 | * SPDX-License-Identifier: GPL-2.0+ |
ee52b188 YS |
5 | */ |
6 | ||
7 | /* | |
8 | * Corenet DS style board configuration file | |
9 | */ | |
1cb19fbb YS |
10 | #ifndef __T4QDS_H |
11 | #define __T4QDS_H | |
69fdf900 | 12 | |
ee52b188 YS |
13 | #define CONFIG_CMD_REGINFO |
14 | ||
15 | /* High Level Configuration Options */ | |
16 | #define CONFIG_BOOKE | |
ee52b188 YS |
17 | #define CONFIG_E500 /* BOOKE e500 family */ |
18 | #define CONFIG_E500MC /* BOOKE e500mc family */ | |
19 | #define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */ | |
ee52b188 YS |
20 | #define CONFIG_MP /* support multiple processors */ |
21 | ||
22 | #ifndef CONFIG_SYS_TEXT_BASE | |
e222b1f3 | 23 | #define CONFIG_SYS_TEXT_BASE 0xeff40000 |
ee52b188 YS |
24 | #endif |
25 | ||
26 | #ifndef CONFIG_RESET_VECTOR_ADDRESS | |
27 | #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc | |
28 | #endif | |
29 | ||
30 | #define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */ | |
31 | #define CONFIG_SYS_NUM_CPC CONFIG_NUM_DDR_CONTROLLERS | |
32 | #define CONFIG_FSL_IFC /* Enable IFC Support */ | |
33 | #define CONFIG_PCI /* Enable PCI/PCIE */ | |
34 | #define CONFIG_PCIE1 /* PCIE controler 1 */ | |
35 | #define CONFIG_PCIE2 /* PCIE controler 2 */ | |
36 | #define CONFIG_PCIE3 /* PCIE controler 3 */ | |
37 | #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ | |
38 | #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ | |
39 | ||
40 | #define CONFIG_SYS_SRIO | |
41 | #define CONFIG_SRIO1 /* SRIO port 1 */ | |
42 | #define CONFIG_SRIO2 /* SRIO port 2 */ | |
43 | ||
44 | #define CONFIG_FSL_LAW /* Use common FSL init code */ | |
45 | ||
46 | #define CONFIG_ENV_OVERWRITE | |
47 | ||
ee52b188 YS |
48 | /* |
49 | * These can be toggled for performance analysis, otherwise use default. | |
50 | */ | |
51 | #define CONFIG_SYS_CACHE_STASHING | |
52 | #define CONFIG_BTB /* toggle branch predition */ | |
ee52b188 YS |
53 | #ifdef CONFIG_DDR_ECC |
54 | #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER | |
55 | #define CONFIG_MEM_INIT_VALUE 0xdeadbeef | |
56 | #endif | |
57 | ||
58 | #define CONFIG_ENABLE_36BIT_PHYS | |
59 | ||
ee52b188 YS |
60 | #define CONFIG_ADDR_MAP |
61 | #define CONFIG_SYS_NUM_ADDR_MAP 64 /* number of TLB1 entries */ | |
ee52b188 | 62 | |
ee52b188 YS |
63 | #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */ |
64 | #define CONFIG_SYS_MEMTEST_END 0x00400000 | |
65 | #define CONFIG_SYS_ALT_MEMTEST | |
66 | #define CONFIG_PANIC_HANG /* do not reset board on panic */ | |
67 | ||
68 | /* | |
69 | * Config the L3 Cache as L3 SRAM | |
70 | */ | |
b6036993 SX |
71 | #define CONFIG_SYS_INIT_L3_ADDR 0xFFFC0000 |
72 | #define CONFIG_SYS_L3_SIZE (512 << 10) | |
73 | #define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L3_ADDR + 32 * 1024) | |
74 | #ifdef CONFIG_RAMBOOT_PBL | |
75 | #define CONFIG_ENV_ADDR (CONFIG_SPL_GD_ADDR + 4 * 1024) | |
76 | #endif | |
77 | #define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SPL_GD_ADDR + 12 * 1024) | |
78 | #define CONFIG_SPL_RELOC_MALLOC_SIZE (50 << 10) | |
79 | #define CONFIG_SPL_RELOC_STACK (CONFIG_SPL_GD_ADDR + 64 * 1024) | |
80 | #define CONFIG_SPL_RELOC_STACK_SIZE (22 << 10) | |
ee52b188 | 81 | |
ee52b188 YS |
82 | #define CONFIG_SYS_DCSRBAR 0xf0000000 |
83 | #define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull | |
ee52b188 | 84 | |
ee52b188 YS |
85 | /* |
86 | * DDR Setup | |
87 | */ | |
88 | #define CONFIG_VERY_BIG_RAM | |
89 | #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 | |
90 | #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE | |
91 | ||
92 | /* CONFIG_NUM_DDR_CONTROLLERS is defined in include/asm/config_mpc85xx.h */ | |
93 | #define CONFIG_DIMM_SLOTS_PER_CTLR 2 | |
94 | #define CONFIG_CHIP_SELECTS_PER_CTRL 4 | |
95 | #define CONFIG_FSL_DDR_FIRST_SLOT_QUAD_CAPABLE | |
96 | ||
97 | #define CONFIG_DDR_SPD | |
5614e71b | 98 | #define CONFIG_SYS_FSL_DDR3 |
ee52b188 | 99 | |
ee52b188 YS |
100 | |
101 | /* | |
102 | * IFC Definitions | |
103 | */ | |
104 | #define CONFIG_SYS_FLASH_BASE 0xe0000000 | |
ee52b188 | 105 | #define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE) |
ee52b188 | 106 | |
ee52b188 | 107 | |
b6036993 SX |
108 | #ifdef CONFIG_SPL_BUILD |
109 | #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE | |
110 | #else | |
111 | #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ | |
112 | #endif | |
ee52b188 | 113 | |
ee52b188 YS |
114 | #define CONFIG_BOARD_EARLY_INIT_R /* call board_early_init_r function */ |
115 | #define CONFIG_MISC_INIT_R | |
116 | ||
117 | #define CONFIG_HWCONFIG | |
118 | ||
119 | /* define to use L1 as initial stack */ | |
120 | #define CONFIG_L1_INIT_RAM | |
121 | #define CONFIG_SYS_INIT_RAM_LOCK | |
122 | #define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */ | |
ee52b188 YS |
123 | #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf |
124 | #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW 0xfe0ec000 | |
125 | /* The assembler doesn't like typecast */ | |
126 | #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \ | |
127 | ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \ | |
128 | CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW) | |
ee52b188 YS |
129 | #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 |
130 | ||
131 | #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \ | |
132 | GENERATED_GBL_DATA_SIZE) | |
133 | #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET | |
134 | ||
9307cbab | 135 | #define CONFIG_SYS_MONITOR_LEN (768 * 1024) |
ee52b188 YS |
136 | #define CONFIG_SYS_MALLOC_LEN (4 * 1024 * 1024) |
137 | ||
138 | /* Serial Port - controlled on board with jumper J8 | |
139 | * open - index 2 | |
140 | * shorted - index 1 | |
141 | */ | |
142 | #define CONFIG_CONS_INDEX 1 | |
143 | #define CONFIG_SYS_NS16550 | |
144 | #define CONFIG_SYS_NS16550_SERIAL | |
145 | #define CONFIG_SYS_NS16550_REG_SIZE 1 | |
146 | #define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2) | |
147 | ||
148 | #define CONFIG_SYS_BAUDRATE_TABLE \ | |
149 | {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} | |
150 | ||
151 | #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500) | |
152 | #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600) | |
153 | #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500) | |
154 | #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600) | |
155 | ||
156 | /* Use the HUSH parser */ | |
157 | #define CONFIG_SYS_HUSH_PARSER | |
158 | #define CONFIG_SYS_PROMPT_HUSH_PS2 "> " | |
159 | ||
160 | /* pass open firmware flat tree */ | |
161 | #define CONFIG_OF_LIBFDT | |
162 | #define CONFIG_OF_BOARD_SETUP | |
163 | #define CONFIG_OF_STDOUT_VIA_ALIAS | |
164 | ||
165 | /* new uImage format support */ | |
166 | #define CONFIG_FIT | |
167 | #define CONFIG_FIT_VERBOSE /* enable fit_format_{error,warning}() */ | |
168 | ||
169 | /* I2C */ | |
00f792e0 HS |
170 | #define CONFIG_SYS_I2C |
171 | #define CONFIG_SYS_I2C_FSL | |
00f792e0 HS |
172 | #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F |
173 | #define CONFIG_SYS_FSL_I2C_OFFSET 0x118000 | |
00f792e0 HS |
174 | #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F |
175 | #define CONFIG_SYS_FSL_I2C2_OFFSET 0x118100 | |
176 | ||
ee52b188 YS |
177 | /* |
178 | * RapidIO | |
179 | */ | |
180 | #define CONFIG_SYS_SRIO1_MEM_VIRT 0xa0000000 | |
ee52b188 | 181 | #define CONFIG_SYS_SRIO1_MEM_PHYS 0xc20000000ull |
ee52b188 YS |
182 | #define CONFIG_SYS_SRIO1_MEM_SIZE 0x10000000 /* 256M */ |
183 | ||
184 | #define CONFIG_SYS_SRIO2_MEM_VIRT 0xb0000000 | |
ee52b188 | 185 | #define CONFIG_SYS_SRIO2_MEM_PHYS 0xc30000000ull |
ee52b188 YS |
186 | #define CONFIG_SYS_SRIO2_MEM_SIZE 0x10000000 /* 256M */ |
187 | ||
ee52b188 YS |
188 | /* |
189 | * General PCI | |
190 | * Memory space is mapped 1-1, but I/O space must start from 0. | |
191 | */ | |
192 | ||
193 | /* controller 1, direct to uli, tgtid 3, Base address 20000 */ | |
194 | #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000 | |
ee52b188 YS |
195 | #define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000 |
196 | #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull | |
ee52b188 YS |
197 | #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ |
198 | #define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000 | |
199 | #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 | |
ee52b188 | 200 | #define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull |
ee52b188 YS |
201 | #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ |
202 | ||
203 | /* controller 2, Slot 2, tgtid 2, Base address 201000 */ | |
204 | #define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000 | |
ee52b188 YS |
205 | #define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000 |
206 | #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull | |
ee52b188 YS |
207 | #define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */ |
208 | #define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000 | |
209 | #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 | |
ee52b188 | 210 | #define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull |
ee52b188 YS |
211 | #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ |
212 | ||
213 | /* controller 3, Slot 1, tgtid 1, Base address 202000 */ | |
214 | #define CONFIG_SYS_PCIE3_MEM_VIRT 0xc0000000 | |
ee52b188 YS |
215 | #define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000 |
216 | #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc40000000ull | |
ee52b188 YS |
217 | #define CONFIG_SYS_PCIE3_MEM_SIZE 0x20000000 /* 512M */ |
218 | #define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000 | |
219 | #define CONFIG_SYS_PCIE3_IO_BUS 0x00000000 | |
ee52b188 | 220 | #define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull |
ee52b188 YS |
221 | #define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */ |
222 | ||
223 | /* controller 4, Base address 203000 */ | |
224 | #define CONFIG_SYS_PCIE4_MEM_BUS 0xe0000000 | |
225 | #define CONFIG_SYS_PCIE4_MEM_PHYS 0xc60000000ull | |
226 | #define CONFIG_SYS_PCIE4_MEM_SIZE 0x20000000 /* 512M */ | |
227 | #define CONFIG_SYS_PCIE4_IO_BUS 0x00000000 | |
228 | #define CONFIG_SYS_PCIE4_IO_PHYS 0xff8030000ull | |
229 | #define CONFIG_SYS_PCIE4_IO_SIZE 0x00010000 /* 64k */ | |
230 | ||
ee52b188 | 231 | #ifdef CONFIG_PCI |
842033e6 | 232 | #define CONFIG_PCI_INDIRECT_BRIDGE |
ee52b188 YS |
233 | #define CONFIG_NET_MULTI |
234 | #define CONFIG_PCI_PNP /* do pci plug-and-play */ | |
235 | #define CONFIG_E1000 | |
236 | ||
237 | #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ | |
238 | #define CONFIG_DOS_PARTITION | |
239 | #endif /* CONFIG_PCI */ | |
240 | ||
241 | /* SATA */ | |
242 | #ifdef CONFIG_FSL_SATA_V2 | |
243 | #define CONFIG_LIBATA | |
244 | #define CONFIG_FSL_SATA | |
245 | ||
246 | #define CONFIG_SYS_SATA_MAX_DEVICE 2 | |
247 | #define CONFIG_SATA1 | |
248 | #define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR | |
249 | #define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA | |
250 | #define CONFIG_SATA2 | |
251 | #define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR | |
252 | #define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA | |
253 | ||
254 | #define CONFIG_LBA48 | |
255 | #define CONFIG_CMD_SATA | |
256 | #define CONFIG_DOS_PARTITION | |
257 | #define CONFIG_CMD_EXT2 | |
258 | #endif | |
259 | ||
260 | #ifdef CONFIG_FMAN_ENET | |
261 | #define CONFIG_MII /* MII PHY management */ | |
262 | #define CONFIG_ETHPRIME "FM1@DTSEC1" | |
263 | #define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */ | |
264 | #endif | |
265 | ||
266 | /* | |
267 | * Environment | |
268 | */ | |
269 | #define CONFIG_LOADS_ECHO /* echo on for serial download */ | |
270 | #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */ | |
271 | ||
272 | /* | |
273 | * Command line configuration. | |
274 | */ | |
275 | #include <config_cmd_default.h> | |
276 | ||
277 | #define CONFIG_CMD_DHCP | |
278 | #define CONFIG_CMD_ELF | |
279 | #define CONFIG_CMD_ERRATA | |
280 | #define CONFIG_CMD_GREPENV | |
281 | #define CONFIG_CMD_IRQ | |
282 | #define CONFIG_CMD_I2C | |
283 | #define CONFIG_CMD_MII | |
284 | #define CONFIG_CMD_PING | |
285 | #define CONFIG_CMD_SETEXPR | |
286 | ||
287 | #ifdef CONFIG_PCI | |
288 | #define CONFIG_CMD_PCI | |
289 | #define CONFIG_CMD_NET | |
290 | #endif | |
291 | ||
ee52b188 YS |
292 | /* |
293 | * Miscellaneous configurable options | |
294 | */ | |
295 | #define CONFIG_SYS_LONGHELP /* undef to save memory */ | |
296 | #define CONFIG_CMDLINE_EDITING /* Command-line editing */ | |
297 | #define CONFIG_AUTO_COMPLETE /* add autocompletion support */ | |
298 | #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ | |
ee52b188 YS |
299 | #ifdef CONFIG_CMD_KGDB |
300 | #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ | |
301 | #else | |
302 | #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ | |
303 | #endif | |
304 | #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) | |
305 | #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ | |
306 | #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE/* Boot Argument Buffer Size */ | |
ee52b188 YS |
307 | |
308 | /* | |
309 | * For booting Linux, the board info and command line data | |
310 | * have to be in the first 64 MB of memory, since this is | |
311 | * the maximum mapped by the Linux kernel during initialization. | |
312 | */ | |
313 | #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial map for Linux*/ | |
314 | #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ | |
315 | ||
316 | #ifdef CONFIG_CMD_KGDB | |
317 | #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ | |
ee52b188 YS |
318 | #endif |
319 | ||
320 | /* | |
321 | * Environment Configuration | |
322 | */ | |
323 | #define CONFIG_ROOTPATH "/opt/nfsroot" | |
324 | #define CONFIG_BOOTFILE "uImage" | |
325 | #define CONFIG_UBOOTPATH "u-boot.bin" /* U-Boot image on TFTP server*/ | |
326 | ||
327 | /* default location for tftp and bootm */ | |
328 | #define CONFIG_LOADADDR 1000000 | |
329 | ||
ee52b188 YS |
330 | |
331 | #define CONFIG_BAUDRATE 115200 | |
332 | ||
ee52b188 YS |
333 | #define CONFIG_HVBOOT \ |
334 | "setenv bootargs config-addr=0x60000000; " \ | |
335 | "bootm 0x01000000 - 0x00f00000" | |
336 | ||
ee52b188 | 337 | #endif /* __CONFIG_H */ |