[people/ms/u-boot.git] / include / configs / taihu.h

/*
 * (C) Copyright 2000-2005
 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
 *
 * (C) Copyright 2005-2007
 * Beijing UD Technology Co., Ltd., taihusupport@amcc.com
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */

#ifndef __CONFIG_H
#define __CONFIG_H


#define CONFIG_405EP		1	/* this is a PPC405 CPU */
#define CONFIG_4xx		1	/*  member of PPC4xx family */
#define CONFIG_TAIHU	        1	/*  on a taihu board */

/*
 * Include common defines/options for all AMCC eval boards
 */
#define CONFIG_HOSTNAME		taihu
#include "amcc-common.h"

#define CONFIG_BOARD_EARLY_INIT_F 1	/* call board_early_init_f */

#define CONFIG_SYS_CLK_FREQ     33000000 /* external frequency to pll   */

#define CONFIG_NO_SERIAL_EEPROM

/*----------------------------------------------------------------------------*/
#ifdef CONFIG_NO_SERIAL_EEPROM

/*
!-------------------------------------------------------------------------------
! PLL settings for 333MHz CPU, 111MHz PLB/SDRAM, 55MHz EBC, 33MHz PCI,
! assuming a 33MHz input clock to the 405EP from the C9531.
!-------------------------------------------------------------------------------
*/
#define PLLMR0_333_111_55_37 (PLL_CPUDIV_1 | PLL_PLBDIV_3 |  \
			      PLL_OPBDIV_2 | PLL_EXTBUSDIV_2 |  \
			      PLL_MALDIV_1 | PLL_PCIDIV_3)
#define PLLMR1_333_111_55_37 (PLL_FBKDIV_10  |  \
			      PLL_FWDDIVA_3 | PLL_FWDDIVB_3 |  \
			      PLL_TUNE_15_M_40 | PLL_TUNE_VCO_HI)
#define PLLMR0_333_111_55_111 (PLL_CPUDIV_1 | PLL_PLBDIV_3 |  \
			       PLL_OPBDIV_2 | PLL_EXTBUSDIV_2 |  \
			       PLL_MALDIV_1 | PLL_PCIDIV_1)
#define PLLMR1_333_111_55_111 (PLL_FBKDIV_10  |  \
			       PLL_FWDDIVA_3 | PLL_FWDDIVB_3 |  \
			       PLL_TUNE_15_M_40 | PLL_TUNE_VCO_HI)

#define PLLMR0_DEFAULT		PLLMR0_333_111_55_37
#define PLLMR1_DEFAULT		PLLMR1_333_111_55_37
#define PLLMR0_DEFAULT_PCI66	PLLMR0_333_111_55_111
#define PLLMR1_DEFAULT_PCI66	PLLMR1_333_111_55_111

#endif
/*----------------------------------------------------------------------------*/

#define CONFIG_ENV_IS_IN_FLASH     1	/* use FLASH for environment vars */

/*
 * Default environment variables
 */
#define	CONFIG_EXTRA_ENV_SETTINGS					\
	CONFIG_AMCC_DEF_ENV						\
	CONFIG_AMCC_DEF_ENV_PPC						\
	CONFIG_AMCC_DEF_ENV_NOR_UPD					\
	"kernel_addr=FC000000\0"					\
	"ramdisk_addr=FC180000\0"					\
	""

#define CONFIG_PHY_ADDR		0x14	/* PHY address			*/
#define CONFIG_HAS_ETH0
#define CONFIG_HAS_ETH1
#define CONFIG_PHY1_ADDR	0x10	/* EMAC1 PHY address		*/
#define CONFIG_PHY_RESET	1

/*
 * Commands additional to the ones defined in amcc-common.h
 */
#define CONFIG_CMD_CACHE
#define CONFIG_CMD_PCI
#define CONFIG_CMD_SDRAM
#define CONFIG_CMD_SPI

#undef CONFIG_SPD_EEPROM		/* use SPD EEPROM for setup */
#define CONFIG_SYS_SDRAM_SIZE_PER_BANK 0x04000000 /* 64MB */
#define CONFIG_SYS_SDRAM_BANKS	        2

/*
 * SDRAM configuration (please see cpu/ppc/sdram.[ch])
 */
#define CONFIG_SDRAM_BANK0	1	/* init onboard SDRAM bank 0 */
#define CONFIG_SDRAM_BANK1	1	/* init onboard SDRAM bank 1 */

/* SDRAM timings used in datasheet */
#define CONFIG_SYS_SDRAM_CL            3	/* CAS latency */
#define CONFIG_SYS_SDRAM_tRP           20	/* PRECHARGE command period */
#define CONFIG_SYS_SDRAM_tRC           66	/* ACTIVE-to-ACTIVE command period */
#define CONFIG_SYS_SDRAM_tRCD          20	/* ACTIVE-to-READ delay */
#define CONFIG_SYS_SDRAM_tRFC		66	/* Auto refresh period */

/*
 * If CONFIG_SYS_EXT_SERIAL_CLOCK, then the UART divisor is 1.
 * If CONFIG_SYS_405_UART_ERRATA_59, then UART divisor is 31.
 * Otherwise, UART divisor is determined by CPU Clock and CONFIG_SYS_BASE_BAUD value.
 * The Linux BASE_BAUD define should match this configuration.
 *    baseBaud = cpuClock/(uartDivisor*16)
 * If CONFIG_SYS_405_UART_ERRATA_59 and 200MHz CPU clock,
 * set Linux BASE_BAUD to 403200.
 */
#undef	CONFIG_SERIAL_SOFTWARE_FIFO
#undef  CONFIG_SYS_EXT_SERIAL_CLOCK           /* external serial clock */
#undef  CONFIG_SYS_405_UART_ERRATA_59         /* 405GP/CR Rev. D silicon */
#define CONFIG_SYS_BASE_BAUD		691200
#define CONFIG_UART1_CONSOLE	1

/*-----------------------------------------------------------------------
 * I2C stuff
 *-----------------------------------------------------------------------
 */
#define CONFIG_SYS_I2C_SPEED		400000	/* I2C speed and slave address	*/

#define CONFIG_SYS_I2C_NOPROBES	{ 0x69 } /* avoid iprobe hangup (why?) */
#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS	6 /* 24C02 requires 5ms delay */

#define CONFIG_SYS_I2C_EEPROM_ADDR	0x50	/* I2C boot EEPROM (24C02W)	*/
#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN	1	/* Bytes of address		*/

#define CONFIG_SOFT_SPI
#define SPI_SCL  spi_scl
#define SPI_SDA  spi_sda
#define SPI_READ spi_read()
#define SPI_DELAY udelay(2)
#ifndef __ASSEMBLY__
void spi_scl(int);
void spi_sda(int);
unsigned char spi_read(void);
#endif

/* standard dtt sensor configuration */
#define CONFIG_DTT_DS1775	1
#define CONFIG_DTT_SENSORS	{ 0 }
#define CONFIG_SYS_I2C_DTT_ADDR	0x49

/*-----------------------------------------------------------------------
 * PCI stuff
 *-----------------------------------------------------------------------
 */
#define PCI_HOST_ADAPTER 0		/* configure ar pci adapter    */
#define PCI_HOST_FORCE   1		/* configure as pci host       */
#define PCI_HOST_AUTO    2		/* detected via arbiter enable */

#define CONFIG_PCI			/* include pci support	       */
#define CONFIG_PCI_HOST	PCI_HOST_FORCE  /* select pci host function    */
#define CONFIG_PCI_PNP			/* do pci plug-and-play        */
					/* resource configuration      */
#define CONFIG_PCI_SCAN_SHOW            /* show pci devices on startup */

#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x10e8	/* AMCC */
#define CONFIG_SYS_PCI_SUBSYS_DEVICEID 0xcafe	/* Whatever */
#define CONFIG_SYS_PCI_CLASSCODE       0x0600  /* PCI Class Code: bridge/host */
#define CONFIG_SYS_PCI_PTM1LA	    0x00000000	/* point to sdram              */
#define CONFIG_SYS_PCI_PTM1MS      0x80000001	/* 2GB, enable hard-wired to 1 */
#define CONFIG_SYS_PCI_PTM1PCI     0x00000000	/* Host: use this pci address  */
#define CONFIG_SYS_PCI_PTM2LA      0x00000000	/* disabled                    */
#define CONFIG_SYS_PCI_PTM2MS	    0x00000000	/* disabled                    */
#define CONFIG_SYS_PCI_PTM2PCI     0x04000000	/* Host: use this pci address  */
#define CONFIG_EEPRO100		1

/*-----------------------------------------------------------------------
 * Start addresses for the final memory configuration
 * (Set up by the startup code)
 */
#define CONFIG_SYS_FLASH_BASE		0xFFE00000

/*-----------------------------------------------------------------------
 * FLASH organization
 */
#define CONFIG_SYS_MAX_FLASH_BANKS	2	/* max number of memory banks		*/
#define CONFIG_SYS_MAX_FLASH_SECT	256	/* max number of sectors on one chip	*/

#define CONFIG_SYS_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)	*/

#define CONFIG_SYS_FLASH_ADDR0         0x555
#define CONFIG_SYS_FLASH_ADDR1         0x2aa
#define CONFIG_SYS_FLASH_WORD_SIZE     unsigned short

#ifdef CONFIG_ENV_IS_IN_FLASH
#define CONFIG_ENV_SECT_SIZE	0x10000	/* size of one complete sector	*/
#define CONFIG_ENV_ADDR		(CONFIG_SYS_MONITOR_BASE-CONFIG_ENV_SECT_SIZE)
#define CONFIG_ENV_SIZE		0x4000	/* Total Size of Environment Sector	*/

/* Address and size of Redundant Environment Sector	*/
#define CONFIG_ENV_ADDR_REDUND	(CONFIG_ENV_ADDR-CONFIG_ENV_SECT_SIZE)
#define CONFIG_ENV_SIZE_REDUND	(CONFIG_ENV_SIZE)
#endif /* CONFIG_ENV_IS_IN_FLASH */

/*-----------------------------------------------------------------------
 * NVRAM organization
 */
#define CONFIG_SYS_NVRAM_BASE_ADDR	0xf0000000	/* NVRAM base address */
#define CONFIG_SYS_NVRAM_SIZE		0x1ff8		/* NVRAM size */

#ifdef CONFIG_ENV_IS_IN_NVRAM
#define CONFIG_ENV_SIZE		0x0ff8		/* Size of Environment vars */
#define CONFIG_ENV_ADDR		\
	(CONFIG_SYS_NVRAM_BASE_ADDR+CONFIG_SYS_NVRAM_SIZE-CONFIG_ENV_SIZE)	/* Env*/
#endif

/*-----------------------------------------------------------------------
 * PPC405 GPIO Configuration
 */
#define CONFIG_SYS_4xx_GPIO_TABLE { /*				GPIO	Alternate1		*/	\
{												\
/* GPIO Core 0 */										\
{ GPIO_BASE, GPIO_OUT, GPIO_SEL,  GPIO_OUT_NO_CHG }, /* GPIO0	PerBLast    SPI CS	*/	\
{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO1	TS1E			*/	\
{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO2	TS2E			*/	\
{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO3	TS1O			*/	\
{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO4	TS2O			*/	\
{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO5	TS3			*/	\
{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO6	TS4			*/	\
{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO7	TS5			*/	\
{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO8	TS6			*/	\
{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO9	TrcClk			*/	\
{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO10	PerCS1			*/	\
{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO11	PerCS2			*/	\
{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO12	PerCS3			*/	\
{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO13	PerCS4			*/	\
{ GPIO_BASE, GPIO_OUT, GPIO_SEL,  GPIO_OUT_NO_CHG }, /* GPIO14	PerAddr03   SPI SCLK	*/	\
{ GPIO_BASE, GPIO_IN,  GPIO_SEL,  GPIO_OUT_NO_CHG }, /* GPIO15	PerAddr04   SPI DI	*/	\
{ GPIO_BASE, GPIO_OUT, GPIO_SEL,  GPIO_OUT_NO_CHG }, /* GPIO16	PerAddr05   SPI DO	*/	\
{ GPIO_BASE, GPIO_IN,  GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO17	IRQ0	    PCI INTA	*/	\
{ GPIO_BASE, GPIO_IN,  GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO18	IRQ1	    PCI INTB	*/	\
{ GPIO_BASE, GPIO_IN,  GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO19	IRQ2	    PCI INTC	*/	\
{ GPIO_BASE, GPIO_IN,  GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO20	IRQ3	    PCI INTD	*/	\
{ GPIO_BASE, GPIO_IN,  GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO21	IRQ4	    USB		*/	\
{ GPIO_BASE, GPIO_IN,  GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO22	IRQ5	    EBC		*/	\
{ GPIO_BASE, GPIO_OUT, GPIO_SEL,  GPIO_OUT_NO_CHG }, /* GPIO23	IRQ6	    unused	*/	\
{ GPIO_BASE, GPIO_IN,  GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO24	UART0_DCD   UART1	*/	\
{ GPIO_BASE, GPIO_IN,  GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO25	UART0_DSR		*/	\
{ GPIO_BASE, GPIO_IN,  GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO26	UART0_RI		*/	\
{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO27	UART0_DTR		*/	\
{ GPIO_BASE, GPIO_IN,  GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO28	UART1_Rx    UART0	*/	\
{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO29	UART1_Tx		*/	\
{ GPIO_BASE, GPIO_OUT, GPIO_SEL,  GPIO_OUT_NO_CHG }, /* GPIO30	RejectPkt0  User LED1	*/	\
{ GPIO_BASE, GPIO_OUT, GPIO_SEL,  GPIO_OUT_NO_CHG }, /* GPIO31	RejectPkt1  User LED2	*/	\
}												\
}

/*
 * Init Memory Controller:
 *
 * BR0/1 and OR0/1 (FLASH)
 */

#define FLASH_BASE0_PRELIM CONFIG_SYS_FLASH_BASE /* FLASH bank #0 */
#define FLASH_BASE1_PRELIM  0xFC000000	/* FLASH bank #1 */

/*-----------------------------------------------------------------------
 * Definitions for initial stack pointer and data area (in data cache)
 */
/* use on chip memory (OCM) for temperary stack until sdram is tested */
#define CONFIG_SYS_TEMP_STACK_OCM        1

/* On Chip Memory location */
#define CONFIG_SYS_OCM_DATA_ADDR	0xF8000000
#define CONFIG_SYS_OCM_DATA_SIZE	0x1000
#define CONFIG_SYS_INIT_RAM_ADDR	CONFIG_SYS_OCM_DATA_ADDR /* inside of SDRAM		*/
#define CONFIG_SYS_INIT_RAM_END	CONFIG_SYS_OCM_DATA_SIZE /* End of used area in RAM	*/

#define CONFIG_SYS_GBL_DATA_SIZE      128  /* size in bytes reserved for initial data */
#define CONFIG_SYS_GBL_DATA_OFFSET    (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_OFFSET      CONFIG_SYS_GBL_DATA_OFFSET

/*-----------------------------------------------------------------------
 * External Bus Controller (EBC) Setup
 */

/* Memory Bank 0 (Flash/SRAM) initialization */
#define CONFIG_SYS_EBC_PB0AP           0x03815600
#define CONFIG_SYS_EBC_PB0CR           0xFFE3A000  /* BAS=0xFFE,BS=2MB,BU=R/W,BW=16bit */

/* Memory Bank 1 (NVRAM/RTC) initialization */
#define CONFIG_SYS_EBC_PB1AP           0x05815600
#define CONFIG_SYS_EBC_PB1CR           0xFC0BA000  /* BAS=0xFc0,BS=32MB,BU=R/W,BW=16bit */

/* Memory Bank 2 (USB device) initialization */
#define CONFIG_SYS_EBC_PB2AP           0x03016600
#define CONFIG_SYS_EBC_PB2CR           0x50018000 /* BAS=0x500,BS=1MB,BU=R/W,BW=8bit */

/* Memory Bank 3 (LCM and D-flip-flop) initialization */
#define CONFIG_SYS_EBC_PB3AP           0x158FF600
#define CONFIG_SYS_EBC_PB3CR           0x50118000 /* BAS=0x501,BS=1MB,BU=R/W,BW=8bit */

/* Memory Bank 4 (not install) initialization */
#define CONFIG_SYS_EBC_PB4AP           0x158FF600
#define CONFIG_SYS_EBC_PB4CR           0x5021A000

#define CPLD_REG0_ADDR	0x50100000
#define CPLD_REG1_ADDR	0x50100001

#endif	/* __CONFIG_H */
Commit	Line	Data
d4024bb7 JO	1	/*
	2	* (C) Copyright 2000-2005
	3	* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
	4	*
	5	* (C) Copyright 2005-2007
	6	* Beijing UD Technology Co., Ltd., taihusupport@amcc.com
	7	*
	8	* See file CREDITS for list of people who contributed to this
	9	* project.
	10	*
	11	* This program is free software; you can redistribute it and/or
	12	* modify it under the terms of the GNU General Public License as
	13	* published by the Free Software Foundation; either version 2 of
	14	* the License, or (at your option) any later version.
	15	*
	16	* This program is distributed in the hope that it will be useful,
	17	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	18	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	19	* GNU General Public License for more details.
	20	*
	21	* You should have received a copy of the GNU General Public License
	22	* along with this program; if not, write to the Free Software
	23	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	24	* MA 02111-1307 USA
	25	*/
	26
	27	#ifndef __CONFIG_H
	28	#define __CONFIG_H
	29
	30
	31	#define CONFIG_405EP 1 /* this is a PPC405 CPU */
	32	#define CONFIG_4xx 1 /* member of PPC4xx family */
	33	#define CONFIG_TAIHU 1 /* on a taihu board */
	34
72675dc6 SR	35	/*
	36	* Include common defines/options for all AMCC eval boards
	37	*/
	38	#define CONFIG_HOSTNAME taihu
	39	#include "amcc-common.h"
	40
d4024bb7 JO	41	#define CONFIG_BOARD_EARLY_INIT_F 1 /* call board_early_init_f */
	42
	43	#define CONFIG_SYS_CLK_FREQ 33000000 /* external frequency to pll */
	44
	45	#define CONFIG_NO_SERIAL_EEPROM
	46
	47	/----------------------------------------------------------------------------/
	48	#ifdef CONFIG_NO_SERIAL_EEPROM
	49
	50	/*
	51	!-------------------------------------------------------------------------------
	52	! PLL settings for 333MHz CPU, 111MHz PLB/SDRAM, 55MHz EBC, 33MHz PCI,
	53	! assuming a 33MHz input clock to the 405EP from the C9531.
	54	!-------------------------------------------------------------------------------
	55	*/
	56	#define PLLMR0_333_111_55_37 (PLL_CPUDIV_1 \| PLL_PLBDIV_3 \| \
	57	PLL_OPBDIV_2 \| PLL_EXTBUSDIV_2 \| \
	58	PLL_MALDIV_1 \| PLL_PCIDIV_3)
	59	#define PLLMR1_333_111_55_37 (PLL_FBKDIV_10 \| \
	60	PLL_FWDDIVA_3 \| PLL_FWDDIVB_3 \| \
	61	PLL_TUNE_15_M_40 \| PLL_TUNE_VCO_HI)
	62	#define PLLMR0_333_111_55_111 (PLL_CPUDIV_1 \| PLL_PLBDIV_3 \| \
	63	PLL_OPBDIV_2 \| PLL_EXTBUSDIV_2 \| \
	64	PLL_MALDIV_1 \| PLL_PCIDIV_1)
	65	#define PLLMR1_333_111_55_111 (PLL_FBKDIV_10 \| \
	66	PLL_FWDDIVA_3 \| PLL_FWDDIVB_3 \| \
	67	PLL_TUNE_15_M_40 \| PLL_TUNE_VCO_HI)
	68
	69	#define PLLMR0_DEFAULT PLLMR0_333_111_55_37
	70	#define PLLMR1_DEFAULT PLLMR1_333_111_55_37
	71	#define PLLMR0_DEFAULT_PCI66 PLLMR0_333_111_55_111
	72	#define PLLMR1_DEFAULT_PCI66 PLLMR1_333_111_55_111
	73
	74	#endif
	75	/----------------------------------------------------------------------------/
	76
5a1aceb0	77	#define CONFIG_ENV_IS_IN_FLASH 1 /* use FLASH for environment vars */
d4024bb7	78
72675dc6 SR	79	/*
	80	* Default environment variables
	81	*/
	82	#define CONFIG_EXTRA_ENV_SETTINGS \
	83	CONFIG_AMCC_DEF_ENV \
	84	CONFIG_AMCC_DEF_ENV_PPC \
	85	CONFIG_AMCC_DEF_ENV_NOR_UPD \
d4024bb7 JO	86	"kernel_addr=FC000000\0" \
d4024bb7 JO	87	"ramdisk_addr=FC180000\0" \
d4024bb7	88	""
d4024bb7	89
d4024bb7	90	#define CONFIG_PHY_ADDR 0x14 /* PHY address */
a00eccfe	91	#define CONFIG_HAS_ETH0
d4024bb7 JO	92	#define CONFIG_HAS_ETH1
d4024bb7 JO	93	#define CONFIG_PHY1_ADDR 0x10 /* EMAC1 PHY address */
d4024bb7 JO	94	#define CONFIG_PHY_RESET 1
d4024bb7 JO	95
3b3bff4c	96	/*
72675dc6	97	* Commands additional to the ones defined in amcc-common.h
3b3bff4c	98	*/
3b3bff4c	99	#define CONFIG_CMD_CACHE
3b3bff4c	100	#define CONFIG_CMD_PCI
3b3bff4c SR	101	#define CONFIG_CMD_SDRAM
3b3bff4c SR	102	#define CONFIG_CMD_SPI
d4024bb7	103
d4024bb7	104	#undef CONFIG_SPD_EEPROM /* use SPD EEPROM for setup */
6d0f6bcf JCPV	105	#define CONFIG_SYS_SDRAM_SIZE_PER_BANK 0x04000000 /* 64MB */
6d0f6bcf JCPV	106	#define CONFIG_SYS_SDRAM_BANKS 2
d4024bb7 JO	107
	108	/*
	109	* SDRAM configuration (please see cpu/ppc/sdram.[ch])
	110	*/
	111	#define CONFIG_SDRAM_BANK0 1 /* init onboard SDRAM bank 0 */
	112	#define CONFIG_SDRAM_BANK1 1 /* init onboard SDRAM bank 1 */
	113
	114	/* SDRAM timings used in datasheet */
6d0f6bcf JCPV	115	#define CONFIG_SYS_SDRAM_CL 3 /* CAS latency */
	116	#define CONFIG_SYS_SDRAM_tRP 20 /* PRECHARGE command period */
	117	#define CONFIG_SYS_SDRAM_tRC 66 /* ACTIVE-to-ACTIVE command period */
	118	#define CONFIG_SYS_SDRAM_tRCD 20 /* ACTIVE-to-READ delay */
	119	#define CONFIG_SYS_SDRAM_tRFC 66 /* Auto refresh period */
d4024bb7	120
d4024bb7	121	/*
6d0f6bcf JCPV	122	* If CONFIG_SYS_EXT_SERIAL_CLOCK, then the UART divisor is 1.
	123	* If CONFIG_SYS_405_UART_ERRATA_59, then UART divisor is 31.
	124	* Otherwise, UART divisor is determined by CPU Clock and CONFIG_SYS_BASE_BAUD value.
d4024bb7 JO	125	* The Linux BASE_BAUD define should match this configuration.
d4024bb7 JO	126	* baseBaud = cpuClock/(uartDivisor*16)
6d0f6bcf	127	* If CONFIG_SYS_405_UART_ERRATA_59 and 200MHz CPU clock,
d4024bb7 JO	128	* set Linux BASE_BAUD to 403200.
	129	*/
	130	#undef CONFIG_SERIAL_SOFTWARE_FIFO
6d0f6bcf JCPV	131	#undef CONFIG_SYS_EXT_SERIAL_CLOCK /* external serial clock */
	132	#undef CONFIG_SYS_405_UART_ERRATA_59 /* 405GP/CR Rev. D silicon */
	133	#define CONFIG_SYS_BASE_BAUD 691200
d4024bb7 JO	134	#define CONFIG_UART1_CONSOLE 1
d4024bb7 JO	135
d4024bb7 JO	136	/*-----------------------------------------------------------------------
	137	* I2C stuff
	138	*-----------------------------------------------------------------------
	139	*/
6d0f6bcf	140	#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */
d4024bb7	141
6d0f6bcf JCPV	142	#define CONFIG_SYS_I2C_NOPROBES { 0x69 } /* avoid iprobe hangup (why?) */
6d0f6bcf JCPV	143	#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 6 /* 24C02 requires 5ms delay */
d4024bb7	144
6d0f6bcf JCPV	145	#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* I2C boot EEPROM (24C02W) */
6d0f6bcf JCPV	146	#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 /* Bytes of address */
d4024bb7 JO	147
	148	#define CONFIG_SOFT_SPI
	149	#define SPI_SCL spi_scl
	150	#define SPI_SDA spi_sda
	151	#define SPI_READ spi_read()
	152	#define SPI_DELAY udelay(2)
	153	#ifndef __ASSEMBLY__
	154	void spi_scl(int);
	155	void spi_sda(int);
	156	unsigned char spi_read(void);
	157	#endif
	158
	159	/* standard dtt sensor configuration */
	160	#define CONFIG_DTT_DS1775 1
	161	#define CONFIG_DTT_SENSORS { 0 }
6d0f6bcf	162	#define CONFIG_SYS_I2C_DTT_ADDR 0x49
d4024bb7 JO	163
	164	/*-----------------------------------------------------------------------
	165	* PCI stuff
	166	*-----------------------------------------------------------------------
	167	*/
	168	#define PCI_HOST_ADAPTER 0 /* configure ar pci adapter */
	169	#define PCI_HOST_FORCE 1 /* configure as pci host */
	170	#define PCI_HOST_AUTO 2 /* detected via arbiter enable */
	171
	172	#define CONFIG_PCI /* include pci support */
	173	#define CONFIG_PCI_HOST PCI_HOST_FORCE /* select pci host function */
	174	#define CONFIG_PCI_PNP /* do pci plug-and-play */
	175	/* resource configuration */
	176	#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
	177
6d0f6bcf JCPV	178	#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x10e8 /* AMCC */
	179	#define CONFIG_SYS_PCI_SUBSYS_DEVICEID 0xcafe /* Whatever */
	180	#define CONFIG_SYS_PCI_CLASSCODE 0x0600 /* PCI Class Code: bridge/host */
	181	#define CONFIG_SYS_PCI_PTM1LA 0x00000000 /* point to sdram */
	182	#define CONFIG_SYS_PCI_PTM1MS 0x80000001 /* 2GB, enable hard-wired to 1 */
	183	#define CONFIG_SYS_PCI_PTM1PCI 0x00000000 /* Host: use this pci address */
	184	#define CONFIG_SYS_PCI_PTM2LA 0x00000000 /* disabled */
	185	#define CONFIG_SYS_PCI_PTM2MS 0x00000000 /* disabled */
	186	#define CONFIG_SYS_PCI_PTM2PCI 0x04000000 /* Host: use this pci address */
d4024bb7 JO	187	#define CONFIG_EEPRO100 1
	188
	189	/*-----------------------------------------------------------------------
	190	* Start addresses for the final memory configuration
	191	* (Set up by the startup code)
d4024bb7	192	*/
6d0f6bcf	193	#define CONFIG_SYS_FLASH_BASE 0xFFE00000
d4024bb7 JO	194
	195	/*-----------------------------------------------------------------------
	196	* FLASH organization
	197	*/
6d0f6bcf JCPV	198	#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of memory banks */
6d0f6bcf JCPV	199	#define CONFIG_SYS_MAX_FLASH_SECT 256 /* max number of sectors on one chip */
d4024bb7	200
6d0f6bcf JCPV	201	#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
6d0f6bcf JCPV	202	#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
d4024bb7	203
6d0f6bcf JCPV	204	#define CONFIG_SYS_FLASH_ADDR0 0x555
	205	#define CONFIG_SYS_FLASH_ADDR1 0x2aa
	206	#define CONFIG_SYS_FLASH_WORD_SIZE unsigned short
d4024bb7	207
5a1aceb0	208	#ifdef CONFIG_ENV_IS_IN_FLASH
0e8d1586	209	#define CONFIG_ENV_SECT_SIZE 0x10000 /* size of one complete sector */
6d0f6bcf	210	#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE-CONFIG_ENV_SECT_SIZE)
0e8d1586	211	#define CONFIG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */
d4024bb7 JO	212
d4024bb7 JO	213	/* Address and size of Redundant Environment Sector */
0e8d1586 JCPV	214	#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR-CONFIG_ENV_SECT_SIZE)
0e8d1586 JCPV	215	#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
5a1aceb0	216	#endif /* CONFIG_ENV_IS_IN_FLASH */
d4024bb7 JO	217
	218	/*-----------------------------------------------------------------------
	219	* NVRAM organization
	220	*/
6d0f6bcf JCPV	221	#define CONFIG_SYS_NVRAM_BASE_ADDR 0xf0000000 /* NVRAM base address */
6d0f6bcf JCPV	222	#define CONFIG_SYS_NVRAM_SIZE 0x1ff8 /* NVRAM size */
d4024bb7	223
9314cee6	224	#ifdef CONFIG_ENV_IS_IN_NVRAM
0e8d1586 JCPV	225	#define CONFIG_ENV_SIZE 0x0ff8 /* Size of Environment vars */
0e8d1586 JCPV	226	#define CONFIG_ENV_ADDR \
6d0f6bcf	227	(CONFIG_SYS_NVRAM_BASE_ADDR+CONFIG_SYS_NVRAM_SIZE-CONFIG_ENV_SIZE) /* Env*/
d4024bb7 JO	228	#endif
	229
	230	/*-----------------------------------------------------------------------
	231	* PPC405 GPIO Configuration
	232	*/
6d0f6bcf	233	#define CONFIG_SYS_4xx_GPIO_TABLE { /* GPIO Alternate1 */ \
d4024bb7 JO	234	{ \
	235	/* GPIO Core 0 */ \
	236	{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO0 PerBLast SPI CS */ \
	237	{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO1 TS1E */ \
	238	{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO2 TS2E */ \
	239	{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO3 TS1O */ \
	240	{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO4 TS2O */ \
	241	{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO5 TS3 */ \
	242	{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO6 TS4 */ \
	243	{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO7 TS5 */ \
	244	{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO8 TS6 */ \
	245	{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO9 TrcClk */ \
	246	{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO10 PerCS1 */ \
	247	{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO11 PerCS2 */ \
	248	{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO12 PerCS3 */ \
	249	{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO13 PerCS4 */ \
	250	{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO14 PerAddr03 SPI SCLK */ \
	251	{ GPIO_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO15 PerAddr04 SPI DI */ \
	252	{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO16 PerAddr05 SPI DO */ \
	253	{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO17 IRQ0 PCI INTA */ \
	254	{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO18 IRQ1 PCI INTB */ \
	255	{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO19 IRQ2 PCI INTC */ \
	256	{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO20 IRQ3 PCI INTD */ \
	257	{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO21 IRQ4 USB */ \
	258	{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO22 IRQ5 EBC */ \
	259	{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO23 IRQ6 unused */ \
	260	{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO24 UART0_DCD UART1 */ \
	261	{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO25 UART0_DSR */ \
	262	{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO26 UART0_RI */ \
	263	{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO27 UART0_DTR */ \
53677ef1	264	{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO28 UART1_Rx UART0 */ \
d4024bb7 JO	265	{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO29 UART1_Tx */ \
	266	{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO30 RejectPkt0 User LED1 */ \
	267	{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO31 RejectPkt1 User LED2 */ \
	268	} \
	269	}
	270
d4024bb7 JO	271	/*
	272	* Init Memory Controller:
	273	*
	274	* BR0/1 and OR0/1 (FLASH)
	275	*/
	276
6d0f6bcf	277	#define FLASH_BASE0_PRELIM CONFIG_SYS_FLASH_BASE /* FLASH bank #0 */
d4024bb7 JO	278	#define FLASH_BASE1_PRELIM 0xFC000000 /* FLASH bank #1 */
	279
	280	/*-----------------------------------------------------------------------
	281	* Definitions for initial stack pointer and data area (in data cache)
	282	*/
	283	/* use on chip memory (OCM) for temperary stack until sdram is tested */
6d0f6bcf	284	#define CONFIG_SYS_TEMP_STACK_OCM 1
d4024bb7 JO	285
d4024bb7 JO	286	/* On Chip Memory location */
6d0f6bcf JCPV	287	#define CONFIG_SYS_OCM_DATA_ADDR 0xF8000000
	288	#define CONFIG_SYS_OCM_DATA_SIZE 0x1000
	289	#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_OCM_DATA_ADDR /* inside of SDRAM */
	290	#define CONFIG_SYS_INIT_RAM_END CONFIG_SYS_OCM_DATA_SIZE /* End of used area in RAM */
d4024bb7	291
6d0f6bcf JCPV	292	#define CONFIG_SYS_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
	293	#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
	294	#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
d4024bb7 JO	295
	296	/*-----------------------------------------------------------------------
	297	* External Bus Controller (EBC) Setup
	298	*/
	299
	300	/* Memory Bank 0 (Flash/SRAM) initialization */
6d0f6bcf JCPV	301	#define CONFIG_SYS_EBC_PB0AP 0x03815600
6d0f6bcf JCPV	302	#define CONFIG_SYS_EBC_PB0CR 0xFFE3A000 /* BAS=0xFFE,BS=2MB,BU=R/W,BW=16bit */
d4024bb7 JO	303
d4024bb7 JO	304	/* Memory Bank 1 (NVRAM/RTC) initialization */
6d0f6bcf JCPV	305	#define CONFIG_SYS_EBC_PB1AP 0x05815600
6d0f6bcf JCPV	306	#define CONFIG_SYS_EBC_PB1CR 0xFC0BA000 /* BAS=0xFc0,BS=32MB,BU=R/W,BW=16bit */
d4024bb7 JO	307
d4024bb7 JO	308	/* Memory Bank 2 (USB device) initialization */
6d0f6bcf JCPV	309	#define CONFIG_SYS_EBC_PB2AP 0x03016600
6d0f6bcf JCPV	310	#define CONFIG_SYS_EBC_PB2CR 0x50018000 /* BAS=0x500,BS=1MB,BU=R/W,BW=8bit */
d4024bb7 JO	311
d4024bb7 JO	312	/* Memory Bank 3 (LCM and D-flip-flop) initialization */
6d0f6bcf JCPV	313	#define CONFIG_SYS_EBC_PB3AP 0x158FF600
6d0f6bcf JCPV	314	#define CONFIG_SYS_EBC_PB3CR 0x50118000 /* BAS=0x501,BS=1MB,BU=R/W,BW=8bit */
d4024bb7 JO	315
d4024bb7 JO	316	/* Memory Bank 4 (not install) initialization */
6d0f6bcf JCPV	317	#define CONFIG_SYS_EBC_PB4AP 0x158FF600
6d0f6bcf JCPV	318	#define CONFIG_SYS_EBC_PB4CR 0x5021A000
d4024bb7	319
d4024bb7 JO	320	#define CPLD_REG0_ADDR 0x50100000
d4024bb7 JO	321	#define CPLD_REG1_ADDR 0x50100001
a00eccfe	322
d4024bb7	323	#endif /* __CONFIG_H */