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34167a36 SR |
1 | /* |
2 | * (C) Copyright 2007 | |
3 | * Stefan Roese, DENX Software Engineering, sr@denx.de. | |
4 | * | |
5 | * This program is free software; you can redistribute it and/or | |
6 | * modify it under the terms of the GNU General Public License as | |
7 | * published by the Free Software Foundation; either version 2 of | |
8 | * the License, or (at your option) any later version. | |
9 | * | |
10 | * This program is distributed in the hope that it will be useful, | |
11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
13 | * GNU General Public License for more details. | |
14 | * | |
15 | * You should have received a copy of the GNU General Public License | |
16 | * along with this program; if not, write to the Free Software | |
17 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | |
18 | * MA 02111-1307 USA | |
19 | */ | |
20 | ||
21 | /************************************************************************ | |
22 | * TAISHAN.h - configuration for AMCC 440GX Ref | |
23 | ***********************************************************************/ | |
24 | ||
25 | #ifndef __CONFIG_H | |
26 | #define __CONFIG_H | |
27 | ||
28 | /*----------------------------------------------------------------------- | |
29 | * High Level Configuration Options | |
30 | *----------------------------------------------------------------------*/ | |
31 | #define CONFIG_TAISHAN 1 /* Board is taishan */ | |
32 | #define CONFIG_440GX 1 /* Specifc GX support */ | |
efa35cf1 | 33 | #define CONFIG_440 1 /* ... PPC440 family */ |
34167a36 | 34 | #define CONFIG_4xx 1 /* ... PPC4xx family */ |
34167a36 SR |
35 | #define CONFIG_SYS_CLK_FREQ 33333333 /* external freq to pll */ |
36 | ||
72675dc6 SR |
37 | /* |
38 | * Include common defines/options for all AMCC eval boards | |
39 | */ | |
40 | #define CONFIG_HOSTNAME taishan | |
41 | #define CONFIG_USE_TTY ttyS1 | |
42 | #include "amcc-common.h" | |
43 | ||
34167a36 SR |
44 | #define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */ |
45 | #define CONFIG_MISC_INIT_R 1 /* Call misc_init_r */ | |
46 | ||
47 | /*----------------------------------------------------------------------- | |
48 | * Base addresses -- Note these are effective addresses where the | |
49 | * actual resources get mapped (not physical addresses) | |
50 | *----------------------------------------------------------------------*/ | |
6d0f6bcf JCPV |
51 | #define CONFIG_SYS_FLASH_BASE 0xfc000000 /* start of FLASH */ |
52 | #define CONFIG_SYS_PCI_MEMBASE 0x80000000 /* mapped pci memory */ | |
53 | #define CONFIG_SYS_PERIPHERAL_BASE 0xe0000000 /* internal peripherals */ | |
54 | #define CONFIG_SYS_ISRAM_BASE 0xc0000000 /* internal SRAM */ | |
55 | #define CONFIG_SYS_PCI_BASE 0xd0000000 /* internal PCI regs */ | |
34167a36 | 56 | |
6d0f6bcf JCPV |
57 | #define CONFIG_SYS_EBC0_FLASH_BASE CONFIG_SYS_FLASH_BASE |
58 | #define CONFIG_SYS_EBC1_FPGA_BASE (CONFIG_SYS_PERIPHERAL_BASE + 0x01000000) | |
59 | #define CONFIG_SYS_EBC2_LCM_BASE (CONFIG_SYS_PERIPHERAL_BASE + 0x02000000) | |
60 | #define CONFIG_SYS_EBC3_CONN_BASE (CONFIG_SYS_PERIPHERAL_BASE + 0x08000000) | |
34167a36 | 61 | |
6d0f6bcf | 62 | #define CONFIG_SYS_GPIO_BASE (CONFIG_SYS_PERIPHERAL_BASE + 0x00000700) |
34167a36 SR |
63 | |
64 | /*----------------------------------------------------------------------- | |
65 | * Initial RAM & stack pointer (placed in internal SRAM) | |
66 | *----------------------------------------------------------------------*/ | |
6d0f6bcf JCPV |
67 | #define CONFIG_SYS_TEMP_STACK_OCM 1 |
68 | #define CONFIG_SYS_OCM_DATA_ADDR CONFIG_SYS_ISRAM_BASE | |
69 | #define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_ISRAM_BASE /* Initial RAM address */ | |
70 | #define CONFIG_SYS_INIT_RAM_END 0x2000 /* End of used area in RAM*/ | |
71 | #define CONFIG_SYS_GBL_DATA_SIZE 128 /* num bytes initial data*/ | |
34167a36 | 72 | |
6d0f6bcf JCPV |
73 | #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE) |
74 | #define CONFIG_SYS_POST_WORD_ADDR (CONFIG_SYS_GBL_DATA_OFFSET - 0x4) | |
75 | #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_POST_WORD_ADDR | |
34167a36 | 76 | |
34167a36 SR |
77 | /*----------------------------------------------------------------------- |
78 | * Serial Port | |
79 | *----------------------------------------------------------------------*/ | |
80 | #define CONFIG_UART1_CONSOLE 1 /* use of UART1 as console */ | |
6d0f6bcf | 81 | #define CONFIG_SYS_EXT_SERIAL_CLOCK (1843200 * 6) /* Ext clk @ 11.059 MHz */ |
34167a36 SR |
82 | |
83 | /*----------------------------------------------------------------------- | |
84 | * Environment | |
85 | *----------------------------------------------------------------------*/ | |
5a1aceb0 | 86 | #define CONFIG_ENV_IS_IN_FLASH 1 /* use FLASH for environment vars */ |
34167a36 SR |
87 | |
88 | /*----------------------------------------------------------------------- | |
89 | * FLASH related | |
90 | *----------------------------------------------------------------------*/ | |
6d0f6bcf | 91 | #define CONFIG_SYS_FLASH_CFI |
00b1883a | 92 | #define CONFIG_FLASH_CFI_DRIVER |
6d0f6bcf JCPV |
93 | #define CONFIG_SYS_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */ |
94 | #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 /* use buffered writes (20x faster) */ | |
34167a36 | 95 | |
6d0f6bcf JCPV |
96 | #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE} |
97 | #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ | |
98 | #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ | |
34167a36 | 99 | |
6d0f6bcf JCPV |
100 | #undef CONFIG_SYS_FLASH_CHECKSUM |
101 | #define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ | |
102 | #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ | |
34167a36 | 103 | |
0e8d1586 | 104 | #define CONFIG_ENV_SECT_SIZE 0x40000 /* size of one complete sector */ |
6d0f6bcf | 105 | #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE-CONFIG_ENV_SECT_SIZE) |
0e8d1586 | 106 | #define CONFIG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */ |
34167a36 SR |
107 | |
108 | /* Address and size of Redundant Environment Sector */ | |
0e8d1586 JCPV |
109 | #define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR-CONFIG_ENV_SECT_SIZE) |
110 | #define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE) | |
34167a36 SR |
111 | |
112 | /*----------------------------------------------------------------------- | |
113 | * E2PROM bootstrap configure value | |
114 | *----------------------------------------------------------------------*/ | |
115 | ||
116 | /* | |
117 | * 800/133/66 | |
118 | * IIC 0~15: 86 78 11 6a 61 A7 04 62 00 00 00 00 00 00 00 00 | |
119 | */ | |
120 | ||
121 | /* | |
122 | * 800/160/80 | |
123 | * IIC 0~15: 86 78 c1 a6 09 67 04 63 00 00 00 00 00 00 00 00 | |
124 | */ | |
125 | ||
126 | /*----------------------------------------------------------------------- | |
127 | * DDR SDRAM | |
128 | *----------------------------------------------------------------------*/ | |
129 | #undef CONFIG_SPD_EEPROM /* Don't use SPD EEPROM for setup */ | |
130 | #define CONFIG_SDRAM_BANK0 1 /* init onboard DDR SDRAM bank 0 */ | |
6d0f6bcf | 131 | #define CONFIG_SYS_SDRAM0_TR0 0xC10A401A |
34167a36 SR |
132 | #undef CONFIG_SDRAM_ECC /* enable ECC support */ |
133 | ||
134 | /*----------------------------------------------------------------------- | |
135 | * I2C | |
136 | *----------------------------------------------------------------------*/ | |
6d0f6bcf | 137 | #define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */ |
34167a36 | 138 | |
6d0f6bcf JCPV |
139 | #undef CONFIG_SYS_I2C_MULTI_EEPROMS |
140 | #define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 | |
141 | #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 | |
142 | #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 | |
143 | #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 | |
34167a36 | 144 | |
6d0f6bcf | 145 | #define CONFIG_SYS_BOOTSTRAP_IIC_ADDR 0x50 |
34167a36 SR |
146 | |
147 | /* I2C SYSMON (LM75, AD7414 is almost compatible) */ | |
148 | #define CONFIG_DTT_LM75 1 /* ON Semi's LM75 */ | |
149 | #define CONFIG_DTT_SENSORS {0} /* Sensor addresses */ | |
6d0f6bcf JCPV |
150 | #define CONFIG_SYS_DTT_MAX_TEMP 70 |
151 | #define CONFIG_SYS_DTT_LOW_TEMP -30 | |
152 | #define CONFIG_SYS_DTT_HYSTERESIS 3 | |
34167a36 | 153 | |
72675dc6 SR |
154 | /* |
155 | * Default environment variables | |
156 | */ | |
34167a36 | 157 | #define CONFIG_EXTRA_ENV_SETTINGS \ |
72675dc6 SR |
158 | CONFIG_AMCC_DEF_ENV \ |
159 | CONFIG_AMCC_DEF_ENV_POWERPC \ | |
160 | CONFIG_AMCC_DEF_ENV_PPC_OLD \ | |
161 | CONFIG_AMCC_DEF_ENV_NOR_UPD \ | |
34167a36 SR |
162 | "kernel_addr=fc000000\0" \ |
163 | "ramdisk_addr=fc180000\0" \ | |
34167a36 SR |
164 | "kozio=bootm 0xffe00000\0" \ |
165 | "" | |
34167a36 SR |
166 | |
167 | /*----------------------------------------------------------------------- | |
168 | * Networking | |
169 | *----------------------------------------------------------------------*/ | |
170 | #define CONFIG_EMAC_NR_START 2 /* start with EMAC 2 (skip 0&1) */ | |
1636d1c8 WD |
171 | #define CONFIG_PHY_ADDR 0xff /* no phy on EMAC0 */ |
172 | #define CONFIG_PHY1_ADDR 0xff /* no phy on EMAC1 */ | |
34167a36 SR |
173 | #define CONFIG_PHY2_ADDR 0x1 |
174 | #define CONFIG_PHY3_ADDR 0x3 | |
175 | #define CONFIG_ET1011C_PHY 1 | |
176 | #define CONFIG_HAS_ETH0 | |
177 | #define CONFIG_HAS_ETH1 | |
178 | #define CONFIG_HAS_ETH2 | |
179 | #define CONFIG_HAS_ETH3 | |
180 | #define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */ | |
181 | #define CONFIG_PHY_RESET 1 /* reset phy upon startup */ | |
182 | #define CONFIG_PHY_RESET_DELAY 1000 | |
079a136c | 183 | |
6c18eb98 | 184 | /* |
72675dc6 | 185 | * Commands additional to the ones defined in amcc-common.h |
6c18eb98 | 186 | */ |
6c18eb98 | 187 | #define CONFIG_CMD_DTT |
6c18eb98 | 188 | #define CONFIG_CMD_PCI |
34167a36 SR |
189 | |
190 | /*----------------------------------------------------------------------- | |
191 | * PCI stuff | |
192 | *----------------------------------------------------------------------- | |
193 | */ | |
194 | /* General PCI */ | |
195 | #define CONFIG_PCI /* include pci support */ | |
196 | #define CONFIG_PCI_PNP /* do pci plug-and-play */ | |
197 | #define CONFIG_EEPRO100 1 /* include PCI EEPRO100 */ | |
198 | #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ | |
6d0f6bcf | 199 | #define CONFIG_SYS_PCI_TARGBASE 0x80000000 /* PCIaddr mapped to CONFIG_SYS_PCI_MEMBASE */ |
34167a36 SR |
200 | |
201 | /* Board-specific PCI */ | |
6d0f6bcf | 202 | #define CONFIG_SYS_PCI_TARGET_INIT /* let board init pci target */ |
34167a36 | 203 | |
6d0f6bcf JCPV |
204 | #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x10e8 /* AMCC */ |
205 | #define CONFIG_SYS_PCI_SUBSYS_DEVICEID 0xcafe /* Whatever */ | |
34167a36 | 206 | |
34167a36 | 207 | #endif /* __CONFIG_H */ |