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425faf74 TA |
1 | /* |
2 | * ti816x_evm.h | |
3 | * | |
4 | * Copyright (C) 2013, Adeneo Embedded <www.adeneo-embedded.com> | |
5 | * Antoine Tenart, <atenart@adeneo-embedded.com> | |
6 | * | |
7 | * SPDX-License-Identifier: GPL-2.0+ | |
8 | */ | |
9 | ||
10 | #ifndef __CONFIG_TI816X_EVM_H | |
11 | #define __CONFIG_TI816X_EVM_H | |
12 | ||
1d7f6ad2 | 13 | #include <configs/ti_armv7_omap.h> |
425faf74 TA |
14 | #include <asm/arch/omap.h> |
15 | ||
16 | #define CONFIG_ENV_SIZE 0x2000 | |
425faf74 TA |
17 | #define CONFIG_MACH_TYPE MACH_TYPE_TI8168EVM |
18 | ||
425faf74 | 19 | #define CONFIG_EXTRA_ENV_SETTINGS \ |
1d7f6ad2 TR |
20 | DEFAULT_LINUX_BOOT_ENV \ |
21 | "mtdids=" MTDIDS_DEFAULT "\0" \ | |
22 | "mtdparts=" MTDPARTS_DEFAULT "\0" \ | |
425faf74 TA |
23 | |
24 | #define CONFIG_BOOTCOMMAND \ | |
25 | "mmc rescan;" \ | |
26 | "fatload mmc 0 ${loadaddr} uImage;" \ | |
27 | "bootm ${loadaddr}" \ | |
28 | ||
29 | #define CONFIG_BOOTARGS "console=ttyO2,115200n8 noinitrd earlyprintk" | |
30 | ||
31 | /* Clock Defines */ | |
32 | #define V_OSCK 24000000 /* Clock output from T2 */ | |
33 | #define V_SCLK (V_OSCK >> 1) | |
34 | ||
4848d89d | 35 | #define CONFIG_CMD_ASKENV |
425faf74 | 36 | |
425faf74 | 37 | #define CONFIG_MAX_RAM_BANK_SIZE (2048 << 20) /* 2048MB */ |
1d7f6ad2 | 38 | #define CONFIG_SYS_SDRAM_BASE 0x80000000 |
425faf74 TA |
39 | |
40 | /** | |
41 | * Platform/Board specific defs | |
42 | */ | |
43 | #define CONFIG_SYS_CLK_FREQ 27000000 | |
44 | #define CONFIG_SYS_TIMERBASE 0x4802E000 | |
45 | #define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */ | |
46 | ||
425faf74 TA |
47 | /* |
48 | * NS16550 Configuration | |
49 | */ | |
425faf74 TA |
50 | #define CONFIG_SYS_NS16550_SERIAL |
51 | #define CONFIG_SYS_NS16550_REG_SIZE (-4) | |
52 | #define CONFIG_SYS_NS16550_CLK (48000000) | |
53 | #define CONFIG_SYS_NS16550_COM1 0x48024000 /* Base EVM has UART2 */ | |
54 | ||
425faf74 TA |
55 | /* allow overwriting serial config and ethaddr */ |
56 | #define CONFIG_ENV_OVERWRITE | |
57 | ||
58 | #define CONFIG_SERIAL1 | |
59 | #define CONFIG_SERIAL2 | |
60 | #define CONFIG_SERIAL3 | |
61 | #define CONFIG_CONS_INDEX 1 | |
425faf74 | 62 | |
77e99277 TR |
63 | /* |
64 | * GPMC NAND block. We support 1 device and the physical address to | |
65 | * access CS0 at is 0x8000000. | |
66 | */ | |
67 | #define CONFIG_SYS_NAND_BASE 0x8000000 | |
68 | #define CONFIG_SYS_MAX_NAND_DEVICE 1 | |
69 | ||
70 | /* NAND: SPL related configs */ | |
77e99277 | 71 | #define CONFIG_SPL_NAND_AM33XX_BCH |
77e99277 TR |
72 | |
73 | /* NAND: device related configs */ | |
74 | #define CONFIG_SYS_NAND_5_ADDR_CYCLE | |
75 | #define CONFIG_SYS_NAND_BUSWIDTH_16BIT | |
76 | #define CONFIG_SYS_NAND_PAGE_COUNT (CONFIG_SYS_NAND_BLOCK_SIZE / \ | |
77 | CONFIG_SYS_NAND_PAGE_SIZE) | |
78 | #define CONFIG_SYS_NAND_PAGE_SIZE 2048 | |
79 | #define CONFIG_SYS_NAND_OOBSIZE 64 | |
80 | #define CONFIG_SYS_NAND_BLOCK_SIZE (128*1024) | |
81 | /* NAND: driver related configs */ | |
77e99277 TR |
82 | #define CONFIG_NAND_OMAP_GPMC_PREFETCH |
83 | #define CONFIG_NAND_OMAP_ELM | |
84 | #define CONFIG_SYS_NAND_BAD_BLOCK_POS NAND_LARGE_BADBLOCK_POS | |
85 | #define CONFIG_SYS_NAND_ECCPOS { 2, 3, 4, 5, 6, 7, 8, 9, \ | |
86 | 10, 11, 12, 13, 14, 15, 16, 17, \ | |
87 | 18, 19, 20, 21, 22, 23, 24, 25, \ | |
88 | 26, 27, 28, 29, 30, 31, 32, 33, \ | |
89 | 34, 35, 36, 37, 38, 39, 40, 41, \ | |
90 | 42, 43, 44, 45, 46, 47, 48, 49, \ | |
91 | 50, 51, 52, 53, 54, 55, 56, 57, } | |
92 | ||
93 | #define CONFIG_SYS_NAND_ECCSIZE 512 | |
94 | #define CONFIG_SYS_NAND_ECCBYTES 14 | |
95 | #define CONFIG_SYS_NAND_ONFI_DETECTION | |
96 | #define CONFIG_NAND_OMAP_ECCSCHEME OMAP_ECC_BCH8_CODE_HW | |
97 | #define MTDIDS_DEFAULT "nand0=nand.0" | |
98 | #define MTDPARTS_DEFAULT "mtdparts=nand.0:" \ | |
99 | "128k(NAND.SPL)," \ | |
100 | "128k(NAND.SPL.backup1)," \ | |
101 | "128k(NAND.SPL.backup2)," \ | |
102 | "128k(NAND.SPL.backup3)," \ | |
103 | "256k(NAND.u-boot-spl-os)," \ | |
104 | "1m(NAND.u-boot)," \ | |
105 | "128k(NAND.u-boot-env)," \ | |
106 | "128k(NAND.u-boot-env.backup1)," \ | |
107 | "8m(NAND.kernel)," \ | |
108 | "-(NAND.file-system)" | |
109 | #define CONFIG_SYS_NAND_U_BOOT_OFFS 0x000c0000 | |
77e99277 TR |
110 | #define CONFIG_ENV_OFFSET 0x001c0000 |
111 | #define CONFIG_ENV_OFFSET_REDUND 0x001e0000 | |
112 | #define CONFIG_SYS_ENV_SECT_SIZE CONFIG_SYS_NAND_BLOCK_SIZE | |
425faf74 TA |
113 | |
114 | /* SPL */ | |
115 | /* Defines for SPL */ | |
77e99277 | 116 | #define CONFIG_SPL_NAND_AM33XX_BCH /* ELM support */ |
425faf74 | 117 | #define CONFIG_SPL_TEXT_BASE 0x40400000 |
fa2f81b0 TR |
118 | #define CONFIG_SPL_MAX_SIZE (SRAM_SCRATCH_SPACE_ADDR - \ |
119 | CONFIG_SPL_TEXT_BASE) | |
425faf74 | 120 | |
983e3700 | 121 | #define CONFIG_SPL_LDSCRIPT "arch/arm/mach-omap2/u-boot-spl.lds" |
425faf74 | 122 | |
425faf74 | 123 | #define CONFIG_SYS_TEXT_BASE 0x80800000 |
425faf74 | 124 | |
de820365 TR |
125 | #define CONFIG_DRIVER_TI_EMAC |
126 | #define CONFIG_MII | |
127 | #define CONFIG_BOOTP_DNS | |
128 | #define CONFIG_BOOTP_DNS2 | |
129 | #define CONFIG_BOOTP_SEND_HOSTNAME | |
130 | #define CONFIG_BOOTP_GATEWAY | |
131 | #define CONFIG_BOOTP_SUBNETMASK | |
132 | #define CONFIG_NET_RETRY_COUNT 10 | |
133 | ||
425faf74 TA |
134 | /* Since SPL did pll and ddr initialization for us, |
135 | * we don't need to do it twice. | |
136 | */ | |
137 | #ifndef CONFIG_SPL_BUILD | |
138 | #define CONFIG_SKIP_LOWLEVEL_INIT | |
139 | #endif | |
140 | ||
1d7f6ad2 TR |
141 | /* |
142 | * Disable MMC DM for SPL build and can be re-enabled after adding | |
143 | * DM support in SPL | |
144 | */ | |
145 | #ifdef CONFIG_SPL_BUILD | |
146 | #undef CONFIG_DM_MMC | |
147 | #undef CONFIG_TIMER | |
148 | #undef CONFIG_DM_USB | |
149 | #endif | |
425faf74 | 150 | #endif |