[people/ms/u-boot.git] / include / configs / ti_armv7_keystone2.h

/*
 * Common configuration header file for all Keystone II EVM platforms
 *
 * (C) Copyright 2012-2014
 *     Texas Instruments Incorporated, <www.ti.com>
 *
 * SPDX-License-Identifier:     GPL-2.0+
 */

#ifndef __CONFIG_KS2_EVM_H
#define __CONFIG_KS2_EVM_H

#define CONFIG_SOC_KEYSTONE

/* U-Boot Build Configuration */
#define CONFIG_SKIP_LOWLEVEL_INIT	/* U-Boot is a 2nd stage loader */
#define CONFIG_BOARD_EARLY_INIT_F

/* SoC Configuration */
#define CONFIG_ARCH_CPU_INIT
#define CONFIG_SYS_ARCH_TIMER
#define CONFIG_SYS_TEXT_BASE		0x0c001000
#define CONFIG_SPL_TARGET		"u-boot-spi.gph"
#define CONFIG_SYS_DCACHE_OFF

/* Memory Configuration */
#define CONFIG_NR_DRAM_BANKS		2
#define CONFIG_SYS_LPAE_SDRAM_BASE	0x800000000
#define CONFIG_MAX_RAM_BANK_SIZE	(2 << 30)       /* 2GB */
#define CONFIG_STACKSIZE		(512 << 10)     /* 512 KiB */
#define CONFIG_SYS_INIT_SP_ADDR		(CONFIG_SYS_TEXT_BASE - \
					GENERATED_GBL_DATA_SIZE)

/* SPL SPI Loader Configuration */
#define CONFIG_SPL_PAD_TO		65536
#define CONFIG_SPL_MAX_SIZE		(CONFIG_SPL_PAD_TO - 8)
#define CONFIG_SPL_BSS_START_ADDR	(CONFIG_SPL_TEXT_BASE + \
					CONFIG_SPL_MAX_SIZE)
#define CONFIG_SPL_BSS_MAX_SIZE		(32 * 1024)
#define CONFIG_SYS_SPL_MALLOC_START	(CONFIG_SPL_BSS_START_ADDR + \
					CONFIG_SPL_BSS_MAX_SIZE)
#define CONFIG_SYS_SPL_MALLOC_SIZE	(32 * 1024)
#define CONFIG_SPL_STACK_SIZE		(8 * 1024)
#define CONFIG_SPL_STACK		(CONFIG_SYS_SPL_MALLOC_START + \
					CONFIG_SYS_SPL_MALLOC_SIZE + \
					CONFIG_SPL_STACK_SIZE - 4)
#define CONFIG_SPL_SPI_FLASH_SUPPORT
#define CONFIG_SPL_SPI_SUPPORT
#define CONFIG_SPL_SPI_LOAD
#define CONFIG_SYS_SPI_U_BOOT_OFFS	CONFIG_SPL_PAD_TO

/* UART Configuration */
#define CONFIG_SYS_NS16550
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_MEM32
#define CONFIG_SYS_NS16550_REG_SIZE	-4
#define CONFIG_SYS_NS16550_COM1		KS2_UART0_BASE
#define CONFIG_SYS_NS16550_COM2		KS2_UART1_BASE
#define CONFIG_SYS_NS16550_CLK		clk_get_rate(KS2_CLK1_6)
#define CONFIG_CONS_INDEX		1

/* SPI Configuration */
#define CONFIG_SPI_FLASH_STMICRO
#define CONFIG_DAVINCI_SPI
#define CONFIG_SYS_SPI_CLK		clk_get_rate(KS2_CLK1_6)
#define CONFIG_SF_DEFAULT_SPEED		30000000
#define CONFIG_ENV_SPI_MAX_HZ		CONFIG_SF_DEFAULT_SPEED
#define CONFIG_SYS_SPI0
#define CONFIG_SYS_SPI_BASE		KS2_SPI0_BASE
#define CONFIG_SYS_SPI0_NUM_CS		4
#define CONFIG_SYS_SPI1
#define CONFIG_SYS_SPI1_BASE		KS2_SPI1_BASE
#define CONFIG_SYS_SPI1_NUM_CS		4
#define CONFIG_SYS_SPI2
#define CONFIG_SYS_SPI2_BASE		KS2_SPI2_BASE
#define CONFIG_SYS_SPI2_NUM_CS		4

/* Network Configuration */
#define CONFIG_PHYLIB
#define CONFIG_PHY_MARVELL
#define CONFIG_MII
#define CONFIG_BOOTP_DEFAULT
#define CONFIG_BOOTP_DNS
#define CONFIG_BOOTP_DNS2
#define CONFIG_BOOTP_SEND_HOSTNAME
#define CONFIG_NET_RETRY_COUNT		32
#define CONFIG_SYS_SGMII_REFCLK_MHZ	312
#define CONFIG_SYS_SGMII_LINERATE_MHZ	1250
#define CONFIG_SYS_SGMII_RATESCALE	2

/* Keyston Navigator Configuration */
#define CONFIG_TI_KSNAV
#define CONFIG_KSNAV_QM_BASE_ADDRESS		KS2_QM_BASE_ADDRESS
#define CONFIG_KSNAV_QM_CONF_BASE		KS2_QM_CONF_BASE
#define CONFIG_KSNAV_QM_DESC_SETUP_BASE		KS2_QM_DESC_SETUP_BASE
#define CONFIG_KSNAV_QM_STATUS_RAM_BASE		KS2_QM_STATUS_RAM_BASE
#define CONFIG_KSNAV_QM_INTD_CONF_BASE		KS2_QM_INTD_CONF_BASE
#define CONFIG_KSNAV_QM_PDSP1_CMD_BASE		KS2_QM_PDSP1_CMD_BASE
#define CONFIG_KSNAV_QM_PDSP1_CTRL_BASE		KS2_QM_PDSP1_CTRL_BASE
#define CONFIG_KSNAV_QM_PDSP1_IRAM_BASE		KS2_QM_PDSP1_IRAM_BASE
#define CONFIG_KSNAV_QM_MANAGER_QUEUES_BASE	KS2_QM_MANAGER_QUEUES_BASE
#define CONFIG_KSNAV_QM_MANAGER_Q_PROXY_BASE	KS2_QM_MANAGER_Q_PROXY_BASE
#define CONFIG_KSNAV_QM_QUEUE_STATUS_BASE	KS2_QM_QUEUE_STATUS_BASE
#define CONFIG_KSNAV_QM_LINK_RAM_BASE		KS2_QM_LINK_RAM_BASE
#define CONFIG_KSNAV_QM_REGION_NUM		KS2_QM_REGION_NUM
#define CONFIG_KSNAV_QM_QPOOL_NUM		KS2_QM_QPOOL_NUM

/* NETCP pktdma */
#define CONFIG_KSNAV_PKTDMA_NETCP
#define CONFIG_KSNAV_NETCP_PDMA_CTRL_BASE	KS2_NETCP_PDMA_CTRL_BASE
#define CONFIG_KSNAV_NETCP_PDMA_TX_BASE		KS2_NETCP_PDMA_TX_BASE
#define CONFIG_KSNAV_NETCP_PDMA_TX_CH_NUM	KS2_NETCP_PDMA_TX_CH_NUM
#define CONFIG_KSNAV_NETCP_PDMA_RX_BASE		KS2_NETCP_PDMA_RX_BASE
#define CONFIG_KSNAV_NETCP_PDMA_RX_CH_NUM	KS2_NETCP_PDMA_RX_CH_NUM
#define CONFIG_KSNAV_NETCP_PDMA_SCHED_BASE	KS2_NETCP_PDMA_SCHED_BASE
#define CONFIG_KSNAV_NETCP_PDMA_RX_FLOW_BASE	KS2_NETCP_PDMA_RX_FLOW_BASE
#define CONFIG_KSNAV_NETCP_PDMA_RX_FLOW_NUM	KS2_NETCP_PDMA_RX_FLOW_NUM
#define CONFIG_KSNAV_NETCP_PDMA_RX_FREE_QUEUE	KS2_NETCP_PDMA_RX_FREE_QUEUE
#define CONFIG_KSNAV_NETCP_PDMA_RX_RCV_QUEUE	KS2_NETCP_PDMA_RX_RCV_QUEUE
#define CONFIG_KSNAV_NETCP_PDMA_TX_SND_QUEUE	KS2_NETCP_PDMA_TX_SND_QUEUE

/* Keystone net */
#define CONFIG_DRIVER_TI_KEYSTONE_NET
#define CONFIG_KSNET_MAC_ID_BASE		KS2_MAC_ID_BASE_ADDR
#define CONFIG_KSNET_NETCP_BASE			KS2_NETCP_BASE
#define CONFIG_KSNET_SERDES_SGMII_BASE		KS2_SGMII_SERDES_BASE
#define CONFIG_KSNET_SERDES_SGMII2_BASE		KS2_SGMII_SERDES2_BASE
#define CONFIG_KSNET_SERDES_LANES_PER_SGMII	KS2_LANES_PER_SGMII_SERDES

/* SerDes */
#define CONFIG_TI_KEYSTONE_SERDES

/* AEMIF */
#define CONFIG_TI_AEMIF
#define CONFIG_AEMIF_CNTRL_BASE		KS2_AEMIF_CNTRL_BASE

/* I2C Configuration */
#define CONFIG_SYS_I2C_DAVINCI
#define CONFIG_SYS_DAVINCI_I2C_SPEED	100000
#define CONFIG_SYS_DAVINCI_I2C_SLAVE	0x10 /* SMBus host address */
#define CONFIG_SYS_DAVINCI_I2C_SPEED1	100000
#define CONFIG_SYS_DAVINCI_I2C_SLAVE1	0x10 /* SMBus host address */
#define CONFIG_SYS_DAVINCI_I2C_SPEED2	100000
#define CONFIG_SYS_DAVINCI_I2C_SLAVE2	0x10 /* SMBus host address */
#define I2C_BUS_MAX			3

/* EEPROM definitions */
#define CONFIG_SYS_I2C_MULTI_EEPROMS
#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN		2
#define CONFIG_SYS_I2C_EEPROM_ADDR		0x50
#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS	6
#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS	20
#define CONFIG_ENV_EEPROM_IS_ON_I2C

/* NAND Configuration */
#define CONFIG_NAND_DAVINCI
#define CONFIG_KEYSTONE_RBL_NAND
#define CONFIG_KEYSTONE_NAND_MAX_RBL_SIZE	CONFIG_ENV_OFFSET
#define CONFIG_SYS_NAND_MASK_CLE		0x4000
#define CONFIG_SYS_NAND_MASK_ALE		0x2000
#define CONFIG_SYS_NAND_CS			2
#define CONFIG_SYS_NAND_USE_FLASH_BBT
#define CONFIG_SYS_NAND_4BIT_HW_ECC_OOBFIRST

#define CONFIG_SYS_NAND_LARGEPAGE
#define CONFIG_SYS_NAND_BASE_LIST		{ 0x30000000, }
#define CONFIG_SYS_MAX_NAND_DEVICE		1
#define CONFIG_SYS_NAND_MAX_CHIPS		1
#define CONFIG_SYS_NAND_NO_SUBPAGE_WRITE
#define CONFIG_ENV_SIZE				(256 << 10)  /* 256 KiB */
#define CONFIG_ENV_IS_IN_NAND
#define CONFIG_ENV_OFFSET			0x100000
#define CONFIG_MTD_PARTITIONS
#define CONFIG_RBTREE
#define CONFIG_LZO
#define MTDIDS_DEFAULT			"nand0=davinci_nand.0"
#define MTDPARTS_DEFAULT		"mtdparts=davinci_nand.0:" \
					"1024k(bootloader)ro,512k(params)ro," \
					"-(ubifs)"

/* USB Configuration */
#define CONFIG_USB_XHCI
#define CONFIG_USB_XHCI_DWC3
#define CONFIG_USB_XHCI_KEYSTONE
#define CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS	2
#define CONFIG_EFI_PARTITION
#define CONFIG_FS_FAT
#define CONFIG_SYS_CACHELINE_SIZE		64
#define CONFIG_USB_SS_BASE			KS2_USB_SS_BASE
#define CONFIG_USB_HOST_XHCI_BASE		KS2_USB_HOST_XHCI_BASE
#define CONFIG_DEV_USB_PHY_BASE			KS2_DEV_USB_PHY_BASE
#define CONFIG_USB_PHY_CFG_BASE			KS2_USB_PHY_CFG_BASE

/* U-Boot command configuration */
#define CONFIG_CMD_DHCP
#define CONFIG_CMD_PING
#define CONFIG_CMD_SAVES
#define CONFIG_CMD_NAND
#define CONFIG_CMD_UBI
#define CONFIG_CMD_UBIFS
#define CONFIG_CMD_SF
#define CONFIG_CMD_EEPROM
#define CONFIG_CMD_USB

/* U-Boot general configuration */
#define CONFIG_MISC_INIT_R
#define CONFIG_CRC32_VERIFY
#define CONFIG_MX_CYCLIC
#define CONFIG_TIMESTAMP

/* EDMA3 */
#define CONFIG_TI_EDMA3

#define CONFIG_BOOTFILE			"uImage"
#define CONFIG_EXTRA_ENV_SETTINGS					\
	CONFIG_EXTRA_ENV_KS2_BOARD_SETTINGS				\
	"boot=ubi\0"							\
	"tftp_root=/\0"							\
	"nfs_root=/export\0"						\
	"mem_lpae=1\0"							\
	"mem_reserve=512M\0"						\
	"addr_fdt=0x87000000\0"						\
	"addr_kern=0x88000000\0"					\
	"addr_uboot=0x87000000\0"					\
	"addr_fs=0x82000000\0"						\
	"addr_ubi=0x82000000\0"						\
	"addr_secdb_key=0xc000000\0"					\
	"fdt_high=0xffffffff\0"						\
	"name_kern=uImage-keystone-evm.bin\0"				\
	"run_mon=mon_install ${addr_mon}\0"				\
	"run_kern=bootm ${addr_kern} - ${addr_fdt}\0"			\
	"init_net=run args_all args_net\0"				\
	"init_ubi=run args_all args_ubi; "				\
		"ubi part ubifs; ubifsmount ubi:boot;"			\
		"ubifsload ${addr_secdb_key} securedb.key.bin;\0"       \
	"get_fdt_net=dhcp ${addr_fdt} ${tftp_root}/${name_fdt}\0"	\
	"get_fdt_ubi=ubifsload ${addr_fdt} ${name_fdt}\0"		\
	"get_kern_net=dhcp ${addr_kern} ${tftp_root}/${name_kern}\0"	\
	"get_kern_ubi=ubifsload ${addr_kern} ${name_kern}\0"		\
	"get_mon_net=dhcp ${addr_mon} ${tftp_root}/${name_mon}\0"	\
	"get_mon_ubi=ubifsload ${addr_mon} ${name_mon}\0"		\
	"get_uboot_net=dhcp ${addr_uboot} ${tftp_root}/${name_uboot}\0"	\
	"burn_uboot_spi=sf probe; sf erase 0 0x100000; "		\
		"sf write ${addr_uboot} 0 ${filesize}\0"		\
	"burn_uboot_nand=nand erase 0 0x100000; "			\
		"nand write ${addr_uboot} 0 ${filesize}\0"		\
	"args_all=setenv bootargs console=ttyS0,115200n8 rootwait=1\0"	\
	"args_net=setenv bootargs ${bootargs} rootfstype=nfs "		\
		"root=/dev/nfs rw nfsroot=${serverip}:${nfs_root},"	\
		"${nfs_options} ip=dhcp\0"				\
	"nfs_options=v3,tcp,rsize=4096,wsize=4096\0"			\
	"get_fdt_ramfs=dhcp ${addr_fdt} ${tftp_root}/${name_fdt}\0"	\
	"get_kern_ramfs=dhcp ${addr_kern} ${tftp_root}/${name_kern}\0"	\
	"get_mon_ramfs=dhcp ${addr_mon} ${tftp_root}/${name_mon}\0"	\
	"get_fs_ramfs=dhcp ${addr_fs} ${tftp_root}/${name_fs}\0"	\
	"get_ubi_net=dhcp ${addr_ubi} ${tftp_root}/${name_ubi}\0"	\
	"burn_ubi=nand erase.part ubifs; "				\
		"nand write ${addr_ubi} ubifs ${filesize}\0"		\
	"init_ramfs=run args_all args_ramfs get_fs_ramfs\0"		\
	"args_ramfs=setenv bootargs ${bootargs} "			\
		"rdinit=/sbin/init rw root=/dev/ram0 "			\
		"initrd=0x802000000,9M\0"				\
	"no_post=1\0"							\
	"mtdparts=mtdparts=davinci_nand.0:"				\
		"1024k(bootloader)ro,512k(params)ro,-(ubifs)\0"

#define CONFIG_BOOTCOMMAND						\
	"run init_${boot} get_fdt_${boot} get_mon_${boot} "		\
		"get_kern_${boot} run_mon run_kern"

#define CONFIG_BOOTARGS							\

/* Linux interfacing */
#define CONFIG_OF_BOARD_SETUP

/* Now for the remaining common defines */
#include <configs/ti_armv7_common.h>

/* We wont be loading up OS from SPL for now.. */
#undef CONFIG_SPL_OS_BOOT

/* We do not have MMC support.. yet.. */
#undef CONFIG_SPL_LIBDISK_SUPPORT
#undef CONFIG_SPL_MMC_SUPPORT
#undef CONFIG_SPL_FAT_SUPPORT
#undef CONFIG_SPL_EXT_SUPPORT
#undef CONFIG_MMC
#undef CONFIG_GENERIC_MMC
#undef CONFIG_CMD_MMC

/* And no support for GPIO, yet.. */
#undef CONFIG_SPL_GPIO_SUPPORT
#undef CONFIG_CMD_GPIO

/* we may include files below only after all above definitions */
#include <asm/arch/hardware.h>
#include <asm/arch/clock.h>
#define CONFIG_SYS_HZ_CLOCK		clk_get_rate(KS2_CLK1_6)

#endif /* __CONFIG_KS2_EVM_H */
Commit	Line	Data
2221cd12 HZ	1	/*
	2	* Common configuration header file for all Keystone II EVM platforms
	3	*
	4	* (C) Copyright 2012-2014
	5	* Texas Instruments Incorporated, <www.ti.com>
	6	*
	7	* SPDX-License-Identifier: GPL-2.0+
	8	*/
	9
	10	#ifndef __CONFIG_KS2_EVM_H
	11	#define __CONFIG_KS2_EVM_H
	12
	13	#define CONFIG_SOC_KEYSTONE
	14
	15	/* U-Boot Build Configuration */
	16	#define CONFIG_SKIP_LOWLEVEL_INIT /* U-Boot is a 2nd stage loader */
2221cd12	17	#define CONFIG_BOARD_EARLY_INIT_F
2221cd12 HZ	18
2221cd12 HZ	19	/* SoC Configuration */
2221cd12 HZ	20	#define CONFIG_ARCH_CPU_INIT
2221cd12 HZ	21	#define CONFIG_SYS_ARCH_TIMER
2221cd12 HZ	22	#define CONFIG_SYS_TEXT_BASE 0x0c001000
	23	#define CONFIG_SPL_TARGET "u-boot-spi.gph"
	24	#define CONFIG_SYS_DCACHE_OFF
	25
	26	/* Memory Configuration */
	27	#define CONFIG_NR_DRAM_BANKS 2
2221cd12 HZ	28	#define CONFIG_SYS_LPAE_SDRAM_BASE 0x800000000
	29	#define CONFIG_MAX_RAM_BANK_SIZE (2 << 30) /* 2GB */
	30	#define CONFIG_STACKSIZE (512 << 10) /* 512 KiB */
2221cd12 HZ	31	#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_TEXT_BASE - \
	32	GENERATED_GBL_DATA_SIZE)
	33
	34	/* SPL SPI Loader Configuration */
	35	#define CONFIG_SPL_PAD_TO 65536
	36	#define CONFIG_SPL_MAX_SIZE (CONFIG_SPL_PAD_TO - 8)
	37	#define CONFIG_SPL_BSS_START_ADDR (CONFIG_SPL_TEXT_BASE + \
	38	CONFIG_SPL_MAX_SIZE)
	39	#define CONFIG_SPL_BSS_MAX_SIZE (32 * 1024)
	40	#define CONFIG_SYS_SPL_MALLOC_START (CONFIG_SPL_BSS_START_ADDR + \
	41	CONFIG_SPL_BSS_MAX_SIZE)
	42	#define CONFIG_SYS_SPL_MALLOC_SIZE (32 * 1024)
	43	#define CONFIG_SPL_STACK_SIZE (8 * 1024)
	44	#define CONFIG_SPL_STACK (CONFIG_SYS_SPL_MALLOC_START + \
	45	CONFIG_SYS_SPL_MALLOC_SIZE + \
	46	CONFIG_SPL_STACK_SIZE - 4)
2221cd12 HZ	47	#define CONFIG_SPL_SPI_FLASH_SUPPORT
2221cd12 HZ	48	#define CONFIG_SPL_SPI_SUPPORT
2221cd12	49	#define CONFIG_SPL_SPI_LOAD
2221cd12	50	#define CONFIG_SYS_SPI_U_BOOT_OFFS CONFIG_SPL_PAD_TO
2221cd12 HZ	51
	52	/* UART Configuration */
	53	#define CONFIG_SYS_NS16550
	54	#define CONFIG_SYS_NS16550_SERIAL
	55	#define CONFIG_SYS_NS16550_MEM32
	56	#define CONFIG_SYS_NS16550_REG_SIZE -4
	57	#define CONFIG_SYS_NS16550_COM1 KS2_UART0_BASE
	58	#define CONFIG_SYS_NS16550_COM2 KS2_UART1_BASE
	59	#define CONFIG_SYS_NS16550_CLK clk_get_rate(KS2_CLK1_6)
	60	#define CONFIG_CONS_INDEX 1
2221cd12 HZ	61
2221cd12 HZ	62	/* SPI Configuration */
2221cd12 HZ	63	#define CONFIG_SPI_FLASH_STMICRO
2221cd12 HZ	64	#define CONFIG_DAVINCI_SPI
4dca7f0a	65	#define CONFIG_SYS_SPI_CLK clk_get_rate(KS2_CLK1_6)
2221cd12 HZ	66	#define CONFIG_SF_DEFAULT_SPEED 30000000
	67	#define CONFIG_ENV_SPI_MAX_HZ CONFIG_SF_DEFAULT_SPEED
	68	#define CONFIG_SYS_SPI0
	69	#define CONFIG_SYS_SPI_BASE KS2_SPI0_BASE
	70	#define CONFIG_SYS_SPI0_NUM_CS 4
	71	#define CONFIG_SYS_SPI1
	72	#define CONFIG_SYS_SPI1_BASE KS2_SPI1_BASE
	73	#define CONFIG_SYS_SPI1_NUM_CS 4
	74	#define CONFIG_SYS_SPI2
	75	#define CONFIG_SYS_SPI2_BASE KS2_SPI2_BASE
	76	#define CONFIG_SYS_SPI2_NUM_CS 4
	77
	78	/* Network Configuration */
3fe93623 KI	79	#define CONFIG_PHYLIB
3fe93623 KI	80	#define CONFIG_PHY_MARVELL
2221cd12 HZ	81	#define CONFIG_MII
	82	#define CONFIG_BOOTP_DEFAULT
	83	#define CONFIG_BOOTP_DNS
	84	#define CONFIG_BOOTP_DNS2
	85	#define CONFIG_BOOTP_SEND_HOSTNAME
	86	#define CONFIG_NET_RETRY_COUNT 32
2221cd12 HZ	87	#define CONFIG_SYS_SGMII_REFCLK_MHZ 312
	88	#define CONFIG_SYS_SGMII_LINERATE_MHZ 1250
	89	#define CONFIG_SYS_SGMII_RATESCALE 2
	90
ef454717	91	/* Keyston Navigator Configuration */
796bcee6	92	#define CONFIG_TI_KSNAV
ef454717 KI	93	#define CONFIG_KSNAV_QM_BASE_ADDRESS KS2_QM_BASE_ADDRESS
	94	#define CONFIG_KSNAV_QM_CONF_BASE KS2_QM_CONF_BASE
	95	#define CONFIG_KSNAV_QM_DESC_SETUP_BASE KS2_QM_DESC_SETUP_BASE
	96	#define CONFIG_KSNAV_QM_STATUS_RAM_BASE KS2_QM_STATUS_RAM_BASE
	97	#define CONFIG_KSNAV_QM_INTD_CONF_BASE KS2_QM_INTD_CONF_BASE
	98	#define CONFIG_KSNAV_QM_PDSP1_CMD_BASE KS2_QM_PDSP1_CMD_BASE
	99	#define CONFIG_KSNAV_QM_PDSP1_CTRL_BASE KS2_QM_PDSP1_CTRL_BASE
	100	#define CONFIG_KSNAV_QM_PDSP1_IRAM_BASE KS2_QM_PDSP1_IRAM_BASE
	101	#define CONFIG_KSNAV_QM_MANAGER_QUEUES_BASE KS2_QM_MANAGER_QUEUES_BASE
	102	#define CONFIG_KSNAV_QM_MANAGER_Q_PROXY_BASE KS2_QM_MANAGER_Q_PROXY_BASE
	103	#define CONFIG_KSNAV_QM_QUEUE_STATUS_BASE KS2_QM_QUEUE_STATUS_BASE
	104	#define CONFIG_KSNAV_QM_LINK_RAM_BASE KS2_QM_LINK_RAM_BASE
	105	#define CONFIG_KSNAV_QM_REGION_NUM KS2_QM_REGION_NUM
	106	#define CONFIG_KSNAV_QM_QPOOL_NUM KS2_QM_QPOOL_NUM
	107
	108	/* NETCP pktdma */
796bcee6	109	#define CONFIG_KSNAV_PKTDMA_NETCP
ef454717 KI	110	#define CONFIG_KSNAV_NETCP_PDMA_CTRL_BASE KS2_NETCP_PDMA_CTRL_BASE
	111	#define CONFIG_KSNAV_NETCP_PDMA_TX_BASE KS2_NETCP_PDMA_TX_BASE
	112	#define CONFIG_KSNAV_NETCP_PDMA_TX_CH_NUM KS2_NETCP_PDMA_TX_CH_NUM
	113	#define CONFIG_KSNAV_NETCP_PDMA_RX_BASE KS2_NETCP_PDMA_RX_BASE
	114	#define CONFIG_KSNAV_NETCP_PDMA_RX_CH_NUM KS2_NETCP_PDMA_RX_CH_NUM
	115	#define CONFIG_KSNAV_NETCP_PDMA_SCHED_BASE KS2_NETCP_PDMA_SCHED_BASE
	116	#define CONFIG_KSNAV_NETCP_PDMA_RX_FLOW_BASE KS2_NETCP_PDMA_RX_FLOW_BASE
	117	#define CONFIG_KSNAV_NETCP_PDMA_RX_FLOW_NUM KS2_NETCP_PDMA_RX_FLOW_NUM
	118	#define CONFIG_KSNAV_NETCP_PDMA_RX_FREE_QUEUE KS2_NETCP_PDMA_RX_FREE_QUEUE
	119	#define CONFIG_KSNAV_NETCP_PDMA_RX_RCV_QUEUE KS2_NETCP_PDMA_RX_RCV_QUEUE
	120	#define CONFIG_KSNAV_NETCP_PDMA_TX_SND_QUEUE KS2_NETCP_PDMA_TX_SND_QUEUE
	121
0935cac6	122	/* Keystone net */
796bcee6	123	#define CONFIG_DRIVER_TI_KEYSTONE_NET
92a16c81 HZ	124	#define CONFIG_KSNET_MAC_ID_BASE KS2_MAC_ID_BASE_ADDR
	125	#define CONFIG_KSNET_NETCP_BASE KS2_NETCP_BASE
	126	#define CONFIG_KSNET_SERDES_SGMII_BASE KS2_SGMII_SERDES_BASE
3c61502a	127	#define CONFIG_KSNET_SERDES_SGMII2_BASE KS2_SGMII_SERDES2_BASE
92a16c81	128	#define CONFIG_KSNET_SERDES_LANES_PER_SGMII KS2_LANES_PER_SGMII_SERDES
0935cac6	129
87ac27bd KI	130	/* SerDes */
	131	#define CONFIG_TI_KEYSTONE_SERDES
	132
2221cd12 HZ	133	/* AEMIF */
	134	#define CONFIG_TI_AEMIF
	135	#define CONFIG_AEMIF_CNTRL_BASE KS2_AEMIF_CNTRL_BASE
	136
	137	/* I2C Configuration */
2221cd12 HZ	138	#define CONFIG_SYS_I2C_DAVINCI
	139	#define CONFIG_SYS_DAVINCI_I2C_SPEED 100000
	140	#define CONFIG_SYS_DAVINCI_I2C_SLAVE 0x10 /* SMBus host address */
	141	#define CONFIG_SYS_DAVINCI_I2C_SPEED1 100000
	142	#define CONFIG_SYS_DAVINCI_I2C_SLAVE1 0x10 /* SMBus host address */
	143	#define CONFIG_SYS_DAVINCI_I2C_SPEED2 100000
	144	#define CONFIG_SYS_DAVINCI_I2C_SLAVE2 0x10 /* SMBus host address */
	145	#define I2C_BUS_MAX 3
	146
	147	/* EEPROM definitions */
	148	#define CONFIG_SYS_I2C_MULTI_EEPROMS
	149	#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
	150	#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50
	151	#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 6
	152	#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 20
	153	#define CONFIG_ENV_EEPROM_IS_ON_I2C
	154
	155	/* NAND Configuration */
	156	#define CONFIG_NAND_DAVINCI
	157	#define CONFIG_KEYSTONE_RBL_NAND
	158	#define CONFIG_KEYSTONE_NAND_MAX_RBL_SIZE CONFIG_ENV_OFFSET
	159	#define CONFIG_SYS_NAND_MASK_CLE 0x4000
	160	#define CONFIG_SYS_NAND_MASK_ALE 0x2000
	161	#define CONFIG_SYS_NAND_CS 2
	162	#define CONFIG_SYS_NAND_USE_FLASH_BBT
	163	#define CONFIG_SYS_NAND_4BIT_HW_ECC_OOBFIRST
	164
	165	#define CONFIG_SYS_NAND_LARGEPAGE
	166	#define CONFIG_SYS_NAND_BASE_LIST { 0x30000000, }
	167	#define CONFIG_SYS_MAX_NAND_DEVICE 1
	168	#define CONFIG_SYS_NAND_MAX_CHIPS 1
	169	#define CONFIG_SYS_NAND_NO_SUBPAGE_WRITE
	170	#define CONFIG_ENV_SIZE (256 << 10) /* 256 KiB */
	171	#define CONFIG_ENV_IS_IN_NAND
	172	#define CONFIG_ENV_OFFSET 0x100000
	173	#define CONFIG_MTD_PARTITIONS
2221cd12 HZ	174	#define CONFIG_RBTREE
	175	#define CONFIG_LZO
	176	#define MTDIDS_DEFAULT "nand0=davinci_nand.0"
	177	#define MTDPARTS_DEFAULT "mtdparts=davinci_nand.0:" \
	178	"1024k(bootloader)ro,512k(params)ro," \
	179	"-(ubifs)"
	180
bc0e8d7c WK	181	/* USB Configuration */
bc0e8d7c WK	182	#define CONFIG_USB_XHCI
792651f0	183	#define CONFIG_USB_XHCI_DWC3
bc0e8d7c WK	184	#define CONFIG_USB_XHCI_KEYSTONE
bc0e8d7c WK	185	#define CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS 2
bc0e8d7c WK	186	#define CONFIG_EFI_PARTITION
	187	#define CONFIG_FS_FAT
	188	#define CONFIG_SYS_CACHELINE_SIZE 64
	189	#define CONFIG_USB_SS_BASE KS2_USB_SS_BASE
	190	#define CONFIG_USB_HOST_XHCI_BASE KS2_USB_HOST_XHCI_BASE
	191	#define CONFIG_DEV_USB_PHY_BASE KS2_DEV_USB_PHY_BASE
	192	#define CONFIG_USB_PHY_CFG_BASE KS2_USB_PHY_CFG_BASE
	193
2221cd12	194	/* U-Boot command configuration */
2221cd12	195	#define CONFIG_CMD_DHCP
2221cd12 HZ	196	#define CONFIG_CMD_PING
2221cd12 HZ	197	#define CONFIG_CMD_SAVES
2221cd12 HZ	198	#define CONFIG_CMD_NAND
	199	#define CONFIG_CMD_UBI
	200	#define CONFIG_CMD_UBIFS
	201	#define CONFIG_CMD_SF
	202	#define CONFIG_CMD_EEPROM
bc0e8d7c	203	#define CONFIG_CMD_USB
2221cd12 HZ	204
2221cd12 HZ	205	/* U-Boot general configuration */
8347210a	206	#define CONFIG_MISC_INIT_R
2221cd12 HZ	207	#define CONFIG_CRC32_VERIFY
2221cd12 HZ	208	#define CONFIG_MX_CYCLIC
2221cd12 HZ	209	#define CONFIG_TIMESTAMP
	210
	211	/* EDMA3 */
	212	#define CONFIG_TI_EDMA3
	213
2221cd12 HZ	214	#define CONFIG_BOOTFILE "uImage"
2221cd12 HZ	215	#define CONFIG_EXTRA_ENV_SETTINGS \
349c26dd	216	CONFIG_EXTRA_ENV_KS2_BOARD_SETTINGS \
b7d9f9ca	217	"boot=ubi\0" \
2221cd12 HZ	218	"tftp_root=/\0" \
	219	"nfs_root=/export\0" \
	220	"mem_lpae=1\0" \
	221	"mem_reserve=512M\0" \
	222	"addr_fdt=0x87000000\0" \
	223	"addr_kern=0x88000000\0" \
2221cd12 HZ	224	"addr_uboot=0x87000000\0" \
	225	"addr_fs=0x82000000\0" \
	226	"addr_ubi=0x82000000\0" \
	227	"addr_secdb_key=0xc000000\0" \
	228	"fdt_high=0xffffffff\0" \
dd31079e	229	"name_kern=uImage-keystone-evm.bin\0" \
2221cd12 HZ	230	"run_mon=mon_install ${addr_mon}\0" \
	231	"run_kern=bootm ${addr_kern} - ${addr_fdt}\0" \
	232	"init_net=run args_all args_net\0" \
	233	"init_ubi=run args_all args_ubi; " \
ff52e3b4	234	"ubi part ubifs; ubifsmount ubi:boot;" \
2221cd12 HZ	235	"ubifsload ${addr_secdb_key} securedb.key.bin;\0" \
	236	"get_fdt_net=dhcp ${addr_fdt} ${tftp_root}/${name_fdt}\0" \
	237	"get_fdt_ubi=ubifsload ${addr_fdt} ${name_fdt}\0" \
	238	"get_kern_net=dhcp ${addr_kern} ${tftp_root}/${name_kern}\0" \
	239	"get_kern_ubi=ubifsload ${addr_kern} ${name_kern}\0" \
	240	"get_mon_net=dhcp ${addr_mon} ${tftp_root}/${name_mon}\0" \
	241	"get_mon_ubi=ubifsload ${addr_mon} ${name_mon}\0" \
	242	"get_uboot_net=dhcp ${addr_uboot} ${tftp_root}/${name_uboot}\0" \
	243	"burn_uboot_spi=sf probe; sf erase 0 0x100000; " \
	244	"sf write ${addr_uboot} 0 ${filesize}\0" \
	245	"burn_uboot_nand=nand erase 0 0x100000; " \
	246	"nand write ${addr_uboot} 0 ${filesize}\0" \
	247	"args_all=setenv bootargs console=ttyS0,115200n8 rootwait=1\0" \
2221cd12 HZ	248	"args_net=setenv bootargs ${bootargs} rootfstype=nfs " \
	249	"root=/dev/nfs rw nfsroot=${serverip}:${nfs_root}," \
	250	"${nfs_options} ip=dhcp\0" \
	251	"nfs_options=v3,tcp,rsize=4096,wsize=4096\0" \
	252	"get_fdt_ramfs=dhcp ${addr_fdt} ${tftp_root}/${name_fdt}\0" \
	253	"get_kern_ramfs=dhcp ${addr_kern} ${tftp_root}/${name_kern}\0" \
	254	"get_mon_ramfs=dhcp ${addr_mon} ${tftp_root}/${name_mon}\0" \
	255	"get_fs_ramfs=dhcp ${addr_fs} ${tftp_root}/${name_fs}\0" \
	256	"get_ubi_net=dhcp ${addr_ubi} ${tftp_root}/${name_ubi}\0" \
	257	"burn_ubi=nand erase.part ubifs; " \
	258	"nand write ${addr_ubi} ubifs ${filesize}\0" \
	259	"init_ramfs=run args_all args_ramfs get_fs_ramfs\0" \
	260	"args_ramfs=setenv bootargs ${bootargs} " \
	261	"rdinit=/sbin/init rw root=/dev/ram0 " \
	262	"initrd=0x802000000,9M\0" \
	263	"no_post=1\0" \
	264	"mtdparts=mtdparts=davinci_nand.0:" \
	265	"1024k(bootloader)ro,512k(params)ro,-(ubifs)\0"
	266
	267	#define CONFIG_BOOTCOMMAND \
	268	"run init_${boot} get_fdt_${boot} get_mon_${boot} " \
	269	"get_kern_${boot} run_mon run_kern"
	270
	271	#define CONFIG_BOOTARGS \
	272
	273	/* Linux interfacing */
2221cd12	274	#define CONFIG_OF_BOARD_SETUP
2221cd12	275
e07cff11 NM	276	/* Now for the remaining common defines */
	277	#include <configs/ti_armv7_common.h>
	278
	279	/* We wont be loading up OS from SPL for now.. */
	280	#undef CONFIG_SPL_OS_BOOT
	281
	282	/* We do not have MMC support.. yet.. */
	283	#undef CONFIG_SPL_LIBDISK_SUPPORT
	284	#undef CONFIG_SPL_MMC_SUPPORT
	285	#undef CONFIG_SPL_FAT_SUPPORT
	286	#undef CONFIG_SPL_EXT_SUPPORT
	287	#undef CONFIG_MMC
	288	#undef CONFIG_GENERIC_MMC
	289	#undef CONFIG_CMD_MMC
	290
	291	/* And no support for GPIO, yet.. */
	292	#undef CONFIG_SPL_GPIO_SUPPORT
	293	#undef CONFIG_CMD_GPIO
2221cd12 HZ	294
	295	/* we may include files below only after all above definitions */
	296	#include <asm/arch/hardware.h>
	297	#include <asm/arch/clock.h>
	298	#define CONFIG_SYS_HZ_CLOCK clk_get_rate(KS2_CLK1_6)
	299
2221cd12	300	#endif /* __CONFIG_KS2_EVM_H */