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Commit | Line | Data |
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2221cd12 HZ |
1 | /* |
2 | * Common configuration header file for all Keystone II EVM platforms | |
3 | * | |
4 | * (C) Copyright 2012-2014 | |
5 | * Texas Instruments Incorporated, <www.ti.com> | |
6 | * | |
7 | * SPDX-License-Identifier: GPL-2.0+ | |
8 | */ | |
9 | ||
10 | #ifndef __CONFIG_KS2_EVM_H | |
11 | #define __CONFIG_KS2_EVM_H | |
12 | ||
13 | #define CONFIG_SOC_KEYSTONE | |
14 | ||
15 | /* U-Boot Build Configuration */ | |
16 | #define CONFIG_SKIP_LOWLEVEL_INIT /* U-Boot is a 2nd stage loader */ | |
2221cd12 | 17 | #define CONFIG_BOARD_EARLY_INIT_F |
aeabe652 | 18 | #define CONFIG_DISPLAY_CPUINFO |
2221cd12 HZ |
19 | |
20 | /* SoC Configuration */ | |
2221cd12 HZ |
21 | #define CONFIG_ARCH_CPU_INIT |
22 | #define CONFIG_SYS_ARCH_TIMER | |
27ce6965 | 23 | #ifndef CONFIG_SYS_TEXT_BASE |
401f2d91 | 24 | #define CONFIG_SYS_TEXT_BASE 0x0c000000 |
27ce6965 | 25 | #endif |
2221cd12 HZ |
26 | #define CONFIG_SPL_TARGET "u-boot-spi.gph" |
27 | #define CONFIG_SYS_DCACHE_OFF | |
28 | ||
29 | /* Memory Configuration */ | |
30 | #define CONFIG_NR_DRAM_BANKS 2 | |
2221cd12 HZ |
31 | #define CONFIG_SYS_LPAE_SDRAM_BASE 0x800000000 |
32 | #define CONFIG_MAX_RAM_BANK_SIZE (2 << 30) /* 2GB */ | |
33 | #define CONFIG_STACKSIZE (512 << 10) /* 512 KiB */ | |
401f2d91 | 34 | #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SPL_TEXT_BASE - \ |
2221cd12 HZ |
35 | GENERATED_GBL_DATA_SIZE) |
36 | ||
aaf461f9 LV |
37 | #ifdef CONFIG_SYS_MALLOC_F_LEN |
38 | #define SPL_MALLOC_F_SIZE CONFIG_SYS_MALLOC_F_LEN | |
39 | #else | |
40 | #define SPL_MALLOC_F_SIZE 0 | |
41 | #endif | |
42 | ||
2221cd12 HZ |
43 | /* SPL SPI Loader Configuration */ |
44 | #define CONFIG_SPL_PAD_TO 65536 | |
45 | #define CONFIG_SPL_MAX_SIZE (CONFIG_SPL_PAD_TO - 8) | |
46 | #define CONFIG_SPL_BSS_START_ADDR (CONFIG_SPL_TEXT_BASE + \ | |
47 | CONFIG_SPL_MAX_SIZE) | |
48 | #define CONFIG_SPL_BSS_MAX_SIZE (32 * 1024) | |
49 | #define CONFIG_SYS_SPL_MALLOC_START (CONFIG_SPL_BSS_START_ADDR + \ | |
50 | CONFIG_SPL_BSS_MAX_SIZE) | |
51 | #define CONFIG_SYS_SPL_MALLOC_SIZE (32 * 1024) | |
52 | #define CONFIG_SPL_STACK_SIZE (8 * 1024) | |
53 | #define CONFIG_SPL_STACK (CONFIG_SYS_SPL_MALLOC_START + \ | |
54 | CONFIG_SYS_SPL_MALLOC_SIZE + \ | |
aaf461f9 | 55 | SPL_MALLOC_F_SIZE + \ |
2221cd12 | 56 | CONFIG_SPL_STACK_SIZE - 4) |
2221cd12 HZ |
57 | #define CONFIG_SPL_SPI_FLASH_SUPPORT |
58 | #define CONFIG_SPL_SPI_SUPPORT | |
2221cd12 | 59 | #define CONFIG_SPL_SPI_LOAD |
2221cd12 | 60 | #define CONFIG_SYS_SPI_U_BOOT_OFFS CONFIG_SPL_PAD_TO |
2221cd12 HZ |
61 | |
62 | /* UART Configuration */ | |
2221cd12 | 63 | #define CONFIG_SYS_NS16550_MEM32 |
391839fb LV |
64 | #if defined(CONFIG_SPL_BUILD) || !defined(CONFIG_DM_SERIAL) |
65 | #define CONFIG_SYS_NS16550_SERIAL | |
2221cd12 | 66 | #define CONFIG_SYS_NS16550_REG_SIZE -4 |
391839fb | 67 | #endif |
2221cd12 HZ |
68 | #define CONFIG_SYS_NS16550_COM1 KS2_UART0_BASE |
69 | #define CONFIG_SYS_NS16550_COM2 KS2_UART1_BASE | |
2221cd12 | 70 | #define CONFIG_CONS_INDEX 1 |
2221cd12 | 71 | |
e6d71e1c VA |
72 | #ifndef CONFIG_SOC_K2G |
73 | #define CONFIG_SYS_NS16550_CLK clk_get_rate(KS2_CLK1_6) | |
74 | #else | |
75 | #define CONFIG_SYS_NS16550_CLK clk_get_rate(uart_pll_clk) / 2 | |
76 | #endif | |
77 | ||
2221cd12 | 78 | /* SPI Configuration */ |
2221cd12 | 79 | #define CONFIG_DAVINCI_SPI |
4dca7f0a | 80 | #define CONFIG_SYS_SPI_CLK clk_get_rate(KS2_CLK1_6) |
2221cd12 HZ |
81 | #define CONFIG_SF_DEFAULT_SPEED 30000000 |
82 | #define CONFIG_ENV_SPI_MAX_HZ CONFIG_SF_DEFAULT_SPEED | |
83 | #define CONFIG_SYS_SPI0 | |
84 | #define CONFIG_SYS_SPI_BASE KS2_SPI0_BASE | |
85 | #define CONFIG_SYS_SPI0_NUM_CS 4 | |
86 | #define CONFIG_SYS_SPI1 | |
87 | #define CONFIG_SYS_SPI1_BASE KS2_SPI1_BASE | |
88 | #define CONFIG_SYS_SPI1_NUM_CS 4 | |
89 | #define CONFIG_SYS_SPI2 | |
90 | #define CONFIG_SYS_SPI2_BASE KS2_SPI2_BASE | |
91 | #define CONFIG_SYS_SPI2_NUM_CS 4 | |
92 | ||
93 | /* Network Configuration */ | |
3fe93623 KI |
94 | #define CONFIG_PHYLIB |
95 | #define CONFIG_PHY_MARVELL | |
2221cd12 HZ |
96 | #define CONFIG_MII |
97 | #define CONFIG_BOOTP_DEFAULT | |
98 | #define CONFIG_BOOTP_DNS | |
99 | #define CONFIG_BOOTP_DNS2 | |
100 | #define CONFIG_BOOTP_SEND_HOSTNAME | |
101 | #define CONFIG_NET_RETRY_COUNT 32 | |
2221cd12 HZ |
102 | #define CONFIG_SYS_SGMII_REFCLK_MHZ 312 |
103 | #define CONFIG_SYS_SGMII_LINERATE_MHZ 1250 | |
104 | #define CONFIG_SYS_SGMII_RATESCALE 2 | |
105 | ||
ef454717 | 106 | /* Keyston Navigator Configuration */ |
796bcee6 | 107 | #define CONFIG_TI_KSNAV |
ef454717 KI |
108 | #define CONFIG_KSNAV_QM_BASE_ADDRESS KS2_QM_BASE_ADDRESS |
109 | #define CONFIG_KSNAV_QM_CONF_BASE KS2_QM_CONF_BASE | |
110 | #define CONFIG_KSNAV_QM_DESC_SETUP_BASE KS2_QM_DESC_SETUP_BASE | |
111 | #define CONFIG_KSNAV_QM_STATUS_RAM_BASE KS2_QM_STATUS_RAM_BASE | |
112 | #define CONFIG_KSNAV_QM_INTD_CONF_BASE KS2_QM_INTD_CONF_BASE | |
113 | #define CONFIG_KSNAV_QM_PDSP1_CMD_BASE KS2_QM_PDSP1_CMD_BASE | |
114 | #define CONFIG_KSNAV_QM_PDSP1_CTRL_BASE KS2_QM_PDSP1_CTRL_BASE | |
115 | #define CONFIG_KSNAV_QM_PDSP1_IRAM_BASE KS2_QM_PDSP1_IRAM_BASE | |
116 | #define CONFIG_KSNAV_QM_MANAGER_QUEUES_BASE KS2_QM_MANAGER_QUEUES_BASE | |
117 | #define CONFIG_KSNAV_QM_MANAGER_Q_PROXY_BASE KS2_QM_MANAGER_Q_PROXY_BASE | |
118 | #define CONFIG_KSNAV_QM_QUEUE_STATUS_BASE KS2_QM_QUEUE_STATUS_BASE | |
119 | #define CONFIG_KSNAV_QM_LINK_RAM_BASE KS2_QM_LINK_RAM_BASE | |
120 | #define CONFIG_KSNAV_QM_REGION_NUM KS2_QM_REGION_NUM | |
121 | #define CONFIG_KSNAV_QM_QPOOL_NUM KS2_QM_QPOOL_NUM | |
122 | ||
123 | /* NETCP pktdma */ | |
796bcee6 | 124 | #define CONFIG_KSNAV_PKTDMA_NETCP |
ef454717 KI |
125 | #define CONFIG_KSNAV_NETCP_PDMA_CTRL_BASE KS2_NETCP_PDMA_CTRL_BASE |
126 | #define CONFIG_KSNAV_NETCP_PDMA_TX_BASE KS2_NETCP_PDMA_TX_BASE | |
127 | #define CONFIG_KSNAV_NETCP_PDMA_TX_CH_NUM KS2_NETCP_PDMA_TX_CH_NUM | |
128 | #define CONFIG_KSNAV_NETCP_PDMA_RX_BASE KS2_NETCP_PDMA_RX_BASE | |
129 | #define CONFIG_KSNAV_NETCP_PDMA_RX_CH_NUM KS2_NETCP_PDMA_RX_CH_NUM | |
130 | #define CONFIG_KSNAV_NETCP_PDMA_SCHED_BASE KS2_NETCP_PDMA_SCHED_BASE | |
131 | #define CONFIG_KSNAV_NETCP_PDMA_RX_FLOW_BASE KS2_NETCP_PDMA_RX_FLOW_BASE | |
132 | #define CONFIG_KSNAV_NETCP_PDMA_RX_FLOW_NUM KS2_NETCP_PDMA_RX_FLOW_NUM | |
133 | #define CONFIG_KSNAV_NETCP_PDMA_RX_FREE_QUEUE KS2_NETCP_PDMA_RX_FREE_QUEUE | |
134 | #define CONFIG_KSNAV_NETCP_PDMA_RX_RCV_QUEUE KS2_NETCP_PDMA_RX_RCV_QUEUE | |
135 | #define CONFIG_KSNAV_NETCP_PDMA_TX_SND_QUEUE KS2_NETCP_PDMA_TX_SND_QUEUE | |
136 | ||
0935cac6 | 137 | /* Keystone net */ |
796bcee6 | 138 | #define CONFIG_DRIVER_TI_KEYSTONE_NET |
92a16c81 HZ |
139 | #define CONFIG_KSNET_MAC_ID_BASE KS2_MAC_ID_BASE_ADDR |
140 | #define CONFIG_KSNET_NETCP_BASE KS2_NETCP_BASE | |
141 | #define CONFIG_KSNET_SERDES_SGMII_BASE KS2_SGMII_SERDES_BASE | |
3c61502a | 142 | #define CONFIG_KSNET_SERDES_SGMII2_BASE KS2_SGMII_SERDES2_BASE |
92a16c81 | 143 | #define CONFIG_KSNET_SERDES_LANES_PER_SGMII KS2_LANES_PER_SGMII_SERDES |
0935cac6 | 144 | |
87ac27bd KI |
145 | /* SerDes */ |
146 | #define CONFIG_TI_KEYSTONE_SERDES | |
147 | ||
2221cd12 HZ |
148 | #define CONFIG_AEMIF_CNTRL_BASE KS2_AEMIF_CNTRL_BASE |
149 | ||
150 | /* I2C Configuration */ | |
2221cd12 HZ |
151 | #define CONFIG_SYS_I2C_DAVINCI |
152 | #define CONFIG_SYS_DAVINCI_I2C_SPEED 100000 | |
153 | #define CONFIG_SYS_DAVINCI_I2C_SLAVE 0x10 /* SMBus host address */ | |
154 | #define CONFIG_SYS_DAVINCI_I2C_SPEED1 100000 | |
155 | #define CONFIG_SYS_DAVINCI_I2C_SLAVE1 0x10 /* SMBus host address */ | |
156 | #define CONFIG_SYS_DAVINCI_I2C_SPEED2 100000 | |
157 | #define CONFIG_SYS_DAVINCI_I2C_SLAVE2 0x10 /* SMBus host address */ | |
158 | #define I2C_BUS_MAX 3 | |
159 | ||
160 | /* EEPROM definitions */ | |
2221cd12 HZ |
161 | #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 |
162 | #define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 | |
163 | #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 6 | |
164 | #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 20 | |
165 | #define CONFIG_ENV_EEPROM_IS_ON_I2C | |
166 | ||
167 | /* NAND Configuration */ | |
168 | #define CONFIG_NAND_DAVINCI | |
169 | #define CONFIG_KEYSTONE_RBL_NAND | |
170 | #define CONFIG_KEYSTONE_NAND_MAX_RBL_SIZE CONFIG_ENV_OFFSET | |
171 | #define CONFIG_SYS_NAND_MASK_CLE 0x4000 | |
172 | #define CONFIG_SYS_NAND_MASK_ALE 0x2000 | |
173 | #define CONFIG_SYS_NAND_CS 2 | |
174 | #define CONFIG_SYS_NAND_USE_FLASH_BBT | |
175 | #define CONFIG_SYS_NAND_4BIT_HW_ECC_OOBFIRST | |
176 | ||
177 | #define CONFIG_SYS_NAND_LARGEPAGE | |
178 | #define CONFIG_SYS_NAND_BASE_LIST { 0x30000000, } | |
179 | #define CONFIG_SYS_MAX_NAND_DEVICE 1 | |
180 | #define CONFIG_SYS_NAND_MAX_CHIPS 1 | |
181 | #define CONFIG_SYS_NAND_NO_SUBPAGE_WRITE | |
182 | #define CONFIG_ENV_SIZE (256 << 10) /* 256 KiB */ | |
183 | #define CONFIG_ENV_IS_IN_NAND | |
184 | #define CONFIG_ENV_OFFSET 0x100000 | |
185 | #define CONFIG_MTD_PARTITIONS | |
2221cd12 HZ |
186 | #define CONFIG_RBTREE |
187 | #define CONFIG_LZO | |
188 | #define MTDIDS_DEFAULT "nand0=davinci_nand.0" | |
189 | #define MTDPARTS_DEFAULT "mtdparts=davinci_nand.0:" \ | |
190 | "1024k(bootloader)ro,512k(params)ro," \ | |
191 | "-(ubifs)" | |
192 | ||
bc0e8d7c WK |
193 | /* USB Configuration */ |
194 | #define CONFIG_USB_XHCI | |
792651f0 | 195 | #define CONFIG_USB_XHCI_DWC3 |
bc0e8d7c WK |
196 | #define CONFIG_USB_XHCI_KEYSTONE |
197 | #define CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS 2 | |
cc2c9487 | 198 | #define CONFIG_USB_STORAGE |
bc0e8d7c WK |
199 | #define CONFIG_EFI_PARTITION |
200 | #define CONFIG_FS_FAT | |
201 | #define CONFIG_SYS_CACHELINE_SIZE 64 | |
202 | #define CONFIG_USB_SS_BASE KS2_USB_SS_BASE | |
203 | #define CONFIG_USB_HOST_XHCI_BASE KS2_USB_HOST_XHCI_BASE | |
204 | #define CONFIG_DEV_USB_PHY_BASE KS2_DEV_USB_PHY_BASE | |
205 | #define CONFIG_USB_PHY_CFG_BASE KS2_USB_PHY_CFG_BASE | |
206 | ||
2221cd12 | 207 | /* U-Boot command configuration */ |
2221cd12 | 208 | #define CONFIG_CMD_DHCP |
2221cd12 HZ |
209 | #define CONFIG_CMD_PING |
210 | #define CONFIG_CMD_SAVES | |
2221cd12 HZ |
211 | #define CONFIG_CMD_UBI |
212 | #define CONFIG_CMD_UBIFS | |
213 | #define CONFIG_CMD_SF | |
214 | #define CONFIG_CMD_EEPROM | |
bc0e8d7c | 215 | #define CONFIG_CMD_USB |
2221cd12 HZ |
216 | |
217 | /* U-Boot general configuration */ | |
8347210a | 218 | #define CONFIG_MISC_INIT_R |
2221cd12 HZ |
219 | #define CONFIG_CRC32_VERIFY |
220 | #define CONFIG_MX_CYCLIC | |
2221cd12 HZ |
221 | #define CONFIG_TIMESTAMP |
222 | ||
223 | /* EDMA3 */ | |
224 | #define CONFIG_TI_EDMA3 | |
225 | ||
abca9477 MK |
226 | #define DEFAULT_FW_INITRAMFS_BOOT_ENV \ |
227 | "name_fw_rd=k2-fw-initrd.cpio.gz\0" \ | |
228 | "set_rd_spec=setenv rd_spec ${rdaddr}:${filesize}\0" \ | |
229 | "init_fw_rd_net=dhcp ${rdaddr} ${tftp_root}/${name_fw_rd}; " \ | |
230 | "run set_rd_spec\0" \ | |
231 | "init_fw_rd_ramfs=setenv rd_spec -\0" \ | |
232 | "init_fw_rd_ubi=ubifsload ${rdaddr} ${bootdir}/${name_fw_rd}; " \ | |
233 | "run set_rd_spec\0" \ | |
234 | ||
6f6e9439 NM |
235 | #define DEFAULT_PMMC_BOOT_ENV \ |
236 | "set_name_pmmc=setenv name_pmmc ti-sci-firmware-${soc_variant}.bin\0" \ | |
237 | "dev_pmmc=0\0" \ | |
238 | "get_pmmc_net=dhcp ${loadaddr} ${tftp_root}/${name_pmmc}\0" \ | |
239 | "get_pmmc_ramfs=run get_pmmc_net\0" \ | |
240 | "get_pmmc_mmc=load mmc ${bootpart} ${loadaddr} " \ | |
241 | "${bootdir}/${name_pmmc}\0" \ | |
242 | "get_pmmc_ubi=ubifsload ${loadaddr} ${bootdir}/${name_pmmc}\0" \ | |
243 | "run_pmmc=rproc init; rproc list; " \ | |
244 | "rproc load ${dev_pmmc} ${loadaddr} 0x${filesize}; " \ | |
245 | "rproc start ${dev_pmmc}\0" \ | |
246 | ||
2221cd12 | 247 | #define CONFIG_EXTRA_ENV_SETTINGS \ |
fd72d318 | 248 | DEFAULT_LINUX_BOOT_ENV \ |
349c26dd | 249 | CONFIG_EXTRA_ENV_KS2_BOARD_SETTINGS \ |
48dc1657 | 250 | "bootdir=/boot\0" \ |
2221cd12 HZ |
251 | "tftp_root=/\0" \ |
252 | "nfs_root=/export\0" \ | |
253 | "mem_lpae=1\0" \ | |
254 | "mem_reserve=512M\0" \ | |
2221cd12 HZ |
255 | "addr_ubi=0x82000000\0" \ |
256 | "addr_secdb_key=0xc000000\0" \ | |
bad773f4 | 257 | "name_kern=zImage\0" \ |
2221cd12 | 258 | "run_mon=mon_install ${addr_mon}\0" \ |
abca9477 | 259 | "run_kern=bootz ${loadaddr} ${rd_spec} ${fdtaddr}\0" \ |
2221cd12 | 260 | "init_net=run args_all args_net\0" \ |
c29a3ce4 | 261 | "init_nfs=setenv autoload no; dhcp; run args_all args_net\0" \ |
2221cd12 | 262 | "init_ubi=run args_all args_ubi; " \ |
8462cb57 | 263 | "ubi part ubifs; ubifsmount ubi:rootfs;\0" \ |
fd72d318 | 264 | "get_fdt_net=dhcp ${fdtaddr} ${tftp_root}/${name_fdt}\0" \ |
c29a3ce4 | 265 | "get_fdt_nfs=nfs ${fdtaddr} ${nfs_root}/boot/${name_fdt}\0" \ |
48dc1657 | 266 | "get_fdt_ubi=ubifsload ${fdtaddr} ${bootdir}/${name_fdt}\0" \ |
fd72d318 | 267 | "get_kern_net=dhcp ${loadaddr} ${tftp_root}/${name_kern}\0" \ |
c29a3ce4 | 268 | "get_kern_nfs=nfs ${loadaddr} ${nfs_root}/boot/${name_kern}\0" \ |
48dc1657 | 269 | "get_kern_ubi=ubifsload ${loadaddr} ${bootdir}/${name_kern}\0" \ |
2221cd12 | 270 | "get_mon_net=dhcp ${addr_mon} ${tftp_root}/${name_mon}\0" \ |
c29a3ce4 | 271 | "get_mon_nfs=nfs ${addr_mon} ${nfs_root}/boot/${name_mon}\0" \ |
48dc1657 | 272 | "get_mon_ubi=ubifsload ${addr_mon} ${bootdir}/${name_mon}\0" \ |
8889e984 | 273 | "get_uboot_net=dhcp ${loadaddr} ${tftp_root}/${name_uboot}\0" \ |
c29a3ce4 | 274 | "get_uboot_nfs=nfs ${loadaddr} ${nfs_root}/boot/${name_uboot}\0" \ |
7ec2328d | 275 | "burn_uboot_spi=sf probe; sf erase 0 0x80000; " \ |
8889e984 | 276 | "sf write ${loadaddr} 0 ${filesize}\0" \ |
2221cd12 | 277 | "burn_uboot_nand=nand erase 0 0x100000; " \ |
8889e984 | 278 | "nand write ${loadaddr} 0 ${filesize}\0" \ |
2221cd12 | 279 | "args_all=setenv bootargs console=ttyS0,115200n8 rootwait=1\0" \ |
2221cd12 HZ |
280 | "args_net=setenv bootargs ${bootargs} rootfstype=nfs " \ |
281 | "root=/dev/nfs rw nfsroot=${serverip}:${nfs_root}," \ | |
282 | "${nfs_options} ip=dhcp\0" \ | |
283 | "nfs_options=v3,tcp,rsize=4096,wsize=4096\0" \ | |
fd72d318 NM |
284 | "get_fdt_ramfs=dhcp ${fdtaddr} ${tftp_root}/${name_fdt}\0" \ |
285 | "get_kern_ramfs=dhcp ${loadaddr} ${tftp_root}/${name_kern}\0" \ | |
2221cd12 | 286 | "get_mon_ramfs=dhcp ${addr_mon} ${tftp_root}/${name_mon}\0" \ |
fd72d318 | 287 | "get_fs_ramfs=dhcp ${rdaddr} ${tftp_root}/${name_fs}\0" \ |
2221cd12 | 288 | "get_ubi_net=dhcp ${addr_ubi} ${tftp_root}/${name_ubi}\0" \ |
c29a3ce4 | 289 | "get_ubi_nfs=nfs ${addr_ubi} ${nfs_root}/boot/${name_ubi}\0" \ |
2221cd12 HZ |
290 | "burn_ubi=nand erase.part ubifs; " \ |
291 | "nand write ${addr_ubi} ubifs ${filesize}\0" \ | |
292 | "init_ramfs=run args_all args_ramfs get_fs_ramfs\0" \ | |
293 | "args_ramfs=setenv bootargs ${bootargs} " \ | |
294 | "rdinit=/sbin/init rw root=/dev/ram0 " \ | |
f06b454b | 295 | "initrd=0x808080000,80M\0" \ |
2221cd12 HZ |
296 | "no_post=1\0" \ |
297 | "mtdparts=mtdparts=davinci_nand.0:" \ | |
298 | "1024k(bootloader)ro,512k(params)ro,-(ubifs)\0" | |
299 | ||
6f6e9439 | 300 | #ifndef CONFIG_BOOTCOMMAND |
2221cd12 | 301 | #define CONFIG_BOOTCOMMAND \ |
abca9477 MK |
302 | "run init_${boot} init_fw_rd_${boot} get_fdt_${boot} " \ |
303 | "get_mon_${boot} get_kern_${boot} run_mon run_kern" | |
6f6e9439 | 304 | #endif |
2221cd12 HZ |
305 | |
306 | #define CONFIG_BOOTARGS \ | |
307 | ||
e07cff11 NM |
308 | /* Now for the remaining common defines */ |
309 | #include <configs/ti_armv7_common.h> | |
310 | ||
311 | /* We wont be loading up OS from SPL for now.. */ | |
312 | #undef CONFIG_SPL_OS_BOOT | |
313 | ||
314 | /* We do not have MMC support.. yet.. */ | |
315 | #undef CONFIG_SPL_LIBDISK_SUPPORT | |
316 | #undef CONFIG_SPL_MMC_SUPPORT | |
317 | #undef CONFIG_SPL_FAT_SUPPORT | |
318 | #undef CONFIG_SPL_EXT_SUPPORT | |
319 | #undef CONFIG_MMC | |
320 | #undef CONFIG_GENERIC_MMC | |
321 | #undef CONFIG_CMD_MMC | |
322 | ||
323 | /* And no support for GPIO, yet.. */ | |
324 | #undef CONFIG_SPL_GPIO_SUPPORT | |
2221cd12 HZ |
325 | |
326 | /* we may include files below only after all above definitions */ | |
327 | #include <asm/arch/hardware.h> | |
328 | #include <asm/arch/clock.h> | |
e6d71e1c | 329 | #ifndef CONFIG_SOC_K2G |
2221cd12 | 330 | #define CONFIG_SYS_HZ_CLOCK clk_get_rate(KS2_CLK1_6) |
e6d71e1c VA |
331 | #else |
332 | #define CONFIG_SYS_HZ_CLOCK external_clk[sys_clk] | |
333 | #endif | |
2221cd12 | 334 | |
2221cd12 | 335 | #endif /* __CONFIG_KS2_EVM_H */ |