[people/ms/u-boot.git] / include / configs / trats.h

/*
 * Copyright (C) 2011 Samsung Electronics
 * Heungjun Kim <riverful.kim@samsung.com>
 *
 * Configuation settings for the SAMSUNG TRATS (EXYNOS4210) board.
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

#ifndef __CONFIG_TRATS_H
#define __CONFIG_TRATS_H

#include <configs/exynos4-common.h>

#define CONFIG_TRATS

#define CONFIG_TIZEN			/* TIZEN lib */

#define CONFIG_SYS_L2CACHE_OFF
#ifndef CONFIG_SYS_L2CACHE_OFF
#define CONFIG_SYS_L2_PL310
#define CONFIG_SYS_PL310_BASE	0x10502000
#endif

/* TRATS has 4 banks of DRAM */
#define CONFIG_NR_DRAM_BANKS		4
#define CONFIG_SYS_SDRAM_BASE		0x40000000
#define PHYS_SDRAM_1			CONFIG_SYS_SDRAM_BASE
#define CONFIG_SYS_TEXT_BASE		0x63300000
#define SDRAM_BANK_SIZE			(256 << 20)	/* 256 MB */

/* memtest works on */
#define CONFIG_SYS_MEMTEST_START	CONFIG_SYS_SDRAM_BASE
#define CONFIG_SYS_MEMTEST_END		(CONFIG_SYS_SDRAM_BASE + 0x5000000)
#define CONFIG_SYS_LOAD_ADDR		(CONFIG_SYS_SDRAM_BASE + 0x4800000)

#define CONFIG_SYS_TEXT_BASE		0x63300000

/* select serial console configuration */
#define CONFIG_SERIAL2
#define CONFIG_BAUDRATE			115200

/* Console configuration */
#define CONFIG_SYS_CONSOLE_INFO_QUIET

/* MACH_TYPE_TRATS macro will be removed once added to mach-types */
#define MACH_TYPE_TRATS			3928
#define CONFIG_MACH_TYPE		MACH_TYPE_TRATS

#define CONFIG_BOOTARGS			"Please use defined boot"
#define CONFIG_BOOTCOMMAND		"run autoboot"
#define CONFIG_DEFAULT_CONSOLE		"console=ttySAC2,115200n8\0"

#define CONFIG_SYS_INIT_SP_ADDR	(CONFIG_SYS_LOAD_ADDR \
					- GENERATED_GBL_DATA_SIZE)

#define CONFIG_SYS_MEM_TOP_HIDE	(1 << 20)	/* ram console */

#define CONFIG_SYS_MONITOR_BASE	0x00000000

#define CONFIG_BOOTBLOCK		"10"
#define CONFIG_ENV_COMMON_BOOT		"${console} ${meminfo}"

#define CONFIG_ENV_IS_IN_MMC
#define CONFIG_SYS_MMC_ENV_DEV		CONFIG_MMC_DEFAULT_DEV
#define CONFIG_ENV_SIZE			4096
#define CONFIG_ENV_OFFSET		((32 - 4) << 10) /* 32KiB - 4KiB */

#define CONFIG_ENV_OVERWRITE

#define CONFIG_ENV_VARS_UBOOT_CONFIG
#define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG

/* Tizen - partitions definitions */
#define PARTS_CSA		"csa-mmc"
#define PARTS_BOOT		"boot"
#define PARTS_QBOOT		"qboot"
#define PARTS_CSC		"csc"
#define PARTS_ROOT		"platform"
#define PARTS_DATA		"data"
#define PARTS_UMS		"ums"

#define PARTS_DEFAULT \
	"uuid_disk=${uuid_gpt_disk};" \
	"name="PARTS_CSA",start=5MiB,size=8MiB,uuid=${uuid_gpt_"PARTS_CSA"};" \
	"name="PARTS_BOOT",size=60MiB,uuid=${uuid_gpt_"PARTS_BOOT"};" \
	"name="PARTS_QBOOT",size=100MiB,uuid=${uuid_gpt_"PARTS_QBOOT"};" \
	"name="PARTS_CSC",size=150MiB,uuid=${uuid_gpt_"PARTS_CSC"};" \
	"name="PARTS_ROOT",size=1536MiB,uuid=${uuid_gpt_"PARTS_ROOT"};" \
	"name="PARTS_DATA",size=3000MiB,uuid=${uuid_gpt_"PARTS_DATA"};" \
	"name="PARTS_UMS",size=-,uuid=${uuid_gpt_"PARTS_UMS"}\0" \

#define CONFIG_DFU_ALT \
	"u-boot raw 0x80 0x400;" \
	"/uImage ext4 0 2;" \
	"/modem.bin ext4 0 2;" \
	"/exynos4210-trats.dtb ext4 0 2;" \
	""PARTS_CSA" part 0 1;" \
	""PARTS_BOOT" part 0 2;" \
	""PARTS_QBOOT" part 0 3;" \
	""PARTS_CSC" part 0 4;" \
	""PARTS_ROOT" part 0 5;" \
	""PARTS_DATA" part 0 6;" \
	""PARTS_UMS" part 0 7;" \
	"params.bin raw 0x38 0x8;" \
	"/Image.itb ext4 0 2\0"

#define CONFIG_EXTRA_ENV_SETTINGS \
	"bootk=" \
		"run loaduimage;" \
		"if run loaddtb; then " \
			"bootm 0x40007FC0 - ${fdtaddr};" \
		"fi;" \
		"bootm 0x40007FC0;\0" \
	"updatebackup=" \
		"mmc dev 0 2; mmc write 0 0x42100000 0 0x200;" \
		"mmc dev 0 0\0" \
	"updatebootb=" \
		"mmc read 0 0x42100000 0x80 0x200; run updatebackup\0" \
	"lpj=lpj=3981312\0" \
	"nfsboot=" \
		"setenv bootargs root=/dev/nfs rw " \
		"nfsroot=${nfsroot},nolock,tcp " \
		"ip=${ipaddr}:${serverip}:${gatewayip}:" \
		"${netmask}:generic:usb0:off " CONFIG_ENV_COMMON_BOOT \
		"; run bootk\0" \
	"ramfsboot=" \
		"setenv bootargs root=/dev/ram0 rw rootfstype=ext2 " \
		"${console} ${meminfo} " \
		"initrd=0x43000000,8M ramdisk=8192\0" \
	"mmcboot=" \
		"setenv bootargs root=/dev/mmcblk${mmcdev}p${mmcrootpart} " \
		"${lpj} rootwait ${console} ${meminfo} ${opts} ${lcdinfo}; " \
		"run bootk\0" \
	"bootchart=setenv opts init=/sbin/bootchartd; run bootcmd\0" \
	"boottrace=setenv opts initcall_debug; run bootcmd\0" \
	"mmcoops=mmc read 0 0x40000000 0x40 8; md 0x40000000 0x400\0" \
	"verify=n\0" \
	"rootfstype=ext4\0" \
	"console=" CONFIG_DEFAULT_CONSOLE \
	"meminfo=crashkernel=32M@0x50000000\0" \
	"nfsroot=/nfsroot/arm\0" \
	"bootblock=" CONFIG_BOOTBLOCK "\0" \
	"loaduimage=ext4load mmc ${mmcdev}:${mmcbootpart} 0x40007FC0 uImage\0" \
	"loaddtb=ext4load mmc ${mmcdev}:${mmcbootpart} ${fdtaddr} " \
		"${fdtfile}\0" \
	"mmcdev=0\0" \
	"mmcbootpart=2\0" \
	"mmcrootpart=5\0" \
	"opts=always_resume=1\0" \
	"partitions=" PARTS_DEFAULT \
	"dfu_alt_info=" CONFIG_DFU_ALT \
	"spladdr=0x40000100\0" \
	"splsize=0x200\0" \
	"splfile=falcon.bin\0" \
	"spl_export=" \
		   "setexpr spl_imgsize ${splsize} + 8 ;" \
		   "setenv spl_imgsize 0x${spl_imgsize};" \
		   "setexpr spl_imgaddr ${spladdr} - 8 ;" \
		   "setexpr spl_addr_tmp ${spladdr} - 4 ;" \
		   "mw.b ${spl_imgaddr} 0x00 ${spl_imgsize};run loaduimage;" \
		   "setenv bootargs root=/dev/mmcblk${mmcdev}p${mmcrootpart} " \
		   "${lpj} rootwait ${console} ${meminfo} ${opts} ${lcdinfo};" \
		   "spl export atags 0x40007FC0;" \
		   "crc32 ${spladdr} ${splsize} ${spl_imgaddr};" \
		   "mw.l ${spl_addr_tmp} ${splsize};" \
		   "ext4write mmc ${mmcdev}:${mmcbootpart}" \
		   " /${splfile} ${spl_imgaddr} ${spl_imgsize};" \
		   "setenv spl_imgsize;" \
		   "setenv spl_imgaddr;" \
		   "setenv spl_addr_tmp;\0" \
	CONFIG_EXTRA_ENV_ITB \
	"fdtaddr=40800000\0" \

/* Falcon mode definitions */
#define CONFIG_CMD_SPL
#define CONFIG_SYS_SPL_ARGS_ADDR        CONFIG_SYS_SDRAM_BASE + 0x100

/* GPT */
#define CONFIG_RANDOM_UUID

/* I2C */
#include <asm/arch/gpio.h>

#define CONFIG_SYS_I2C
#define CONFIG_SYS_I2C_S3C24X0
#define CONFIG_SYS_I2C_S3C24X0_SPEED	100000
#define CONFIG_SYS_I2C_S3C24X0_SLAVE	0xFE
#define CONFIG_MAX_I2C_NUM		8
#define CONFIG_SYS_I2C_SOFT		/* I2C bit-banged */
#define CONFIG_SYS_I2C_SOFT_SPEED	50000
#define CONFIG_SYS_I2C_SOFT_SLAVE	0x7F
#define CONFIG_SOFT_I2C_READ_REPEATED_START
#define CONFIG_SYS_I2C_INIT_BOARD

/* I2C FG */
#define CONFIG_SOFT_I2C_GPIO_SCL EXYNOS4_GPIO_Y41
#define CONFIG_SOFT_I2C_GPIO_SDA EXYNOS4_GPIO_Y40

/* POWER */
#define CONFIG_POWER
#define CONFIG_POWER_I2C
#define CONFIG_POWER_MAX8997

#define CONFIG_POWER_FG
#define CONFIG_POWER_FG_MAX17042
#define CONFIG_POWER_MUIC
#define CONFIG_POWER_MUIC_MAX8997
#define CONFIG_POWER_BATTERY
#define CONFIG_POWER_BATTERY_TRATS

/* Security subsystem - enable hw_rand() */
#define CONFIG_EXYNOS_ACE_SHA
#define CONFIG_LIB_HW_RAND

/* Common misc for Samsung */
#define CONFIG_MISC_COMMON

#define CONFIG_MISC_INIT_R

/* Download menu - Samsung common */
#define CONFIG_LCD_MENU
#define CONFIG_LCD_MENU_BOARD

/* Download menu - definitions for check keys */
#ifndef __ASSEMBLY__
#include <power/max8997_pmic.h>

#define KEY_PWR_PMIC_NAME		"MAX8997_PMIC"
#define KEY_PWR_STATUS_REG		MAX8997_REG_STATUS1
#define KEY_PWR_STATUS_MASK		(1 << 0)
#define KEY_PWR_INTERRUPT_REG		MAX8997_REG_INT1
#define KEY_PWR_INTERRUPT_MASK		(1 << 0)

#define KEY_VOL_UP_GPIO			EXYNOS4_GPIO_X20
#define KEY_VOL_DOWN_GPIO		EXYNOS4_GPIO_X21
#endif /* __ASSEMBLY__ */

/* LCD console */
#define LCD_BPP			LCD_COLOR16
#define CONFIG_SYS_WHITE_ON_BLACK

/* LCD */
#define CONFIG_BMP_16BPP
#define CONFIG_FB_ADDR		0x52504000
#define CONFIG_EXYNOS_MIPI_DSIM
#define CONFIG_VIDEO_BMP_GZIP
#define CONFIG_SYS_VIDEO_LOGO_MAX_SIZE  ((500 * 160 * 4) + 54)

#endif	/* __CONFIG_H */
Commit	Line	Data
89f95492 HK	1	/*
	2	* Copyright (C) 2011 Samsung Electronics
	3	* Heungjun Kim <riverful.kim@samsung.com>
	4	*
	5	* Configuation settings for the SAMSUNG TRATS (EXYNOS4210) board.
	6	*
1a459660	7	* SPDX-License-Identifier: GPL-2.0+
89f95492 HK	8	*/
89f95492 HK	9
fe601647 PW	10	#ifndef __CONFIG_TRATS_H
fe601647 PW	11	#define __CONFIG_TRATS_H
89f95492	12
4c7bb1d2	13	#include <configs/exynos4-common.h>
fe601647	14
fe601647	15	#define CONFIG_TRATS
89f95492	16
fe601647	17	#define CONFIG_TIZEN /* TIZEN lib */
89f95492	18
c4e96dbf	19	#define CONFIG_SYS_L2CACHE_OFF
d0460b01 ŁM	20	#ifndef CONFIG_SYS_L2CACHE_OFF
	21	#define CONFIG_SYS_L2_PL310
	22	#define CONFIG_SYS_PL310_BASE 0x10502000
	23	#endif
89f95492	24
fe601647 PW	25	/* TRATS has 4 banks of DRAM */
fe601647 PW	26	#define CONFIG_NR_DRAM_BANKS 4
89f95492	27	#define CONFIG_SYS_SDRAM_BASE 0x40000000
fe601647	28	#define PHYS_SDRAM_1 CONFIG_SYS_SDRAM_BASE
89f95492	29	#define CONFIG_SYS_TEXT_BASE 0x63300000
fe601647	30	#define SDRAM_BANK_SIZE (256 << 20) /* 256 MB */
89f95492	31
fe601647 PW	32	/* memtest works on */
	33	#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE
	34	#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_SDRAM_BASE + 0x5000000)
	35	#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x4800000)
89f95492	36
fe601647	37	#define CONFIG_SYS_TEXT_BASE 0x63300000
89f95492	38
89f95492	39	/* select serial console configuration */
fe601647	40	#define CONFIG_SERIAL2
89f95492 HK	41	#define CONFIG_BAUDRATE 115200
89f95492 HK	42
fe601647 PW	43	/* Console configuration */
fe601647 PW	44	#define CONFIG_SYS_CONSOLE_INFO_QUIET
fe601647 PW	45
	46	/* MACH_TYPE_TRATS macro will be removed once added to mach-types */
	47	#define MACH_TYPE_TRATS 3928
	48	#define CONFIG_MACH_TYPE MACH_TYPE_TRATS
	49
89f95492	50	#define CONFIG_BOOTARGS "Please use defined boot"
0a1387bf	51	#define CONFIG_BOOTCOMMAND "run autoboot"
6afc3f6e	52	#define CONFIG_DEFAULT_CONSOLE "console=ttySAC2,115200n8\0"
fe601647 PW	53
	54	#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_LOAD_ADDR \
	55	- GENERATED_GBL_DATA_SIZE)
	56
	57	#define CONFIG_SYS_MEM_TOP_HIDE (1 << 20) /* ram console */
	58
	59	#define CONFIG_SYS_MONITOR_BASE 0x00000000
89f95492	60
89f95492 HK	61	#define CONFIG_BOOTBLOCK "10"
	62	#define CONFIG_ENV_COMMON_BOOT "${console} ${meminfo}"
	63
fe601647 PW	64	#define CONFIG_ENV_IS_IN_MMC
	65	#define CONFIG_SYS_MMC_ENV_DEV CONFIG_MMC_DEFAULT_DEV
	66	#define CONFIG_ENV_SIZE 4096
	67	#define CONFIG_ENV_OFFSET ((32 - 4) << 10) /* 32KiB - 4KiB */
	68
	69	#define CONFIG_ENV_OVERWRITE
	70
	71	#define CONFIG_ENV_VARS_UBOOT_CONFIG
	72	#define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
	73
9960d9a8 ŁM	74	/* Tizen - partitions definitions */
9960d9a8 ŁM	75	#define PARTS_CSA "csa-mmc"
9960d9a8	76	#define PARTS_BOOT "boot"
18f3e0eb PM	77	#define PARTS_QBOOT "qboot"
18f3e0eb PM	78	#define PARTS_CSC "csc"
9960d9a8 ŁM	79	#define PARTS_ROOT "platform"
9960d9a8 ŁM	80	#define PARTS_DATA "data"
9960d9a8 ŁM	81	#define PARTS_UMS "ums"
	82
	83	#define PARTS_DEFAULT \
	84	"uuid_disk=${uuid_gpt_disk};" \
18f3e0eb PM	85	"name="PARTS_CSA",start=5MiB,size=8MiB,uuid=${uuid_gpt_"PARTS_CSA"};" \
	86	"name="PARTS_BOOT",size=60MiB,uuid=${uuid_gpt_"PARTS_BOOT"};" \
	87	"name="PARTS_QBOOT",size=100MiB,uuid=${uuid_gpt_"PARTS_QBOOT"};" \
9960d9a8	88	"name="PARTS_CSC",size=150MiB,uuid=${uuid_gpt_"PARTS_CSC"};" \
18f3e0eb PM	89	"name="PARTS_ROOT",size=1536MiB,uuid=${uuid_gpt_"PARTS_ROOT"};" \
18f3e0eb PM	90	"name="PARTS_DATA",size=3000MiB,uuid=${uuid_gpt_"PARTS_DATA"};" \
9960d9a8 ŁM	91	"name="PARTS_UMS",size=-,uuid=${uuid_gpt_"PARTS_UMS"}\0" \
9960d9a8 ŁM	92
93a1ab57	93	#define CONFIG_DFU_ALT \
b7d4259a	94	"u-boot raw 0x80 0x400;" \
dcb7eb66 ŁM	95	"/uImage ext4 0 2;" \
	96	"/modem.bin ext4 0 2;" \
	97	"/exynos4210-trats.dtb ext4 0 2;" \
18f3e0eb	98	""PARTS_CSA" part 0 1;" \
cdd15bce	99	""PARTS_BOOT" part 0 2;" \
18f3e0eb PM	100	""PARTS_QBOOT" part 0 3;" \
18f3e0eb PM	101	""PARTS_CSC" part 0 4;" \
cdd15bce ŁM	102	""PARTS_ROOT" part 0 5;" \
cdd15bce ŁM	103	""PARTS_DATA" part 0 6;" \
a0afc6f3	104	""PARTS_UMS" part 0 7;" \
0a1387bf ŁM	105	"params.bin raw 0x38 0x8;" \
0a1387bf ŁM	106	"/Image.itb ext4 0 2\0"
93a1ab57	107
89f95492 HK	108	#define CONFIG_EXTRA_ENV_SETTINGS \
89f95492 HK	109	"bootk=" \
425e26de PW	110	"run loaduimage;" \
	111	"if run loaddtb; then " \
	112	"bootm 0x40007FC0 - ${fdtaddr};" \
	113	"fi;" \
	114	"bootm 0x40007FC0;\0" \
89f95492	115	"updatebackup=" \
188c42b3 JC	116	"mmc dev 0 2; mmc write 0 0x42100000 0 0x200;" \
188c42b3 JC	117	"mmc dev 0 0\0" \
89f95492 HK	118	"updatebootb=" \
	119	"mmc read 0 0x42100000 0x80 0x200; run updatebackup\0" \
	120	"lpj=lpj=3981312\0" \
	121	"nfsboot=" \
35777e22	122	"setenv bootargs root=/dev/nfs rw " \
89f95492 HK	123	"nfsroot=${nfsroot},nolock,tcp " \
	124	"ip=${ipaddr}:${serverip}:${gatewayip}:" \
	125	"${netmask}:generic:usb0:off " CONFIG_ENV_COMMON_BOOT \
	126	"; run bootk\0" \
	127	"ramfsboot=" \
35777e22	128	"setenv bootargs root=/dev/ram0 rw rootfstype=ext2 " \
89f95492 HK	129	"${console} ${meminfo} " \
	130	"initrd=0x43000000,8M ramdisk=8192\0" \
	131	"mmcboot=" \
35777e22	132	"setenv bootargs root=/dev/mmcblk${mmcdev}p${mmcrootpart} " \
89f95492	133	"${lpj} rootwait ${console} ${meminfo} ${opts} ${lcdinfo}; " \
425e26de	134	"run bootk\0" \
35777e22	135	"bootchart=setenv opts init=/sbin/bootchartd; run bootcmd\0" \
89f95492 HK	136	"boottrace=setenv opts initcall_debug; run bootcmd\0" \
	137	"mmcoops=mmc read 0 0x40000000 0x40 8; md 0x40000000 0x400\0" \
	138	"verify=n\0" \
	139	"rootfstype=ext4\0" \
	140	"console=" CONFIG_DEFAULT_CONSOLE \
	141	"meminfo=crashkernel=32M@0x50000000\0" \
	142	"nfsroot=/nfsroot/arm\0" \
	143	"bootblock=" CONFIG_BOOTBLOCK "\0" \
35777e22	144	"loaduimage=ext4load mmc ${mmcdev}:${mmcbootpart} 0x40007FC0 uImage\0" \
4ef400b9	145	"loaddtb=ext4load mmc ${mmcdev}:${mmcbootpart} ${fdtaddr} " \
ba223bb2	146	"${fdtfile}\0" \
89f95492 HK	147	"mmcdev=0\0" \
89f95492 HK	148	"mmcbootpart=2\0" \
35777e22	149	"mmcrootpart=5\0" \
93a1ab57	150	"opts=always_resume=1\0" \
9960d9a8	151	"partitions=" PARTS_DEFAULT \
35777e22 ŁM	152	"dfu_alt_info=" CONFIG_DFU_ALT \
	153	"spladdr=0x40000100\0" \
	154	"splsize=0x200\0" \
	155	"splfile=falcon.bin\0" \
	156	"spl_export=" \
	157	"setexpr spl_imgsize ${splsize} + 8 ;" \
dc993a65	158	"setenv spl_imgsize 0x${spl_imgsize};" \
35777e22 ŁM	159	"setexpr spl_imgaddr ${spladdr} - 8 ;" \
	160	"setexpr spl_addr_tmp ${spladdr} - 4 ;" \
	161	"mw.b ${spl_imgaddr} 0x00 ${spl_imgsize};run loaduimage;" \
	162	"setenv bootargs root=/dev/mmcblk${mmcdev}p${mmcrootpart} " \
	163	"${lpj} rootwait ${console} ${meminfo} ${opts} ${lcdinfo};" \
	164	"spl export atags 0x40007FC0;" \
	165	"crc32 ${spladdr} ${splsize} ${spl_imgaddr};" \
	166	"mw.l ${spl_addr_tmp} ${splsize};" \
	167	"ext4write mmc ${mmcdev}:${mmcbootpart}" \
	168	" /${splfile} ${spl_imgaddr} ${spl_imgsize};" \
	169	"setenv spl_imgsize;" \
	170	"setenv spl_imgaddr;" \
ba223bb2	171	"setenv spl_addr_tmp;\0" \
0a1387bf	172	CONFIG_EXTRA_ENV_ITB \
ba223bb2	173	"fdtaddr=40800000\0" \
ba223bb2	174
35777e22 ŁM	175	/* Falcon mode definitions */
35777e22 ŁM	176	#define CONFIG_CMD_SPL
fe601647	177	#define CONFIG_SYS_SPL_ARGS_ADDR CONFIG_SYS_SDRAM_BASE + 0x100
89f95492	178
9960d9a8	179	/* GPT */
aafd2c5d	180	#define CONFIG_RANDOM_UUID
9960d9a8	181
fe601647 PW	182	/* I2C */
fe601647 PW	183	#include <asm/arch/gpio.h>
9960d9a8	184
ea818dbb	185	#define CONFIG_SYS_I2C
2d8f1e27 PW	186	#define CONFIG_SYS_I2C_S3C24X0
	187	#define CONFIG_SYS_I2C_S3C24X0_SPEED 100000
	188	#define CONFIG_SYS_I2C_S3C24X0_SLAVE 0xFE
	189	#define CONFIG_MAX_I2C_NUM 8
ea818dbb HS	190	#define CONFIG_SYS_I2C_SOFT /* I2C bit-banged */
ea818dbb HS	191	#define CONFIG_SYS_I2C_SOFT_SPEED 50000
2d8f1e27	192	#define CONFIG_SYS_I2C_SOFT_SLAVE 0x7F
89f95492	193	#define CONFIG_SOFT_I2C_READ_REPEATED_START
fd8dca83	194	#define CONFIG_SYS_I2C_INIT_BOARD
fd8dca83	195
fd8dca83	196	/* I2C FG */
9b97b727 AS	197	#define CONFIG_SOFT_I2C_GPIO_SCL EXYNOS4_GPIO_Y41
9b97b727 AS	198	#define CONFIG_SOFT_I2C_GPIO_SDA EXYNOS4_GPIO_Y40
89f95492	199
fe601647	200	/* POWER */
be3b51aa ŁM	201	#define CONFIG_POWER
	202	#define CONFIG_POWER_I2C
	203	#define CONFIG_POWER_MAX8997
89f95492	204
5a77358c ŁM	205	#define CONFIG_POWER_FG
5a77358c ŁM	206	#define CONFIG_POWER_FG_MAX17042
7dcda99d ŁM	207	#define CONFIG_POWER_MUIC
7dcda99d ŁM	208	#define CONFIG_POWER_MUIC_MAX8997
61365ffc ŁM	209	#define CONFIG_POWER_BATTERY
61365ffc ŁM	210	#define CONFIG_POWER_BATTERY_TRATS
89f95492	211
e0021706 PM	212	/* Security subsystem - enable hw_rand() */
	213	#define CONFIG_EXYNOS_ACE_SHA
	214	#define CONFIG_LIB_HW_RAND
	215
679549d1 PM	216	/* Common misc for Samsung */
	217	#define CONFIG_MISC_COMMON
	218
	219	#define CONFIG_MISC_INIT_R
	220
00e64ab6 PM	221	/* Download menu - Samsung common */
	222	#define CONFIG_LCD_MENU
	223	#define CONFIG_LCD_MENU_BOARD
	224
	225	/* Download menu - definitions for check keys */
	226	#ifndef __ASSEMBLY__
	227	#include <power/max8997_pmic.h>
	228
	229	#define KEY_PWR_PMIC_NAME "MAX8997_PMIC"
	230	#define KEY_PWR_STATUS_REG MAX8997_REG_STATUS1
	231	#define KEY_PWR_STATUS_MASK (1 << 0)
	232	#define KEY_PWR_INTERRUPT_REG MAX8997_REG_INT1
	233	#define KEY_PWR_INTERRUPT_MASK (1 << 0)
	234
9b97b727 AS	235	#define KEY_VOL_UP_GPIO EXYNOS4_GPIO_X20
9b97b727 AS	236	#define KEY_VOL_DOWN_GPIO EXYNOS4_GPIO_X21
00e64ab6 PM	237	#endif /* __ASSEMBLY__ */
	238
	239	/* LCD console */
	240	#define LCD_BPP LCD_COLOR16
	241	#define CONFIG_SYS_WHITE_ON_BLACK
	242
51b1cd6d	243	/* LCD */
2df21cb3	244	#define CONFIG_BMP_16BPP
51b1cd6d	245	#define CONFIG_FB_ADDR 0x52504000
51b1cd6d	246	#define CONFIG_EXYNOS_MIPI_DSIM
90464971	247	#define CONFIG_VIDEO_BMP_GZIP
903afe18	248	#define CONFIG_SYS_VIDEO_LOGO_MAX_SIZE ((500 * 160 * 4) + 54)
51b1cd6d	249
89f95492	250	#endif /* __CONFIG_H */