[people/ms/u-boot.git] / include / configs / trizepsiv.h

/*
 * (C) Copyright 2007
 * Stefano Babic, DENX Gmbh, sbabic@denx.de
 *
 * (C) Copyright 2004
 * Robert Whaley, Applied Data Systems, Inc. rwhaley@applieddata.net
 *
 * (C) Copyright 2002
 * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net
 *
 * (C) Copyright 2002
 * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
 * Marius Groeger <mgroeger@sysgo.de>
 *
 * Configuation settings for the LUBBOCK board.
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */

#ifndef __CONFIG_H
#define __CONFIG_H

/*
 * High Level Configuration Options
 * (easy to change)
 */
#define CONFIG_CPU_PXA27X		1	/* This is an PXA27x CPU    */

#define CONFIG_MMC		1
#define CONFIG_BOARD_LATE_INIT
#define	CONFIG_SYS_TEXT_BASE	0x0

/* we will never enable dcache, because we have to setup MMU first */
#define CONFIG_SYS_DCACHE_OFF

#define RTC

/*
 * Size of malloc() pool
 */
#define CONFIG_SYS_MALLOC_LEN	    (CONFIG_ENV_SIZE + 128*1024)

/*
 * Hardware drivers
 */

/*
 * select serial console configuration
 */
#define CONFIG_PXA_SERIAL
#define CONFIG_SERIAL_MULTI
#define CONFIG_FFUART	       1       /* we use FFUART on Conxs */
#define CONFIG_BTUART	       1       /* we use BTUART on Conxs */
#define CONFIG_STUART	       1       /* we use STUART on Conxs */

/* allow to overwrite serial and ethaddr */
#define CONFIG_ENV_OVERWRITE

#define CONFIG_BAUDRATE	       38400

#define CONFIG_DOS_PARTITION   1

/*
 * Command line configuration.
 */
#include <config_cmd_default.h>

#define CONFIG_CMD_FAT
#define CONFIG_CMD_IMLS
#define CONFIG_CMD_PING
#define CONFIG_CMD_USB

/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */

#undef CONFIG_SHOW_BOOT_PROGRESS

#define CONFIG_BOOTDELAY	3
#define CONFIG_SERVERIP		192.168.1.99
#define CONFIG_BOOTCOMMAND	"run boot_flash"
#define CONFIG_BOOTARGS		"console=ttyS0,38400 ramdisk_size=12288"\
				" rw root=/dev/ram initrd=0xa0800000,5m"

#define CONFIG_EXTRA_ENV_SETTINGS					\
	"program_boot_mmc="						\
			"mw.b 0xa0010000 0xff 0x20000; "		\
			"if	 mmcinit && "				\
				"fatload mmc 0 0xa0010000 u-boot.bin; "	\
			"then "						\
				"protect off 0x0 0x1ffff; "		\
				"erase 0x0 0x1ffff; "			\
				"cp.b 0xa0010000 0x0 0x20000; "		\
			"fi\0"						\
	"program_uzImage_mmc="						\
			"mw.b 0xa0010000 0xff 0x180000; "		\
			"if	 mmcinit && "				\
				"fatload mmc 0 0xa0010000 uzImage; "	\
			"then "						\
				"protect off 0x40000 0x1bffff; "	\
				"erase 0x40000 0x1bffff; "		\
				"cp.b 0xa0010000 0x40000 0x180000; "	\
			"fi\0"						\
	"program_ramdisk_mmc="						\
			"mw.b 0xa0010000 0xff 0x500000; "		\
			"if	 mmcinit && "				\
				"fatload mmc 0 0xa0010000 ramdisk.gz; "	\
			"then "						\
				"protect off 0x1c0000 0x6bffff; "	\
				"erase 0x1c0000 0x6bffff; "		\
				"cp.b 0xa0010000 0x1c0000 0x500000; "	\
			"fi\0"						\
	"boot_mmc="							\
			"if	 mmcinit && "				\
				"fatload mmc 0 0xa0030000 uzImage && "	\
				"fatload mmc 0 0xa0800000 ramdisk.gz; "	\
			"then "						\
				"bootm 0xa0030000; "			\
			"fi\0"						\
	"boot_flash="							\
			"cp.b 0x1c0000 0xa0800000 0x500000; "		\
			"bootm 0x40000\0"				\

#define CONFIG_SETUP_MEMORY_TAGS 1
#define CONFIG_CMDLINE_TAG	 1	/* enable passing of ATAGs	*/
/* #define CONFIG_INITRD_TAG	 1 */

#if defined(CONFIG_CMD_KGDB)
#define CONFIG_KGDB_BAUDRATE	230400		/* speed to run kgdb serial port */
#define CONFIG_KGDB_SER_INDEX	2		/* which serial port to use */
#endif

/*
 * Miscellaneous configurable options
 */
#define CONFIG_SYS_HUSH_PARSER		1

#define CONFIG_SYS_LONGHELP				/* undef to save memory		*/
#ifdef CONFIG_SYS_HUSH_PARSER
#define CONFIG_SYS_PROMPT		"$ "		/* Monitor Command Prompt */
#else
#define CONFIG_SYS_PROMPT		"=> "		/* Monitor Command Prompt */
#endif
#define CONFIG_SYS_CBSIZE		256		/* Console I/O Buffer Size	*/
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
#define CONFIG_SYS_MAXARGS		16		/* max number of command args	*/
#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size	*/
#define CONFIG_SYS_DEVICE_NULLDEV	1

#define CONFIG_SYS_MEMTEST_START	0xa0400000	/* memtest works on	*/
#define CONFIG_SYS_MEMTEST_END		0xa0800000	/* 4 ... 8 MB in DRAM	*/

#define CONFIG_SYS_LOAD_ADDR		0xa1000000	/* default load address */

#define CONFIG_SYS_HZ			1000
#define CONFIG_SYS_CPUSPEED		0x207		/* need to look more closely, I think this is Turbo = 2x, L=91Mhz */

#ifdef CONFIG_MMC
#define CONFIG_PXA_MMC
#define CONFIG_CMD_MMC
#define CONFIG_SYS_MMC_BASE		0xF0000000
#endif

/*
 * Physical Memory Map
 */
#define CONFIG_NR_DRAM_BANKS	4	   /* we have 2 banks of DRAM */
#define PHYS_SDRAM_1		0xa0000000 /* SDRAM Bank #1 */
#define PHYS_SDRAM_1_SIZE	0x04000000 /* 64 MB */
#define PHYS_SDRAM_2		0xa4000000 /* SDRAM Bank #2 */
#define PHYS_SDRAM_2_SIZE	0x00000000 /* 0 MB */
#define PHYS_SDRAM_3		0xa8000000 /* SDRAM Bank #3 */
#define PHYS_SDRAM_3_SIZE	0x00000000 /* 0 MB */
#define PHYS_SDRAM_4		0xac000000 /* SDRAM Bank #4 */
#define PHYS_SDRAM_4_SIZE	0x00000000 /* 0 MB */

#define PHYS_FLASH_1		0x00000000 /* Flash Bank #1 */

#define CONFIG_SYS_DRAM_BASE		0xa0000000
#define CONFIG_SYS_DRAM_SIZE		0x04000000

#define CONFIG_SYS_FLASH_BASE		PHYS_FLASH_1

#define CONFIG_SYS_SDRAM_BASE		PHYS_SDRAM_1
#define	CONFIG_SYS_INIT_SP_ADDR		(GENERATED_GBL_DATA_SIZE + PHYS_SDRAM_1)

/*
 * GPIO settings
 */
#define CONFIG_SYS_GPSR0_VAL		0x00018000
#define CONFIG_SYS_GPSR1_VAL		0x00000000
#define CONFIG_SYS_GPSR2_VAL		0x400dc000
#define CONFIG_SYS_GPSR3_VAL		0x00000000
#define CONFIG_SYS_GPCR0_VAL		0x00000000
#define CONFIG_SYS_GPCR1_VAL		0x00000000
#define CONFIG_SYS_GPCR2_VAL		0x00000000
#define CONFIG_SYS_GPCR3_VAL		0x00000000
#define CONFIG_SYS_GPDR0_VAL		0x00018000
#define CONFIG_SYS_GPDR1_VAL		0x00028801
#define CONFIG_SYS_GPDR2_VAL		0x520dc000
#define CONFIG_SYS_GPDR3_VAL		0x0001E000
#define CONFIG_SYS_GAFR0_L_VAL		0x801c0000
#define CONFIG_SYS_GAFR0_U_VAL		0x00000013
#define CONFIG_SYS_GAFR1_L_VAL		0x6990100A
#define CONFIG_SYS_GAFR1_U_VAL		0x00000008
#define CONFIG_SYS_GAFR2_L_VAL		0xA0000000
#define CONFIG_SYS_GAFR2_U_VAL		0x010900F2
#define CONFIG_SYS_GAFR3_L_VAL		0x54000003
#define CONFIG_SYS_GAFR3_U_VAL		0x00002401
#define CONFIG_SYS_GRER0_VAL		0x00000000
#define CONFIG_SYS_GRER1_VAL		0x00000000
#define CONFIG_SYS_GRER2_VAL		0x00000000
#define CONFIG_SYS_GRER3_VAL		0x00000000

#define CONFIG_SYS_GFER1_VAL		0x00000000
#define CONFIG_SYS_GFER3_VAL		0x00000020

#if CONFIG_POLARIS
#define CONFIG_SYS_GFER0_VAL		0x00000001
#define CONFIG_SYS_GFER2_VAL		0x00200000
#else
#define CONFIG_SYS_GFER0_VAL		0x00000000
#define CONFIG_SYS_GFER2_VAL		0x00000000
#endif

#define CONFIG_SYS_PSSR_VAL		0x20	/* CHECK */

/*
 * Clock settings
 */
#define CONFIG_SYS_CKEN		0x01FFFFFF	/* CHECK */
#define CONFIG_SYS_CCCR		0x02000290 /*   520Mhz */

/*
 * Memory settings
 */

#define CONFIG_SYS_MSC0_VAL		0x4df84df0
#define CONFIG_SYS_MSC1_VAL		0x7ff87ff4
#if CONFIG_POLARIS
#define CONFIG_SYS_MSC2_VAL		0xa2697ff8
#else
#define CONFIG_SYS_MSC2_VAL		0xa26936d4
#endif
#define CONFIG_SYS_MDCNFG_VAL		0x880009C9
#define CONFIG_SYS_MDREFR_VAL		0x20ca201e
#define CONFIG_SYS_MDMRS_VAL		0x00220022

#define CONFIG_SYS_FLYCNFG_VAL		0x00000000
#define CONFIG_SYS_SXCNFG_VAL		0x40044004

/*
 * PCMCIA and CF Interfaces
 */
#define CONFIG_SYS_MECR_VAL		0x00000001
#define CONFIG_SYS_MCMEM0_VAL		0x00004204
#define CONFIG_SYS_MCMEM1_VAL		0x00010204
#define CONFIG_SYS_MCATT0_VAL		0x00010504
#define CONFIG_SYS_MCATT1_VAL		0x00010504
#define CONFIG_SYS_MCIO0_VAL		0x00008407
#define CONFIG_SYS_MCIO1_VAL		0x0000c108

#define CONFIG_DRIVER_DM9000		1

#if CONFIG_POLARIS
#define CONFIG_DM9000_BASE		0x0C800000
#else
#define CONFIG_DM9000_BASE		0x08000000
#endif

#define DM9000_IO			CONFIG_DM9000_BASE
#define DM9000_DATA			(CONFIG_DM9000_BASE+0x8004)

#define CONFIG_USB_OHCI_NEW	1
#define CONFIG_SYS_USB_OHCI_BOARD_INIT	1
#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS	3
#define CONFIG_SYS_USB_OHCI_REGS_BASE	0x4C000000
#define CONFIG_SYS_USB_OHCI_SLOT_NAME	"trizepsiv"
#define CONFIG_USB_STORAGE	1
#define CONFIG_SYS_USB_OHCI_CPU_INIT	1

/*
 * FLASH and environment organization
 */

#define CONFIG_SYS_FLASH_CFI
#define CONFIG_FLASH_CFI_DRIVER	1

#define CONFIG_SYS_MONITOR_BASE	0
#define CONFIG_SYS_MONITOR_LEN		0x40000

#define CONFIG_SYS_MAX_FLASH_BANKS	1	/* max number of memory banks		*/
#define CONFIG_SYS_MAX_FLASH_SECT	4 + 255  /* max number of sectors on one chip   */

/* timeout values are in ticks */
#define CONFIG_SYS_FLASH_ERASE_TOUT	(25*CONFIG_SYS_HZ) /* Timeout for Flash Erase */
#define CONFIG_SYS_FLASH_WRITE_TOUT	(25*CONFIG_SYS_HZ) /* Timeout for Flash Write */

/* write flash less slowly */
#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1

/* Unlock to be used with Intel chips */
#define CONFIG_SYS_FLASH_PROTECTION	1

/* Flash environment locations */
#define CONFIG_ENV_IS_IN_FLASH	1
#define CONFIG_ENV_ADDR		(PHYS_FLASH_1 + CONFIG_SYS_MONITOR_LEN) /* Addr of Environment Sector	*/
#define CONFIG_ENV_SIZE		0x40000	/* Total Size of Environment		*/
#define CONFIG_ENV_SECT_SIZE	0x40000	/* Total Size of Environment Sector	*/

/* Address and size of Redundant Environment Sector	*/
#define CONFIG_ENV_ADDR_REDUND	(CONFIG_ENV_ADDR+CONFIG_ENV_SECT_SIZE)
#define CONFIG_ENV_SIZE_REDUND	(CONFIG_ENV_SIZE)

#endif	/* __CONFIG_H */
Commit	Line	Data
5e5803e1 SB	1	/*
	2	* (C) Copyright 2007
	3	* Stefano Babic, DENX Gmbh, sbabic@denx.de
	4	*
	5	* (C) Copyright 2004
	6	* Robert Whaley, Applied Data Systems, Inc. rwhaley@applieddata.net
	7	*
	8	* (C) Copyright 2002
	9	* Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net
	10	*
	11	* (C) Copyright 2002
	12	* Sysgo Real-Time Solutions, GmbH <www.elinos.com>
	13	* Marius Groeger <mgroeger@sysgo.de>
	14	*
	15	* Configuation settings for the LUBBOCK board.
	16	*
	17	* See file CREDITS for list of people who contributed to this
	18	* project.
	19	*
	20	* This program is free software; you can redistribute it and/or
	21	* modify it under the terms of the GNU General Public License as
	22	* published by the Free Software Foundation; either version 2 of
	23	* the License, or (at your option) any later version.
	24	*
	25	* This program is distributed in the hope that it will be useful,
	26	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	27	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	28	* GNU General Public License for more details.
	29	*
	30	* You should have received a copy of the GNU General Public License
	31	* along with this program; if not, write to the Free Software
	32	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	33	* MA 02111-1307 USA
	34	*/
	35
	36	#ifndef __CONFIG_H
	37	#define __CONFIG_H
	38
	39	/*
	40	* High Level Configuration Options
	41	* (easy to change)
	42	*/
abc20aba	43	#define CONFIG_CPU_PXA27X 1 /* This is an PXA27x CPU */
5e5803e1	44
5e5803e1	45	#define CONFIG_MMC 1
9660e442	46	#define CONFIG_BOARD_LATE_INIT
cc72ac66	47	#define CONFIG_SYS_TEXT_BASE 0x0
5e5803e1	48
b3acb6cd	49	/* we will never enable dcache, because we have to setup MMU first */
e47f2db5	50	#define CONFIG_SYS_DCACHE_OFF
b3acb6cd	51
5e5803e1 SB	52	#define RTC
	53
	54	/*
	55	* Size of malloc() pool
	56	*/
6d0f6bcf	57	#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 128*1024)
5e5803e1 SB	58
	59	/*
	60	* Hardware drivers
	61	*/
	62
	63	/*
	64	* select serial console configuration
	65	*/
379be585	66	#define CONFIG_PXA_SERIAL
5e5803e1 SB	67	#define CONFIG_SERIAL_MULTI
	68	#define CONFIG_FFUART 1 /* we use FFUART on Conxs */
	69	#define CONFIG_BTUART 1 /* we use BTUART on Conxs */
	70	#define CONFIG_STUART 1 /* we use STUART on Conxs */
	71
	72	/* allow to overwrite serial and ethaddr */
	73	#define CONFIG_ENV_OVERWRITE
	74
	75	#define CONFIG_BAUDRATE 38400
	76
	77	#define CONFIG_DOS_PARTITION 1
	78
	79	/*
	80	* Command line configuration.
	81	*/
	82	#include <config_cmd_default.h>
	83
5e5803e1 SB	84	#define CONFIG_CMD_FAT
	85	#define CONFIG_CMD_IMLS
	86	#define CONFIG_CMD_PING
	87	#define CONFIG_CMD_USB
	88
	89	/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
	90
	91	#undef CONFIG_SHOW_BOOT_PROGRESS
	92
	93	#define CONFIG_BOOTDELAY 3
	94	#define CONFIG_SERVERIP 192.168.1.99
	95	#define CONFIG_BOOTCOMMAND "run boot_flash"
	96	#define CONFIG_BOOTARGS "console=ttyS0,38400 ramdisk_size=12288"\
	97	" rw root=/dev/ram initrd=0xa0800000,5m"
	98
	99	#define CONFIG_EXTRA_ENV_SETTINGS \
	100	"program_boot_mmc=" \
	101	"mw.b 0xa0010000 0xff 0x20000; " \
	102	"if mmcinit && " \
	103	"fatload mmc 0 0xa0010000 u-boot.bin; " \
	104	"then " \
	105	"protect off 0x0 0x1ffff; " \
	106	"erase 0x0 0x1ffff; " \
	107	"cp.b 0xa0010000 0x0 0x20000; " \
	108	"fi\0" \
	109	"program_uzImage_mmc=" \
	110	"mw.b 0xa0010000 0xff 0x180000; " \
	111	"if mmcinit && " \
	112	"fatload mmc 0 0xa0010000 uzImage; " \
	113	"then " \
	114	"protect off 0x40000 0x1bffff; " \
	115	"erase 0x40000 0x1bffff; " \
	116	"cp.b 0xa0010000 0x40000 0x180000; " \
	117	"fi\0" \
	118	"program_ramdisk_mmc=" \
	119	"mw.b 0xa0010000 0xff 0x500000; " \
	120	"if mmcinit && " \
	121	"fatload mmc 0 0xa0010000 ramdisk.gz; " \
	122	"then " \
	123	"protect off 0x1c0000 0x6bffff; " \
	124	"erase 0x1c0000 0x6bffff; " \
	125	"cp.b 0xa0010000 0x1c0000 0x500000; " \
	126	"fi\0" \
	127	"boot_mmc=" \
	128	"if mmcinit && " \
	129	"fatload mmc 0 0xa0030000 uzImage && " \
	130	"fatload mmc 0 0xa0800000 ramdisk.gz; " \
	131	"then " \
	132	"bootm 0xa0030000; " \
	133	"fi\0" \
	134	"boot_flash=" \
	135	"cp.b 0x1c0000 0xa0800000 0x500000; " \
	136	"bootm 0x40000\0" \
	137
	138	#define CONFIG_SETUP_MEMORY_TAGS 1
	139	#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */
	140	/* #define CONFIG_INITRD_TAG 1 */
	141
1b769881	142	#if defined(CONFIG_CMD_KGDB)
5e5803e1 SB	143	#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
	144	#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
	145	#endif
	146
	147	/*
	148	* Miscellaneous configurable options
	149	*/
6d0f6bcf	150	#define CONFIG_SYS_HUSH_PARSER 1
5e5803e1	151
6d0f6bcf JCPV	152	#define CONFIG_SYS_LONGHELP /* undef to save memory */
	153	#ifdef CONFIG_SYS_HUSH_PARSER
	154	#define CONFIG_SYS_PROMPT "$ " /* Monitor Command Prompt */
5e5803e1	155	#else
6d0f6bcf	156	#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
5e5803e1	157	#endif
6d0f6bcf JCPV	158	#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
	159	#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
	160	#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
	161	#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
	162	#define CONFIG_SYS_DEVICE_NULLDEV 1
5e5803e1	163
6d0f6bcf JCPV	164	#define CONFIG_SYS_MEMTEST_START 0xa0400000 /* memtest works on */
6d0f6bcf JCPV	165	#define CONFIG_SYS_MEMTEST_END 0xa0800000 /* 4 ... 8 MB in DRAM */
5e5803e1	166
6d0f6bcf	167	#define CONFIG_SYS_LOAD_ADDR 0xa1000000 /* default load address */
5e5803e1	168
94a33129	169	#define CONFIG_SYS_HZ 1000
6d0f6bcf	170	#define CONFIG_SYS_CPUSPEED 0x207 /* need to look more closely, I think this is Turbo = 2x, L=91Mhz */
5e5803e1	171
b03d92e5 JCPV	172	#ifdef CONFIG_MMC
	173	#define CONFIG_PXA_MMC
	174	#define CONFIG_CMD_MMC
6d0f6bcf	175	#define CONFIG_SYS_MMC_BASE 0xF0000000
b03d92e5	176	#endif
5e5803e1	177
5e5803e1 SB	178	/*
	179	* Physical Memory Map
	180	*/
	181	#define CONFIG_NR_DRAM_BANKS 4 /* we have 2 banks of DRAM */
	182	#define PHYS_SDRAM_1 0xa0000000 /* SDRAM Bank #1 */
	183	#define PHYS_SDRAM_1_SIZE 0x04000000 /* 64 MB */
	184	#define PHYS_SDRAM_2 0xa4000000 /* SDRAM Bank #2 */
	185	#define PHYS_SDRAM_2_SIZE 0x00000000 /* 0 MB */
	186	#define PHYS_SDRAM_3 0xa8000000 /* SDRAM Bank #3 */
	187	#define PHYS_SDRAM_3_SIZE 0x00000000 /* 0 MB */
	188	#define PHYS_SDRAM_4 0xac000000 /* SDRAM Bank #4 */
	189	#define PHYS_SDRAM_4_SIZE 0x00000000 /* 0 MB */
	190
	191	#define PHYS_FLASH_1 0x00000000 /* Flash Bank #1 */
	192
6d0f6bcf JCPV	193	#define CONFIG_SYS_DRAM_BASE 0xa0000000
6d0f6bcf JCPV	194	#define CONFIG_SYS_DRAM_SIZE 0x04000000
5e5803e1	195
6d0f6bcf	196	#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1
5e5803e1	197
6ef6eb91	198	#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
25ddd1fb	199	#define CONFIG_SYS_INIT_SP_ADDR (GENERATED_GBL_DATA_SIZE + PHYS_SDRAM_1)
6ef6eb91	200
5e5803e1 SB	201	/*
	202	* GPIO settings
	203	*/
6d0f6bcf JCPV	204	#define CONFIG_SYS_GPSR0_VAL 0x00018000
	205	#define CONFIG_SYS_GPSR1_VAL 0x00000000
	206	#define CONFIG_SYS_GPSR2_VAL 0x400dc000
	207	#define CONFIG_SYS_GPSR3_VAL 0x00000000
	208	#define CONFIG_SYS_GPCR0_VAL 0x00000000
	209	#define CONFIG_SYS_GPCR1_VAL 0x00000000
	210	#define CONFIG_SYS_GPCR2_VAL 0x00000000
	211	#define CONFIG_SYS_GPCR3_VAL 0x00000000
	212	#define CONFIG_SYS_GPDR0_VAL 0x00018000
	213	#define CONFIG_SYS_GPDR1_VAL 0x00028801
	214	#define CONFIG_SYS_GPDR2_VAL 0x520dc000
	215	#define CONFIG_SYS_GPDR3_VAL 0x0001E000
	216	#define CONFIG_SYS_GAFR0_L_VAL 0x801c0000
	217	#define CONFIG_SYS_GAFR0_U_VAL 0x00000013
	218	#define CONFIG_SYS_GAFR1_L_VAL 0x6990100A
	219	#define CONFIG_SYS_GAFR1_U_VAL 0x00000008
	220	#define CONFIG_SYS_GAFR2_L_VAL 0xA0000000
	221	#define CONFIG_SYS_GAFR2_U_VAL 0x010900F2
	222	#define CONFIG_SYS_GAFR3_L_VAL 0x54000003
	223	#define CONFIG_SYS_GAFR3_U_VAL 0x00002401
	224	#define CONFIG_SYS_GRER0_VAL 0x00000000
	225	#define CONFIG_SYS_GRER1_VAL 0x00000000
	226	#define CONFIG_SYS_GRER2_VAL 0x00000000
	227	#define CONFIG_SYS_GRER3_VAL 0x00000000
040f8f63	228
6d0f6bcf	229	#define CONFIG_SYS_GFER1_VAL 0x00000000
6d0f6bcf JCPV	230	#define CONFIG_SYS_GFER3_VAL 0x00000020
6d0f6bcf JCPV	231
040f8f63 SB	232	#if CONFIG_POLARIS
	233	#define CONFIG_SYS_GFER0_VAL 0x00000001
	234	#define CONFIG_SYS_GFER2_VAL 0x00200000
	235	#else
	236	#define CONFIG_SYS_GFER0_VAL 0x00000000
	237	#define CONFIG_SYS_GFER2_VAL 0x00000000
	238	#endif
6d0f6bcf JCPV	239
6d0f6bcf JCPV	240	#define CONFIG_SYS_PSSR_VAL 0x20 /* CHECK */
5e5803e1 SB	241
	242	/*
	243	* Clock settings
	244	*/
6d0f6bcf JCPV	245	#define CONFIG_SYS_CKEN 0x01FFFFFF /* CHECK */
6d0f6bcf JCPV	246	#define CONFIG_SYS_CCCR 0x02000290 /* 520Mhz */
5e5803e1 SB	247
	248	/*
	249	* Memory settings
	250	*/
	251
6d0f6bcf JCPV	252	#define CONFIG_SYS_MSC0_VAL 0x4df84df0
6d0f6bcf JCPV	253	#define CONFIG_SYS_MSC1_VAL 0x7ff87ff4
040f8f63 SB	254	#if CONFIG_POLARIS
	255	#define CONFIG_SYS_MSC2_VAL 0xa2697ff8
	256	#else
6d0f6bcf	257	#define CONFIG_SYS_MSC2_VAL 0xa26936d4
040f8f63	258	#endif
6d0f6bcf JCPV	259	#define CONFIG_SYS_MDCNFG_VAL 0x880009C9
	260	#define CONFIG_SYS_MDREFR_VAL 0x20ca201e
	261	#define CONFIG_SYS_MDMRS_VAL 0x00220022
5e5803e1	262
6d0f6bcf JCPV	263	#define CONFIG_SYS_FLYCNFG_VAL 0x00000000
6d0f6bcf JCPV	264	#define CONFIG_SYS_SXCNFG_VAL 0x40044004
5e5803e1 SB	265
	266	/*
	267	* PCMCIA and CF Interfaces
	268	*/
6d0f6bcf JCPV	269	#define CONFIG_SYS_MECR_VAL 0x00000001
	270	#define CONFIG_SYS_MCMEM0_VAL 0x00004204
	271	#define CONFIG_SYS_MCMEM1_VAL 0x00010204
	272	#define CONFIG_SYS_MCATT0_VAL 0x00010504
	273	#define CONFIG_SYS_MCATT1_VAL 0x00010504
	274	#define CONFIG_SYS_MCIO0_VAL 0x00008407
	275	#define CONFIG_SYS_MCIO1_VAL 0x0000c108
5e5803e1	276
5e5803e1	277	#define CONFIG_DRIVER_DM9000 1
040f8f63 SB	278
	279	#if CONFIG_POLARIS
	280	#define CONFIG_DM9000_BASE 0x0C800000
	281	#else
	282	#define CONFIG_DM9000_BASE 0x08000000
	283	#endif
	284
5e5803e1 SB	285	#define DM9000_IO CONFIG_DM9000_BASE
5e5803e1 SB	286	#define DM9000_DATA (CONFIG_DM9000_BASE+0x8004)
5e5803e1 SB	287
5e5803e1 SB	288	#define CONFIG_USB_OHCI_NEW 1
6d0f6bcf JCPV	289	#define CONFIG_SYS_USB_OHCI_BOARD_INIT 1
	290	#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 3
	291	#define CONFIG_SYS_USB_OHCI_REGS_BASE 0x4C000000
	292	#define CONFIG_SYS_USB_OHCI_SLOT_NAME "trizepsiv"
5e5803e1	293	#define CONFIG_USB_STORAGE 1
6d0f6bcf	294	#define CONFIG_SYS_USB_OHCI_CPU_INIT 1
5e5803e1 SB	295
	296	/*
	297	* FLASH and environment organization
	298	*/
	299
6d0f6bcf	300	#define CONFIG_SYS_FLASH_CFI
00b1883a	301	#define CONFIG_FLASH_CFI_DRIVER 1
5e5803e1	302
6d0f6bcf JCPV	303	#define CONFIG_SYS_MONITOR_BASE 0
6d0f6bcf JCPV	304	#define CONFIG_SYS_MONITOR_LEN 0x40000
5e5803e1	305
6d0f6bcf JCPV	306	#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
6d0f6bcf JCPV	307	#define CONFIG_SYS_MAX_FLASH_SECT 4 + 255 /* max number of sectors on one chip */
5e5803e1 SB	308
5e5803e1 SB	309	/* timeout values are in ticks */
6d0f6bcf JCPV	310	#define CONFIG_SYS_FLASH_ERASE_TOUT (25CONFIG_SYS_HZ) / Timeout for Flash Erase */
6d0f6bcf JCPV	311	#define CONFIG_SYS_FLASH_WRITE_TOUT (25CONFIG_SYS_HZ) / Timeout for Flash Write */
5e5803e1 SB	312
5e5803e1 SB	313	/* write flash less slowly */
6d0f6bcf	314	#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1
5e5803e1	315
040f8f63 SB	316	/* Unlock to be used with Intel chips */
	317	#define CONFIG_SYS_FLASH_PROTECTION 1
	318
5e5803e1	319	/* Flash environment locations */
5a1aceb0	320	#define CONFIG_ENV_IS_IN_FLASH 1
6d0f6bcf	321	#define CONFIG_ENV_ADDR (PHYS_FLASH_1 + CONFIG_SYS_MONITOR_LEN) /* Addr of Environment Sector */
0e8d1586 JCPV	322	#define CONFIG_ENV_SIZE 0x40000 /* Total Size of Environment */
0e8d1586 JCPV	323	#define CONFIG_ENV_SECT_SIZE 0x40000 /* Total Size of Environment Sector */
5e5803e1 SB	324
5e5803e1 SB	325	/* Address and size of Redundant Environment Sector */
0e8d1586 JCPV	326	#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR+CONFIG_ENV_SECT_SIZE)
0e8d1586 JCPV	327	#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
5e5803e1 SB	328
5e5803e1 SB	329	#endif /* __CONFIG_H */