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5894ca00 | 1 | /* |
e8a92932 MY |
2 | * Copyright (C) 2012-2015 Panasonic Corporation |
3 | * Copyright (C) 2015-2016 Socionext Inc. | |
4 | * Author: Masahiro Yamada <yamada.masahiro@socionext.com> | |
5894ca00 MY |
5 | * |
6 | * SPDX-License-Identifier: GPL-2.0+ | |
7 | */ | |
8 | ||
a187559e | 9 | /* U-Boot - Common settings for UniPhier Family */ |
5894ca00 MY |
10 | |
11 | #ifndef __CONFIG_UNIPHIER_COMMON_H__ | |
12 | #define __CONFIG_UNIPHIER_COMMON_H__ | |
13 | ||
928f3248 | 14 | #define CONFIG_ARMV7_PSCI_1_0 |
e8a92932 | 15 | |
233e42a9 MY |
16 | #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 |
17 | ||
5894ca00 MY |
18 | /*----------------------------------------------------------------------- |
19 | * MMU and Cache Setting | |
20 | *----------------------------------------------------------------------*/ | |
21 | ||
22 | /* Comment out the following to enable L1 cache */ | |
23 | /* #define CONFIG_SYS_ICACHE_OFF */ | |
24 | /* #define CONFIG_SYS_DCACHE_OFF */ | |
25 | ||
5894ca00 MY |
26 | #define CONFIG_BOARD_LATE_INIT |
27 | ||
28 | #define CONFIG_SYS_MALLOC_LEN (4 * 1024 * 1024) | |
29 | ||
30 | #define CONFIG_TIMESTAMP | |
31 | ||
32 | /* FLASH related */ | |
33 | #define CONFIG_MTD_DEVICE | |
34 | ||
f1d9a9ed MY |
35 | #define CONFIG_SMC911X_32_BIT |
36 | /* dummy: referenced by examples/standalone/smc911x_eeprom.c */ | |
37 | #define CONFIG_SMC911X_BASE 0 | |
38 | ||
39 | #ifdef CONFIG_MICRO_SUPPORT_CARD | |
40 | #define CONFIG_SMC911X | |
41 | #else | |
f4c93a4f MY |
42 | #define CONFIG_SYS_NO_FLASH |
43 | #endif | |
5894ca00 MY |
44 | |
45 | #define CONFIG_FLASH_CFI_DRIVER | |
46 | #define CONFIG_SYS_FLASH_CFI | |
47 | ||
48 | #define CONFIG_SYS_MAX_FLASH_SECT 256 | |
49 | #define CONFIG_SYS_MONITOR_BASE 0 | |
d085ecd6 | 50 | #define CONFIG_SYS_MONITOR_LEN 0x00080000 /* 512KB */ |
5894ca00 MY |
51 | #define CONFIG_SYS_FLASH_BASE 0 |
52 | ||
53 | /* | |
66deb91e | 54 | * flash_toggle does not work for our support card. |
5894ca00 MY |
55 | * We need to use flash_status_poll. |
56 | */ | |
57 | #define CONFIG_SYS_CFI_FLASH_STATUS_POLL | |
58 | ||
59 | #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ | |
60 | ||
9879842c | 61 | #define CONFIG_SYS_MAX_FLASH_BANKS_DETECT 1 |
5894ca00 MY |
62 | |
63 | /* serial console configuration */ | |
64 | #define CONFIG_BAUDRATE 115200 | |
65 | ||
9d0c2ceb | 66 | #if !defined(CONFIG_SPL_BUILD) && !defined(CONFIG_ARM64) |
5894ca00 MY |
67 | #define CONFIG_USE_ARCH_MEMSET |
68 | #define CONFIG_USE_ARCH_MEMCPY | |
69 | #endif | |
70 | ||
71 | #define CONFIG_SYS_LONGHELP /* undef to save memory */ | |
72 | ||
73 | #define CONFIG_CMDLINE_EDITING /* add command line history */ | |
5894ca00 MY |
74 | #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ |
75 | /* Print Buffer Size */ | |
76 | #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) | |
77 | #define CONFIG_SYS_MAXARGS 16 /* max number of command */ | |
78 | /* Boot Argument Buffer Size */ | |
79 | #define CONFIG_SYS_BARGSIZE (CONFIG_SYS_CBSIZE) | |
80 | ||
81 | #define CONFIG_CONS_INDEX 1 | |
82 | ||
aa8a9348 | 83 | /* #define CONFIG_ENV_IS_NOWHERE */ |
5894ca00 | 84 | /* #define CONFIG_ENV_IS_IN_NAND */ |
aa8a9348 MY |
85 | #define CONFIG_ENV_IS_IN_MMC |
86 | #define CONFIG_ENV_OFFSET 0x80000 | |
5894ca00 | 87 | #define CONFIG_ENV_SIZE 0x2000 |
5894ca00 MY |
88 | /* #define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE) */ |
89 | ||
aa8a9348 MY |
90 | #define CONFIG_SYS_MMC_ENV_DEV 0 |
91 | #define CONFIG_SYS_MMC_ENV_PART 1 | |
92 | ||
9d0c2ceb | 93 | #ifdef CONFIG_ARM64 |
50862a51 | 94 | #define CPU_RELEASE_ADDR 0x80000000 |
9d0c2ceb MY |
95 | #define COUNTER_FREQUENCY 50000000 |
96 | #define CONFIG_GICV3 | |
97 | #define GICD_BASE 0x5fe00000 | |
667dbcd0 MY |
98 | #if defined(CONFIG_ARCH_UNIPHIER_LD11) |
99 | #define GICR_BASE 0x5fe40000 | |
100 | #elif defined(CONFIG_ARCH_UNIPHIER_LD20) | |
9d0c2ceb | 101 | #define GICR_BASE 0x5fe80000 |
667dbcd0 | 102 | #endif |
9d0c2ceb | 103 | #else |
5894ca00 MY |
104 | /* Time clock 1MHz */ |
105 | #define CONFIG_SYS_TIMER_RATE 1000000 | |
9d0c2ceb MY |
106 | #endif |
107 | ||
5894ca00 | 108 | |
5894ca00 MY |
109 | #define CONFIG_SYS_MAX_NAND_DEVICE 1 |
110 | #define CONFIG_SYS_NAND_MAX_CHIPS 2 | |
111 | #define CONFIG_SYS_NAND_ONFI_DETECTION | |
112 | ||
113 | #define CONFIG_NAND_DENALI_ECC_SIZE 1024 | |
114 | ||
ea65c980 | 115 | #ifdef CONFIG_ARCH_UNIPHIER_SLD3 |
3365b4eb MY |
116 | #define CONFIG_SYS_NAND_REGS_BASE 0xf8100000 |
117 | #define CONFIG_SYS_NAND_DATA_BASE 0xf8000000 | |
118 | #else | |
5894ca00 MY |
119 | #define CONFIG_SYS_NAND_REGS_BASE 0x68100000 |
120 | #define CONFIG_SYS_NAND_DATA_BASE 0x68000000 | |
3365b4eb | 121 | #endif |
5894ca00 MY |
122 | |
123 | #define CONFIG_SYS_NAND_BASE (CONFIG_SYS_NAND_DATA_BASE + 0x10) | |
124 | ||
125 | #define CONFIG_SYS_NAND_USE_FLASH_BBT | |
126 | #define CONFIG_SYS_NAND_BAD_BLOCK_POS 0 | |
127 | ||
495deb44 | 128 | /* USB */ |
53c45d4e | 129 | #define CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS 4 |
495deb44 MY |
130 | #define CONFIG_FAT_WRITE |
131 | #define CONFIG_DOS_PARTITION | |
132 | ||
4aceb3f8 | 133 | /* SD/MMC */ |
a55d9fee | 134 | #define CONFIG_SUPPORT_EMMC_BOOT |
4aceb3f8 MY |
135 | #define CONFIG_GENERIC_MMC |
136 | ||
5894ca00 MY |
137 | /* memtest works on */ |
138 | #define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE | |
139 | #define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_SDRAM_BASE + 0x01000000) | |
140 | ||
5894ca00 MY |
141 | /* |
142 | * Network Configuration | |
143 | */ | |
5894ca00 MY |
144 | #define CONFIG_SERVERIP 192.168.11.1 |
145 | #define CONFIG_IPADDR 192.168.11.10 | |
146 | #define CONFIG_GATEWAYIP 192.168.11.1 | |
147 | #define CONFIG_NETMASK 255.255.255.0 | |
148 | ||
149 | #define CONFIG_LOADADDR 0x84000000 | |
150 | #define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR | |
5894ca00 MY |
151 | |
152 | #define CONFIG_CMDLINE_EDITING /* add command line history */ | |
153 | ||
154 | #define CONFIG_BOOTCOMMAND "run $bootmode" | |
155 | ||
156 | #define CONFIG_ROOTPATH "/nfs/root/path" | |
157 | #define CONFIG_NFSBOOTCOMMAND \ | |
158 | "setenv bootargs $bootargs root=/dev/nfs rw " \ | |
159 | "nfsroot=$serverip:$rootpath " \ | |
160 | "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off;" \ | |
d566f754 | 161 | "run __nfsboot" |
5894ca00 | 162 | |
421376ae MY |
163 | #ifdef CONFIG_FIT |
164 | #define CONFIG_BOOTFILE "fitImage" | |
165 | #define LINUXBOOT_ENV_SETTINGS \ | |
166 | "fit_addr=0x00100000\0" \ | |
167 | "fit_addr_r=0x84100000\0" \ | |
168 | "fit_size=0x00f00000\0" \ | |
5451b777 | 169 | "norboot=setexpr fit_addr $nor_base + $fit_addr &&" \ |
421376ae | 170 | "bootm $fit_addr\0" \ |
5451b777 | 171 | "nandboot=nand read $fit_addr_r $fit_addr $fit_size &&" \ |
e037db0c | 172 | "bootm $fit_addr_r\0" \ |
5451b777 | 173 | "tftpboot=tftpboot $fit_addr_r $bootfile &&" \ |
d566f754 MY |
174 | "bootm $fit_addr_r\0" \ |
175 | "__nfsboot=run tftpboot\0" | |
421376ae | 176 | #else |
9d0c2ceb | 177 | #ifdef CONFIG_ARM64 |
9d0c2ceb MY |
178 | #define CONFIG_BOOTFILE "Image" |
179 | #define LINUXBOOT_CMD "booti" | |
180 | #define KERNEL_ADDR_R "kernel_addr_r=0x80080000\0" | |
181 | #define KERNEL_SIZE "kernel_size=0x00c00000\0" | |
182 | #define RAMDISK_ADDR "ramdisk_addr=0x00e00000\0" | |
183 | #else | |
89835b35 | 184 | #define CONFIG_BOOTFILE "zImage" |
9d0c2ceb MY |
185 | #define LINUXBOOT_CMD "bootz" |
186 | #define KERNEL_ADDR_R "kernel_addr_r=0x80208000\0" | |
187 | #define KERNEL_SIZE "kernel_size=0x00800000\0" | |
188 | #define RAMDISK_ADDR "ramdisk_addr=0x00a00000\0" | |
189 | #endif | |
421376ae MY |
190 | #define LINUXBOOT_ENV_SETTINGS \ |
191 | "fdt_addr=0x00100000\0" \ | |
192 | "fdt_addr_r=0x84100000\0" \ | |
193 | "fdt_size=0x00008000\0" \ | |
194 | "kernel_addr=0x00200000\0" \ | |
9d0c2ceb MY |
195 | KERNEL_ADDR_R \ |
196 | KERNEL_SIZE \ | |
197 | RAMDISK_ADDR \ | |
421376ae MY |
198 | "ramdisk_addr_r=0x84a00000\0" \ |
199 | "ramdisk_size=0x00600000\0" \ | |
e037db0c | 200 | "ramdisk_file=rootfs.cpio.uboot\0" \ |
cd5d9565 | 201 | "boot_common=setexpr bootm_low $kernel_addr_r '&' fe000000 &&" \ |
9d0c2ceb | 202 | LINUXBOOT_CMD " $kernel_addr_r $ramdisk_addr_r $fdt_addr_r\0" \ |
cd5d9565 | 203 | "norboot=setexpr kernel_addr $nor_base + $kernel_addr &&" \ |
b75e072c MY |
204 | "setexpr kernel_size $kernel_size / 4 &&" \ |
205 | "cp $kernel_addr $kernel_addr_r $kernel_size &&" \ | |
cd5d9565 MY |
206 | "setexpr ramdisk_addr_r $nor_base + $ramdisk_addr &&" \ |
207 | "setexpr fdt_addr_r $nor_base + $fdt_addr &&" \ | |
208 | "run boot_common\0" \ | |
209 | "nandboot=nand read $kernel_addr_r $kernel_addr $kernel_size &&" \ | |
421376ae MY |
210 | "nand read $ramdisk_addr_r $ramdisk_addr $ramdisk_size &&" \ |
211 | "nand read $fdt_addr_r $fdt_addr $fdt_size &&" \ | |
cd5d9565 MY |
212 | "run boot_common\0" \ |
213 | "tftpboot=tftpboot $kernel_addr_r $bootfile &&" \ | |
e037db0c MY |
214 | "tftpboot $ramdisk_addr_r $ramdisk_file &&" \ |
215 | "tftpboot $fdt_addr_r $fdt_file &&" \ | |
d566f754 MY |
216 | "run boot_common\0" \ |
217 | "__nfsboot=tftpboot $kernel_addr_r $bootfile &&" \ | |
d566f754 MY |
218 | "tftpboot $fdt_addr_r $fdt_file &&" \ |
219 | "setenv ramdisk_addr_r - &&" \ | |
cd5d9565 | 220 | "run boot_common\0" |
421376ae MY |
221 | #endif |
222 | ||
223 | #define CONFIG_EXTRA_ENV_SETTINGS \ | |
224 | "netdev=eth0\0" \ | |
225 | "verify=n\0" \ | |
90a6e929 | 226 | "nor_base=0x42000000\0" \ |
61a4f5bd MY |
227 | "sramupdate=setexpr tmp_addr $nor_base + 0x50000 &&" \ |
228 | "tftpboot $tmp_addr u-boot-spl.bin &&" \ | |
229 | "setexpr tmp_addr $nor_base + 0x60000 &&" \ | |
230 | "tftpboot $tmp_addr u-boot.bin\0" \ | |
c231c436 MY |
231 | "emmcupdate=mmcsetn &&" \ |
232 | "mmc partconf $mmc_first_dev 0 1 1 &&" \ | |
c231c436 MY |
233 | "tftpboot u-boot-spl.bin &&" \ |
234 | "mmc write $loadaddr 0 80 &&" \ | |
d085ecd6 | 235 | "tftpboot u-boot.bin &&" \ |
c231c436 | 236 | "mmc write $loadaddr 80 780\0" \ |
421376ae | 237 | "nandupdate=nand erase 0 0x00100000 &&" \ |
3cb9abc9 | 238 | "tftpboot u-boot-spl.bin &&" \ |
421376ae | 239 | "nand write $loadaddr 0 0x00010000 &&" \ |
d085ecd6 | 240 | "tftpboot u-boot.bin &&" \ |
421376ae | 241 | "nand write $loadaddr 0x00010000 0x000f0000\0" \ |
421376ae | 242 | LINUXBOOT_ENV_SETTINGS |
5894ca00 | 243 | |
17bd4a21 MY |
244 | #define CONFIG_SYS_BOOTMAPSZ 0x20000000 |
245 | ||
cf88affa | 246 | #define CONFIG_SYS_SDRAM_BASE 0x80000000 |
5894ca00 | 247 | #define CONFIG_NR_DRAM_BANKS 2 |
23869698 MY |
248 | /* for LD20; the last 64 byte is used for dynamic DDR PHY training */ |
249 | #define CONFIG_SYS_MEM_TOP_HIDE 64 | |
5894ca00 | 250 | |
9d0c2ceb MY |
251 | #if defined(CONFIG_ARM64) |
252 | #define CONFIG_SPL_TEXT_BASE 0x30000000 | |
253 | #elif defined(CONFIG_ARCH_UNIPHIER_SLD3) || \ | |
254 | defined(CONFIG_ARCH_UNIPHIER_LD4) || \ | |
ea65c980 | 255 | defined(CONFIG_ARCH_UNIPHIER_SLD8) |
f5d0b9b2 | 256 | #define CONFIG_SPL_TEXT_BASE 0x00040000 |
323d1f9d | 257 | #else |
f5d0b9b2 MY |
258 | #define CONFIG_SPL_TEXT_BASE 0x00100000 |
259 | #endif | |
260 | ||
667dbcd0 MY |
261 | #if defined(CONFIG_ARCH_UNIPHIER_LD11) |
262 | #define CONFIG_SPL_STACK (0x30014c00) | |
263 | #elif defined(CONFIG_ARCH_UNIPHIER_LD20) | |
9d0c2ceb MY |
264 | #define CONFIG_SPL_STACK (0x3001c000) |
265 | #else | |
755c7d9a | 266 | #define CONFIG_SPL_STACK (0x00100000) |
9d0c2ceb | 267 | #endif |
8cddc279 | 268 | #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_TEXT_BASE) |
5894ca00 | 269 | |
a286039b MY |
270 | #define CONFIG_PANIC_HANG |
271 | ||
5894ca00 | 272 | #define CONFIG_SPL_FRAMEWORK |
adb3928f MY |
273 | #ifdef CONFIG_ARM64 |
274 | #define CONFIG_SPL_BOARD_LOAD_IMAGE | |
9d0c2ceb | 275 | #endif |
5894ca00 | 276 | |
5894ca00 MY |
277 | #define CONFIG_SPL_BOARD_INIT |
278 | ||
279 | #define CONFIG_SYS_NAND_U_BOOT_OFFS 0x10000 | |
cbbc2d80 | 280 | |
d085ecd6 MY |
281 | /* subtract sizeof(struct image_header) */ |
282 | #define CONFIG_SYS_UBOOT_BASE (0x60000 - 0x40) | |
5894ca00 | 283 | |
d085ecd6 | 284 | #define CONFIG_SPL_TARGET "u-boot-with-spl.bin" |
6a3cffe8 | 285 | #define CONFIG_SPL_MAX_FOOTPRINT 0x10000 |
86c3345a | 286 | #define CONFIG_SPL_MAX_SIZE 0x10000 |
667dbcd0 MY |
287 | #if defined(CONFIG_ARCH_UNIPHIER_LD11) |
288 | #define CONFIG_SPL_BSS_START_ADDR 0x30012000 | |
289 | #elif defined(CONFIG_ARCH_UNIPHIER_LD20) | |
9d0c2ceb | 290 | #define CONFIG_SPL_BSS_START_ADDR 0x30016000 |
667dbcd0 | 291 | #endif |
9d0c2ceb | 292 | #define CONFIG_SPL_BSS_MAX_SIZE 0x2000 |
6a3cffe8 | 293 | |
5894ca00 | 294 | #endif /* __CONFIG_UNIPHIER_COMMON_H__ */ |