[people/ms/u-boot.git] / include / configs / uniphier.h

/*
 * Copyright (C) 2012-2015 Masahiro Yamada <yamada.masahiro@socionext.com>
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

/* U-Boot - Common settings for UniPhier Family */

#ifndef __CONFIG_UNIPHIER_COMMON_H__
#define __CONFIG_UNIPHIER_COMMON_H__

#define CONFIG_I2C_EEPROM
#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS  10

#define CONFIG_SMC911X

/* dummy: referenced by examples/standalone/smc911x_eeprom.c */
#define CONFIG_SMC911X_BASE	0
#define CONFIG_SMC911X_32_BIT

/*-----------------------------------------------------------------------
 * MMU and Cache Setting
 *----------------------------------------------------------------------*/

/* Comment out the following to enable L1 cache */
/* #define CONFIG_SYS_ICACHE_OFF */
/* #define CONFIG_SYS_DCACHE_OFF */

#define CONFIG_SYS_CACHELINE_SIZE	32

/* Comment out the following to disable L2 cache */
#define CONFIG_UNIPHIER_L2CACHE_ON

#define CONFIG_DISPLAY_CPUINFO
#define CONFIG_DISPLAY_BOARDINFO
#define CONFIG_MISC_INIT_F
#define CONFIG_BOARD_EARLY_INIT_F
#define CONFIG_BOARD_EARLY_INIT_R
#define CONFIG_BOARD_LATE_INIT

#define CONFIG_SYS_MALLOC_LEN		(4 * 1024 * 1024)

#define CONFIG_TIMESTAMP

/* FLASH related */
#define CONFIG_MTD_DEVICE

/*
 * uncomment the following to disable FLASH related code.
 */
/* #define CONFIG_SYS_NO_FLASH */

#define CONFIG_FLASH_CFI_DRIVER
#define CONFIG_SYS_FLASH_CFI

#define CONFIG_SYS_MAX_FLASH_SECT	256
#define CONFIG_SYS_MONITOR_BASE		0
#define CONFIG_SYS_MONITOR_LEN		0x00080000	/* 512KB */
#define CONFIG_SYS_FLASH_BASE		0

/*
 * flash_toggle does not work for out supoort card.
 * We need to use flash_status_poll.
 */
#define CONFIG_SYS_CFI_FLASH_STATUS_POLL

#define CONFIG_FLASH_SHOW_PROGRESS	45 /* count down from 45/5: 9..1 */

#define CONFIG_SYS_MAX_FLASH_BANKS_DETECT 1

/* serial console configuration */
#define CONFIG_BAUDRATE			115200

#if !defined(CONFIG_SPL_BUILD) && !defined(CONFIG_ARM64)
#define CONFIG_USE_ARCH_MEMSET
#define CONFIG_USE_ARCH_MEMCPY
#endif

#define CONFIG_SYS_LONGHELP		/* undef to save memory */

#define CONFIG_CMDLINE_EDITING		/* add command line history	*/
#define CONFIG_SYS_CBSIZE		1024	/* Console I/O Buffer Size */
/* Print Buffer Size */
#define CONFIG_SYS_PBSIZE		(CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
#define CONFIG_SYS_MAXARGS		16	/* max number of command */
/* Boot Argument Buffer Size */
#define CONFIG_SYS_BARGSIZE		(CONFIG_SYS_CBSIZE)

#define CONFIG_CONS_INDEX		1

/* #define CONFIG_ENV_IS_NOWHERE */
/* #define CONFIG_ENV_IS_IN_NAND */
#define CONFIG_ENV_IS_IN_MMC
#define CONFIG_ENV_OFFSET			0x80000
#define CONFIG_ENV_SIZE				0x2000
/* #define CONFIG_ENV_OFFSET_REDUND	(CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE) */

#define CONFIG_SYS_MMC_ENV_DEV		0
#define CONFIG_SYS_MMC_ENV_PART		1

#ifdef CONFIG_ARM64
#define CONFIG_ARMV8_MULTIENTRY
#define CPU_RELEASE_ADDR			0x80000100
#define COUNTER_FREQUENCY			50000000
#define CONFIG_GICV3
#define GICD_BASE				0x5fe00000
#define GICR_BASE				0x5fe80000
#else
/* Time clock 1MHz */
#define CONFIG_SYS_TIMER_RATE			1000000
#endif


#define CONFIG_SYS_MAX_NAND_DEVICE			1
#define CONFIG_SYS_NAND_MAX_CHIPS			2
#define CONFIG_SYS_NAND_ONFI_DETECTION

#define CONFIG_NAND_DENALI_ECC_SIZE			1024

#ifdef CONFIG_ARCH_UNIPHIER_SLD3
#define CONFIG_SYS_NAND_REGS_BASE			0xf8100000
#define CONFIG_SYS_NAND_DATA_BASE			0xf8000000
#else
#define CONFIG_SYS_NAND_REGS_BASE			0x68100000
#define CONFIG_SYS_NAND_DATA_BASE			0x68000000
#endif

#define CONFIG_SYS_NAND_BASE		(CONFIG_SYS_NAND_DATA_BASE + 0x10)

#define CONFIG_SYS_NAND_USE_FLASH_BBT
#define CONFIG_SYS_NAND_BAD_BLOCK_POS			0

/* USB */
#define CONFIG_USB_MAX_CONTROLLER_COUNT		2
#define CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS	4
#define CONFIG_FAT_WRITE
#define CONFIG_DOS_PARTITION

/* SD/MMC */
#define CONFIG_SUPPORT_EMMC_BOOT
#define CONFIG_GENERIC_MMC

/* memtest works on */
#define CONFIG_SYS_MEMTEST_START	CONFIG_SYS_SDRAM_BASE
#define CONFIG_SYS_MEMTEST_END		(CONFIG_SYS_SDRAM_BASE + 0x01000000)

#define CONFIG_BOOTDELAY			3
#define CONFIG_ZERO_BOOTDELAY_CHECK	/* check for keypress on bootdelay==0 */

/*
 * Network Configuration
 */
#define CONFIG_SERVERIP			192.168.11.1
#define CONFIG_IPADDR			192.168.11.10
#define CONFIG_GATEWAYIP		192.168.11.1
#define CONFIG_NETMASK			255.255.255.0

#define CONFIG_LOADADDR			0x84000000
#define CONFIG_SYS_LOAD_ADDR		CONFIG_LOADADDR

#define CONFIG_CMDLINE_EDITING		/* add command line history	*/

#define CONFIG_BOOTCOMMAND		"run $bootmode"

#define CONFIG_ROOTPATH			"/nfs/root/path"
#define CONFIG_NFSBOOTCOMMAND						\
	"setenv bootargs $bootargs root=/dev/nfs rw "			\
	"nfsroot=$serverip:$rootpath "					\
	"ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off;" \
		"run __nfsboot"

#ifdef CONFIG_FIT
#define CONFIG_BOOTFILE			"fitImage"
#define LINUXBOOT_ENV_SETTINGS \
	"fit_addr=0x00100000\0" \
	"fit_addr_r=0x84100000\0" \
	"fit_size=0x00f00000\0" \
	"norboot=setexpr fit_addr $nor_base + $fit_addr &&" \
		"bootm $fit_addr\0" \
	"nandboot=nand read $fit_addr_r $fit_addr $fit_size &&" \
		"bootm $fit_addr_r\0" \
	"tftpboot=tftpboot $fit_addr_r $bootfile &&" \
		"bootm $fit_addr_r\0" \
	"__nfsboot=run tftpboot\0"
#else
#ifdef CONFIG_ARM64
#define CONFIG_CMD_BOOTI
#define CONFIG_BOOTFILE			"Image"
#define LINUXBOOT_CMD			"booti"
#define KERNEL_ADDR_R			"kernel_addr_r=0x80080000\0"
#define KERNEL_SIZE			"kernel_size=0x00c00000\0"
#define RAMDISK_ADDR			"ramdisk_addr=0x00e00000\0"
#else
#define CONFIG_BOOTFILE			"zImage"
#define LINUXBOOT_CMD			"bootz"
#define KERNEL_ADDR_R			"kernel_addr_r=0x80208000\0"
#define KERNEL_SIZE			"kernel_size=0x00800000\0"
#define RAMDISK_ADDR			"ramdisk_addr=0x00a00000\0"
#endif
#define LINUXBOOT_ENV_SETTINGS \
	"fdt_addr=0x00100000\0" \
	"fdt_addr_r=0x84100000\0" \
	"fdt_size=0x00008000\0" \
	"kernel_addr=0x00200000\0" \
	KERNEL_ADDR_R \
	KERNEL_SIZE \
	RAMDISK_ADDR \
	"ramdisk_addr_r=0x84a00000\0" \
	"ramdisk_size=0x00600000\0" \
	"ramdisk_file=rootfs.cpio.uboot\0" \
	"boot_common=setexpr bootm_low $kernel_addr_r '&' fe000000 &&" \
		LINUXBOOT_CMD " $kernel_addr_r $ramdisk_addr_r $fdt_addr_r\0" \
	"norboot=setexpr kernel_addr $nor_base + $kernel_addr &&" \
		"setexpr kernel_size $kernel_size / 4 &&" \
		"cp $kernel_addr $kernel_addr_r $kernel_size &&" \
		"setexpr ramdisk_addr_r $nor_base + $ramdisk_addr &&" \
		"setexpr fdt_addr_r $nor_base + $fdt_addr &&" \
		"run boot_common\0" \
	"nandboot=nand read $kernel_addr_r $kernel_addr $kernel_size &&" \
		"nand read $ramdisk_addr_r $ramdisk_addr $ramdisk_size &&" \
		"nand read $fdt_addr_r $fdt_addr $fdt_size &&" \
		"run boot_common\0" \
	"tftpboot=tftpboot $kernel_addr_r $bootfile &&" \
		"tftpboot $ramdisk_addr_r $ramdisk_file &&" \
		"tftpboot $fdt_addr_r $fdt_file &&" \
		"run boot_common\0" \
	"__nfsboot=tftpboot $kernel_addr_r $bootfile &&" \
		"tftpboot $fdt_addr_r $fdt_file &&" \
		"tftpboot $fdt_addr_r $fdt_file &&" \
		"setenv ramdisk_addr_r - &&" \
		"run boot_common\0"
#endif

#define	CONFIG_EXTRA_ENV_SETTINGS				\
	"netdev=eth0\0"						\
	"verify=n\0"						\
	"nor_base=0x42000000\0"					\
	"sramupdate=setexpr tmp_addr $nor_base + 0x50000 &&"	\
		"tftpboot $tmp_addr u-boot-spl.bin &&"		\
		"setexpr tmp_addr $nor_base + 0x60000 &&"	\
		"tftpboot $tmp_addr u-boot.bin\0"		\
	"emmcupdate=mmcsetn &&"					\
		"mmc partconf $mmc_first_dev 0 1 1 &&"		\
		"mmc erase 0 800 &&"				\
		"tftpboot u-boot-spl.bin &&"			\
		"mmc write $loadaddr 0 80 &&"			\
		"tftpboot u-boot.bin &&"			\
		"mmc write $loadaddr 80 780\0"			\
	"nandupdate=nand erase 0 0x00100000 &&"			\
		"tftpboot u-boot-spl.bin &&"			\
		"nand write $loadaddr 0 0x00010000 &&"		\
		"tftpboot u-boot.bin &&"			\
		"nand write $loadaddr 0x00010000 0x000f0000\0"	\
	LINUXBOOT_ENV_SETTINGS

#define CONFIG_SYS_BOOTMAPSZ			0x20000000

#define CONFIG_SYS_SDRAM_BASE		0x80000000
#define CONFIG_NR_DRAM_BANKS		2
/* for LD20; the last 64 byte is used for dynamic DDR PHY training */
#define CONFIG_SYS_MEM_TOP_HIDE		64

#if defined(CONFIG_ARM64)
#define CONFIG_SPL_TEXT_BASE		0x30000000
#elif defined(CONFIG_ARCH_UNIPHIER_SLD3) || \
	defined(CONFIG_ARCH_UNIPHIER_LD4) || \
	defined(CONFIG_ARCH_UNIPHIER_SLD8)
#define CONFIG_SPL_TEXT_BASE		0x00040000
#else
#define CONFIG_SPL_TEXT_BASE		0x00100000
#endif

#if defined(CONFIG_ARCH_UNIPHIER_LD20)
#define CONFIG_SPL_STACK		(0x3001c000)
#else
#define CONFIG_SPL_STACK		(0x00100000)
#endif
#define CONFIG_SYS_INIT_SP_ADDR		(CONFIG_SYS_TEXT_BASE)

#define CONFIG_PANIC_HANG

#define CONFIG_SPL_FRAMEWORK
#define CONFIG_SPL_SERIAL_SUPPORT
#define CONFIG_SPL_NOR_SUPPORT
#ifndef CONFIG_ARM64
#define CONFIG_SPL_NAND_SUPPORT
#define CONFIG_SPL_MMC_SUPPORT
#endif

#define CONFIG_SPL_LIBCOMMON_SUPPORT	/* for mem_malloc_init */
#define CONFIG_SPL_LIBGENERIC_SUPPORT

#define CONFIG_SPL_BOARD_INIT

#define CONFIG_SYS_NAND_U_BOOT_OFFS		0x10000

/* subtract sizeof(struct image_header) */
#define CONFIG_SYS_UBOOT_BASE			(0x60000 - 0x40)
#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR	0x80

#define CONFIG_SPL_TARGET			"u-boot-with-spl.bin"
#define CONFIG_SPL_MAX_FOOTPRINT		0x10000
#define CONFIG_SPL_MAX_SIZE			0x10000
#define CONFIG_SPL_BSS_START_ADDR		0x30016000
#define CONFIG_SPL_BSS_MAX_SIZE			0x2000

#endif /* __CONFIG_UNIPHIER_COMMON_H__ */
Commit	Line	Data
5894ca00	1	/*
f8f35944	2	* Copyright (C) 2012-2015 Masahiro Yamada <yamada.masahiro@socionext.com>
5894ca00 MY	3	*
	4	* SPDX-License-Identifier: GPL-2.0+
	5	*/
	6
a187559e	7	/* U-Boot - Common settings for UniPhier Family */
5894ca00 MY	8
	9	#ifndef __CONFIG_UNIPHIER_COMMON_H__
	10	#define __CONFIG_UNIPHIER_COMMON_H__
	11
233e42a9 MY	12	#define CONFIG_I2C_EEPROM
	13	#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10
	14
f5d0b9b2 MY	15	#define CONFIG_SMC911X
f5d0b9b2 MY	16
d7728aa4 MY	17	/* dummy: referenced by examples/standalone/smc911x_eeprom.c */
d7728aa4 MY	18	#define CONFIG_SMC911X_BASE 0
5894ca00 MY	19	#define CONFIG_SMC911X_32_BIT
5894ca00 MY	20
5894ca00 MY	21	/*-----------------------------------------------------------------------
	22	* MMU and Cache Setting
	23	----------------------------------------------------------------------/
	24
	25	/* Comment out the following to enable L1 cache */
	26	/* #define CONFIG_SYS_ICACHE_OFF */
	27	/* #define CONFIG_SYS_DCACHE_OFF */
	28
53c45d4e MY	29	#define CONFIG_SYS_CACHELINE_SIZE 32
53c45d4e MY	30
013dcc78	31	/* Comment out the following to disable L2 cache */
5894ca00 MY	32	#define CONFIG_UNIPHIER_L2CACHE_ON
	33
	34	#define CONFIG_DISPLAY_CPUINFO
	35	#define CONFIG_DISPLAY_BOARDINFO
08fda258	36	#define CONFIG_MISC_INIT_F
84ccd791	37	#define CONFIG_BOARD_EARLY_INIT_F
7a3620b2	38	#define CONFIG_BOARD_EARLY_INIT_R
5894ca00 MY	39	#define CONFIG_BOARD_LATE_INIT
	40
	41	#define CONFIG_SYS_MALLOC_LEN (4 * 1024 * 1024)
	42
	43	#define CONFIG_TIMESTAMP
	44
	45	/* FLASH related */
	46	#define CONFIG_MTD_DEVICE
	47
	48	/*
	49	* uncomment the following to disable FLASH related code.
	50	*/
	51	/* #define CONFIG_SYS_NO_FLASH */
	52
	53	#define CONFIG_FLASH_CFI_DRIVER
	54	#define CONFIG_SYS_FLASH_CFI
	55
	56	#define CONFIG_SYS_MAX_FLASH_SECT 256
	57	#define CONFIG_SYS_MONITOR_BASE 0
d085ecd6	58	#define CONFIG_SYS_MONITOR_LEN 0x00080000 /* 512KB */
5894ca00 MY	59	#define CONFIG_SYS_FLASH_BASE 0
	60
	61	/*
	62	* flash_toggle does not work for out supoort card.
	63	* We need to use flash_status_poll.
	64	*/
	65	#define CONFIG_SYS_CFI_FLASH_STATUS_POLL
	66
	67	#define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
	68
9879842c	69	#define CONFIG_SYS_MAX_FLASH_BANKS_DETECT 1
5894ca00 MY	70
	71	/* serial console configuration */
	72	#define CONFIG_BAUDRATE 115200
	73
9d0c2ceb	74	#if !defined(CONFIG_SPL_BUILD) && !defined(CONFIG_ARM64)
5894ca00 MY	75	#define CONFIG_USE_ARCH_MEMSET
	76	#define CONFIG_USE_ARCH_MEMCPY
	77	#endif
	78
	79	#define CONFIG_SYS_LONGHELP /* undef to save memory */
	80
	81	#define CONFIG_CMDLINE_EDITING /* add command line history */
5894ca00 MY	82	#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
	83	/* Print Buffer Size */
	84	#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
	85	#define CONFIG_SYS_MAXARGS 16 /* max number of command */
	86	/* Boot Argument Buffer Size */
	87	#define CONFIG_SYS_BARGSIZE (CONFIG_SYS_CBSIZE)
	88
	89	#define CONFIG_CONS_INDEX 1
	90
aa8a9348	91	/* #define CONFIG_ENV_IS_NOWHERE */
5894ca00	92	/* #define CONFIG_ENV_IS_IN_NAND */
aa8a9348 MY	93	#define CONFIG_ENV_IS_IN_MMC
aa8a9348 MY	94	#define CONFIG_ENV_OFFSET 0x80000
5894ca00	95	#define CONFIG_ENV_SIZE 0x2000
5894ca00 MY	96	/* #define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE) */
5894ca00 MY	97
aa8a9348 MY	98	#define CONFIG_SYS_MMC_ENV_DEV 0
	99	#define CONFIG_SYS_MMC_ENV_PART 1
	100
9d0c2ceb MY	101	#ifdef CONFIG_ARM64
	102	#define CONFIG_ARMV8_MULTIENTRY
	103	#define CPU_RELEASE_ADDR 0x80000100
	104	#define COUNTER_FREQUENCY 50000000
	105	#define CONFIG_GICV3
	106	#define GICD_BASE 0x5fe00000
	107	#define GICR_BASE 0x5fe80000
	108	#else
5894ca00 MY	109	/* Time clock 1MHz */
5894ca00 MY	110	#define CONFIG_SYS_TIMER_RATE 1000000
9d0c2ceb MY	111	#endif
9d0c2ceb MY	112
5894ca00	113
5894ca00 MY	114	#define CONFIG_SYS_MAX_NAND_DEVICE 1
	115	#define CONFIG_SYS_NAND_MAX_CHIPS 2
	116	#define CONFIG_SYS_NAND_ONFI_DETECTION
	117
	118	#define CONFIG_NAND_DENALI_ECC_SIZE 1024
	119
ea65c980	120	#ifdef CONFIG_ARCH_UNIPHIER_SLD3
3365b4eb MY	121	#define CONFIG_SYS_NAND_REGS_BASE 0xf8100000
	122	#define CONFIG_SYS_NAND_DATA_BASE 0xf8000000
	123	#else
5894ca00 MY	124	#define CONFIG_SYS_NAND_REGS_BASE 0x68100000
5894ca00 MY	125	#define CONFIG_SYS_NAND_DATA_BASE 0x68000000
3365b4eb	126	#endif
5894ca00 MY	127
	128	#define CONFIG_SYS_NAND_BASE (CONFIG_SYS_NAND_DATA_BASE + 0x10)
	129
	130	#define CONFIG_SYS_NAND_USE_FLASH_BBT
	131	#define CONFIG_SYS_NAND_BAD_BLOCK_POS 0
	132
495deb44	133	/* USB */
495deb44	134	#define CONFIG_USB_MAX_CONTROLLER_COUNT 2
53c45d4e	135	#define CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS 4
495deb44 MY	136	#define CONFIG_FAT_WRITE
	137	#define CONFIG_DOS_PARTITION
	138
4aceb3f8	139	/* SD/MMC */
a55d9fee	140	#define CONFIG_SUPPORT_EMMC_BOOT
4aceb3f8 MY	141	#define CONFIG_GENERIC_MMC
4aceb3f8 MY	142
5894ca00 MY	143	/* memtest works on */
	144	#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE
	145	#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_SDRAM_BASE + 0x01000000)
	146
	147	#define CONFIG_BOOTDELAY 3
	148	#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */
5894ca00 MY	149
	150	/*
	151	* Network Configuration
	152	*/
5894ca00 MY	153	#define CONFIG_SERVERIP 192.168.11.1
	154	#define CONFIG_IPADDR 192.168.11.10
	155	#define CONFIG_GATEWAYIP 192.168.11.1
	156	#define CONFIG_NETMASK 255.255.255.0
	157
	158	#define CONFIG_LOADADDR 0x84000000
	159	#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
5894ca00 MY	160
	161	#define CONFIG_CMDLINE_EDITING /* add command line history */
	162
	163	#define CONFIG_BOOTCOMMAND "run $bootmode"
	164
	165	#define CONFIG_ROOTPATH "/nfs/root/path"
	166	#define CONFIG_NFSBOOTCOMMAND \
	167	"setenv bootargs $bootargs root=/dev/nfs rw " \
	168	"nfsroot=$serverip:$rootpath " \
	169	"ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off;" \
d566f754	170	"run __nfsboot"
5894ca00	171
421376ae MY	172	#ifdef CONFIG_FIT
	173	#define CONFIG_BOOTFILE "fitImage"
	174	#define LINUXBOOT_ENV_SETTINGS \
	175	"fit_addr=0x00100000\0" \
	176	"fit_addr_r=0x84100000\0" \
	177	"fit_size=0x00f00000\0" \
5451b777	178	"norboot=setexpr fit_addr $nor_base + $fit_addr &&" \
421376ae	179	"bootm $fit_addr\0" \
5451b777	180	"nandboot=nand read $fit_addr_r $fit_addr $fit_size &&" \
e037db0c	181	"bootm $fit_addr_r\0" \
5451b777	182	"tftpboot=tftpboot $fit_addr_r $bootfile &&" \
d566f754 MY	183	"bootm $fit_addr_r\0" \
d566f754 MY	184	"__nfsboot=run tftpboot\0"
421376ae	185	#else
9d0c2ceb MY	186	#ifdef CONFIG_ARM64
	187	#define CONFIG_CMD_BOOTI
	188	#define CONFIG_BOOTFILE "Image"
	189	#define LINUXBOOT_CMD "booti"
	190	#define KERNEL_ADDR_R "kernel_addr_r=0x80080000\0"
	191	#define KERNEL_SIZE "kernel_size=0x00c00000\0"
	192	#define RAMDISK_ADDR "ramdisk_addr=0x00e00000\0"
	193	#else
89835b35	194	#define CONFIG_BOOTFILE "zImage"
9d0c2ceb MY	195	#define LINUXBOOT_CMD "bootz"
	196	#define KERNEL_ADDR_R "kernel_addr_r=0x80208000\0"
	197	#define KERNEL_SIZE "kernel_size=0x00800000\0"
	198	#define RAMDISK_ADDR "ramdisk_addr=0x00a00000\0"
	199	#endif
421376ae MY	200	#define LINUXBOOT_ENV_SETTINGS \
	201	"fdt_addr=0x00100000\0" \
	202	"fdt_addr_r=0x84100000\0" \
	203	"fdt_size=0x00008000\0" \
	204	"kernel_addr=0x00200000\0" \
9d0c2ceb MY	205	KERNEL_ADDR_R \
	206	KERNEL_SIZE \
	207	RAMDISK_ADDR \
421376ae MY	208	"ramdisk_addr_r=0x84a00000\0" \
421376ae MY	209	"ramdisk_size=0x00600000\0" \
e037db0c	210	"ramdisk_file=rootfs.cpio.uboot\0" \
cd5d9565	211	"boot_common=setexpr bootm_low $kernel_addr_r '&' fe000000 &&" \
9d0c2ceb	212	LINUXBOOT_CMD " $kernel_addr_r $ramdisk_addr_r $fdt_addr_r\0" \
cd5d9565	213	"norboot=setexpr kernel_addr $nor_base + $kernel_addr &&" \
b75e072c MY	214	"setexpr kernel_size $kernel_size / 4 &&" \
b75e072c MY	215	"cp $kernel_addr $kernel_addr_r $kernel_size &&" \
cd5d9565 MY	216	"setexpr ramdisk_addr_r $nor_base + $ramdisk_addr &&" \
	217	"setexpr fdt_addr_r $nor_base + $fdt_addr &&" \
	218	"run boot_common\0" \
	219	"nandboot=nand read $kernel_addr_r $kernel_addr $kernel_size &&" \
421376ae MY	220	"nand read $ramdisk_addr_r $ramdisk_addr $ramdisk_size &&" \
421376ae MY	221	"nand read $fdt_addr_r $fdt_addr $fdt_size &&" \
cd5d9565 MY	222	"run boot_common\0" \
cd5d9565 MY	223	"tftpboot=tftpboot $kernel_addr_r $bootfile &&" \
e037db0c MY	224	"tftpboot $ramdisk_addr_r $ramdisk_file &&" \
e037db0c MY	225	"tftpboot $fdt_addr_r $fdt_file &&" \
d566f754 MY	226	"run boot_common\0" \
	227	"__nfsboot=tftpboot $kernel_addr_r $bootfile &&" \
	228	"tftpboot $fdt_addr_r $fdt_file &&" \
	229	"tftpboot $fdt_addr_r $fdt_file &&" \
	230	"setenv ramdisk_addr_r - &&" \
cd5d9565	231	"run boot_common\0"
421376ae MY	232	#endif
	233
	234	#define CONFIG_EXTRA_ENV_SETTINGS \
	235	"netdev=eth0\0" \
	236	"verify=n\0" \
90a6e929	237	"nor_base=0x42000000\0" \
61a4f5bd MY	238	"sramupdate=setexpr tmp_addr $nor_base + 0x50000 &&" \
	239	"tftpboot $tmp_addr u-boot-spl.bin &&" \
	240	"setexpr tmp_addr $nor_base + 0x60000 &&" \
	241	"tftpboot $tmp_addr u-boot.bin\0" \
c231c436 MY	242	"emmcupdate=mmcsetn &&" \
	243	"mmc partconf $mmc_first_dev 0 1 1 &&" \
	244	"mmc erase 0 800 &&" \
	245	"tftpboot u-boot-spl.bin &&" \
	246	"mmc write $loadaddr 0 80 &&" \
d085ecd6	247	"tftpboot u-boot.bin &&" \
c231c436	248	"mmc write $loadaddr 80 780\0" \
421376ae	249	"nandupdate=nand erase 0 0x00100000 &&" \
3cb9abc9	250	"tftpboot u-boot-spl.bin &&" \
421376ae	251	"nand write $loadaddr 0 0x00010000 &&" \
d085ecd6	252	"tftpboot u-boot.bin &&" \
421376ae	253	"nand write $loadaddr 0x00010000 0x000f0000\0" \
421376ae	254	LINUXBOOT_ENV_SETTINGS
5894ca00	255
17bd4a21 MY	256	#define CONFIG_SYS_BOOTMAPSZ 0x20000000
17bd4a21 MY	257
cf88affa	258	#define CONFIG_SYS_SDRAM_BASE 0x80000000
5894ca00	259	#define CONFIG_NR_DRAM_BANKS 2
23869698 MY	260	/* for LD20; the last 64 byte is used for dynamic DDR PHY training */
23869698 MY	261	#define CONFIG_SYS_MEM_TOP_HIDE 64
5894ca00	262
9d0c2ceb MY	263	#if defined(CONFIG_ARM64)
	264	#define CONFIG_SPL_TEXT_BASE 0x30000000
	265	#elif defined(CONFIG_ARCH_UNIPHIER_SLD3) \|\| \
	266	defined(CONFIG_ARCH_UNIPHIER_LD4) \|\| \
ea65c980	267	defined(CONFIG_ARCH_UNIPHIER_SLD8)
f5d0b9b2	268	#define CONFIG_SPL_TEXT_BASE 0x00040000
323d1f9d	269	#else
f5d0b9b2 MY	270	#define CONFIG_SPL_TEXT_BASE 0x00100000
	271	#endif
	272
9d0c2ceb MY	273	#if defined(CONFIG_ARCH_UNIPHIER_LD20)
	274	#define CONFIG_SPL_STACK (0x3001c000)
	275	#else
755c7d9a	276	#define CONFIG_SPL_STACK (0x00100000)
9d0c2ceb	277	#endif
8cddc279	278	#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_TEXT_BASE)
5894ca00	279
a286039b MY	280	#define CONFIG_PANIC_HANG
a286039b MY	281
5894ca00	282	#define CONFIG_SPL_FRAMEWORK
499785b9	283	#define CONFIG_SPL_SERIAL_SUPPORT
cbbc2d80	284	#define CONFIG_SPL_NOR_SUPPORT
9d0c2ceb	285	#ifndef CONFIG_ARM64
5894ca00	286	#define CONFIG_SPL_NAND_SUPPORT
a55d9fee	287	#define CONFIG_SPL_MMC_SUPPORT
9d0c2ceb	288	#endif
5894ca00 MY	289
	290	#define CONFIG_SPL_LIBCOMMON_SUPPORT /* for mem_malloc_init */
	291	#define CONFIG_SPL_LIBGENERIC_SUPPORT
	292
	293	#define CONFIG_SPL_BOARD_INIT
	294
	295	#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x10000
cbbc2d80	296
d085ecd6 MY	297	/* subtract sizeof(struct image_header) */
d085ecd6 MY	298	#define CONFIG_SYS_UBOOT_BASE (0x60000 - 0x40)
a55d9fee	299	#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x80
5894ca00	300
d085ecd6	301	#define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
6a3cffe8	302	#define CONFIG_SPL_MAX_FOOTPRINT 0x10000
86c3345a	303	#define CONFIG_SPL_MAX_SIZE 0x10000
9d0c2ceb MY	304	#define CONFIG_SPL_BSS_START_ADDR 0x30016000
9d0c2ceb MY	305	#define CONFIG_SPL_BSS_MAX_SIZE 0x2000
6a3cffe8	306
5894ca00	307	#endif /* __CONFIG_UNIPHIER_COMMON_H__ */