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4707fb50 | 1 | /* |
82d9c9ec | 2 | * (C) Copyright 2003-2006 Wolfgang Denk, DENX Software Engineering, |
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3 | * wd@denx.de. |
4 | * | |
1a459660 | 5 | * SPDX-License-Identifier: GPL-2.0+ |
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6 | */ |
7 | ||
8 | #ifndef __CONFIG_H | |
9 | #define __CONFIG_H | |
10 | ||
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11 | /* |
12 | * High Level Configuration Options | |
13 | * (easy to change) | |
82d9c9ec | 14 | */ |
82d9c9ec BS |
15 | #define CONFIG_MPC5200 1 /* This is an MPC5200 CPU */ |
16 | #define CONFIG_V38B 1 /* ...on V38B board */ | |
e1219229 | 17 | #define CONFIG_DISPLAY_BOARDINFO |
2ae18241 WD |
18 | |
19 | #define CONFIG_SYS_TEXT_BASE 0xFF000000 | |
20 | ||
6d0f6bcf | 21 | #define CONFIG_SYS_MPC5XXX_CLKIN 33000000 /* ...running at 33.000000MHz */ |
4707fb50 | 22 | |
82d9c9ec BS |
23 | #define CONFIG_RTC_PCF8563 1 /* has PCF8563 RTC */ |
24 | #define CONFIG_MPC5200_DDR 1 /* has DDR SDRAM */ | |
4707fb50 | 25 | |
ce3f1a40 | 26 | #undef CONFIG_HW_WATCHDOG /* don't use watchdog */ |
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27 | |
28 | #define CONFIG_NETCONSOLE 1 | |
29 | ||
82d9c9ec | 30 | #define CONFIG_BOARD_EARLY_INIT_R 1 /* do board-specific init */ |
cce4acbb | 31 | #define CONFIG_BOARD_EARLY_INIT_F 1 /* do board-specific init */ |
d8d21e69 | 32 | #define CONFIG_MISC_INIT_R |
4707fb50 | 33 | |
6d0f6bcf | 34 | #define CONFIG_SYS_XLB_PIPELINING 1 /* gives better performance */ |
4707fb50 | 35 | |
31d82672 BB |
36 | #define CONFIG_HIGH_BATS 1 /* High BATs supported */ |
37 | ||
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38 | /* |
39 | * Serial console configuration | |
40 | */ | |
82d9c9ec BS |
41 | #define CONFIG_PSC_CONSOLE 1 /* console is on PSC1 */ |
42 | #define CONFIG_BAUDRATE 115200 /* ... at 115200 bps */ | |
6d0f6bcf | 43 | #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 } |
4707fb50 | 44 | |
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45 | /* |
46 | * DDR | |
47 | */ | |
48 | #define SDRAM_DDR 1 /* is DDR */ | |
49 | /* Settings for XLB = 132 MHz */ | |
50 | #define SDRAM_MODE 0x018D0000 | |
51 | #define SDRAM_EMODE 0x40090000 | |
52 | #define SDRAM_CONTROL 0x704f0f00 | |
53 | #define SDRAM_CONFIG1 0x73722930 | |
54 | #define SDRAM_CONFIG2 0x47770000 | |
55 | #define SDRAM_TAPDELAY 0x10000000 | |
56 | ||
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57 | /* |
58 | * PCI - no suport | |
59 | */ | |
60 | #undef CONFIG_PCI | |
61 | ||
62 | /* | |
63 | * Partitions | |
64 | */ | |
65 | #define CONFIG_MAC_PARTITION 1 | |
66 | #define CONFIG_DOS_PARTITION 1 | |
67 | ||
68 | /* | |
69 | * USB | |
70 | */ | |
71 | #define CONFIG_USB_OHCI | |
72 | #define CONFIG_USB_STORAGE | |
82d9c9ec BS |
73 | #define CONFIG_USB_CLOCK 0x0001BBBB |
74 | #define CONFIG_USB_CONFIG 0x00001000 | |
4707fb50 | 75 | |
dca3b3d6 | 76 | |
079a136c JL |
77 | /* |
78 | * BOOTP options | |
79 | */ | |
80 | #define CONFIG_BOOTP_BOOTFILESIZE | |
81 | #define CONFIG_BOOTP_BOOTPATH | |
82 | #define CONFIG_BOOTP_GATEWAY | |
83 | #define CONFIG_BOOTP_HOSTNAME | |
84 | ||
85 | ||
4707fb50 | 86 | /* |
dca3b3d6 | 87 | * Command line configuration. |
4707fb50 | 88 | */ |
dca3b3d6 | 89 | #define CONFIG_CMD_FAT |
dca3b3d6 | 90 | #define CONFIG_CMD_IDE |
dca3b3d6 JL |
91 | #define CONFIG_CMD_DIAG |
92 | #define CONFIG_CMD_IRQ | |
93 | #define CONFIG_CMD_JFFS2 | |
94 | #define CONFIG_CMD_MII | |
95 | #define CONFIG_CMD_SDRAM | |
96 | #define CONFIG_CMD_DATE | |
dca3b3d6 | 97 | #define CONFIG_CMD_FAT |
4707fb50 | 98 | |
82d9c9ec | 99 | |
dca3b3d6 | 100 | #define CONFIG_TIMESTAMP /* Print image info with timestamp */ |
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101 | |
102 | /* | |
103 | * Boot low with 16 MB Flash | |
104 | */ | |
6d0f6bcf JCPV |
105 | #define CONFIG_SYS_LOWBOOT 1 |
106 | #define CONFIG_SYS_LOWBOOT16 1 | |
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107 | |
108 | /* | |
109 | * Autobooting | |
110 | */ | |
111 | #define CONFIG_BOOTDELAY 3 /* autoboot after 3 seconds */ | |
112 | ||
82d9c9ec | 113 | #define CONFIG_PREBOOT "echo;" \ |
32bf3d14 | 114 | "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \ |
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115 | "echo" |
116 | ||
82d9c9ec | 117 | #undef CONFIG_BOOTARGS |
4707fb50 | 118 | |
fcfed4f2 | 119 | #define CONFIG_EXTRA_ENV_SETTINGS \ |
82d9c9ec BS |
120 | "bootcmd=run net_nfs\0" \ |
121 | "bootdelay=3\0" \ | |
122 | "baudrate=115200\0" \ | |
123 | "preboot=echo;echo Type \"run flash_nfs\" to mount root " \ | |
124 | "filesystem over NFS; echo\0" \ | |
fcfed4f2 | 125 | "netdev=eth0\0" \ |
cce4acbb | 126 | "ramargs=setenv bootargs root=/dev/ram rw wdt=off \0" \ |
fcfed4f2 WD |
127 | "addip=setenv bootargs $(bootargs) " \ |
128 | "ip=$(ipaddr):$(serverip):$(gatewayip):" \ | |
129 | "$(netmask):$(hostname):$(netdev):off panic=1\0" \ | |
130 | "flash_nfs=run nfsargs addip;bootm $(kernel_addr)\0" \ | |
131 | "flash_self=run ramargs addip;bootm $(kernel_addr) " \ | |
132 | "$(ramdisk_addr)\0" \ | |
82d9c9ec | 133 | "net_nfs=tftp 200000 $(bootfile);run nfsargs addip;bootm\0" \ |
fcfed4f2 | 134 | "nfsargs=setenv bootargs root=/dev/nfs rw " \ |
cce4acbb | 135 | "nfsroot=$(serverip):$(rootpath) wdt=off\0" \ |
82d9c9ec | 136 | "hostname=v38b\0" \ |
48690d80 | 137 | "ethact=FEC\0" \ |
82d9c9ec BS |
138 | "rootpath=/opt/eldk-3.1.1/ppc_6xx\0" \ |
139 | "update=prot off ff000000 ff03ffff; era ff000000 ff03ffff; " \ | |
140 | "cp.b 200000 ff000000 $(filesize);" \ | |
141 | "prot on ff000000 ff03ffff\0" \ | |
142 | "load=tftp 200000 $(u-boot)\0" \ | |
143 | "netmask=255.255.0.0\0" \ | |
144 | "ipaddr=192.168.160.18\0" \ | |
145 | "serverip=192.168.1.1\0" \ | |
82d9c9ec BS |
146 | "bootfile=/tftpboot/v38b/uImage\0" \ |
147 | "u-boot=/tftpboot/v38b/u-boot.bin\0" \ | |
fcfed4f2 | 148 | "" |
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149 | |
150 | #define CONFIG_BOOTCOMMAND "run net_nfs" | |
151 | ||
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152 | /* |
153 | * IPB Bus clocking configuration. | |
154 | */ | |
6d0f6bcf | 155 | #undef CONFIG_SYS_IPBCLK_EQUALS_XLBCLK /* define for 133MHz speed */ |
82d9c9ec | 156 | |
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157 | /* |
158 | * I2C configuration | |
159 | */ | |
160 | #define CONFIG_HARD_I2C 1 /* I2C with hardware support */ | |
6d0f6bcf JCPV |
161 | #define CONFIG_SYS_I2C_MODULE 2 /* Select I2C module #1 or #2 */ |
162 | #define CONFIG_SYS_I2C_SPEED 100000 /* 100 kHz */ | |
163 | #define CONFIG_SYS_I2C_SLAVE 0x7F | |
4707fb50 BS |
164 | |
165 | /* | |
166 | * EEPROM configuration | |
167 | */ | |
6d0f6bcf JCPV |
168 | #define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* 1010000x */ |
169 | #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 | |
170 | #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 | |
171 | #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 70 | |
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172 | |
173 | /* | |
174 | * RTC configuration | |
175 | */ | |
6d0f6bcf | 176 | #define CONFIG_SYS_I2C_RTC_ADDR 0x51 |
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177 | |
178 | /* | |
179 | * Flash configuration - use CFI driver | |
180 | */ | |
6d0f6bcf | 181 | #define CONFIG_SYS_FLASH_CFI 1 /* Flash is CFI conformant */ |
00b1883a | 182 | #define CONFIG_FLASH_CFI_DRIVER 1 /* Use the common driver */ |
6d0f6bcf JCPV |
183 | #define CONFIG_SYS_FLASH_CFI_AMD_RESET 1 |
184 | #define CONFIG_SYS_FLASH_BASE 0xFF000000 | |
185 | #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of flash banks */ | |
186 | #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE } | |
187 | #define CONFIG_SYS_FLASH_SIZE 0x01000000 /* 16 MiB */ | |
188 | #define CONFIG_SYS_MAX_FLASH_SECT 256 /* max num of sects on one chip */ | |
189 | #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 /* flash write speed-up */ | |
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190 | |
191 | /* | |
192 | * Environment settings | |
193 | */ | |
5a1aceb0 | 194 | #define CONFIG_ENV_IS_IN_FLASH 1 |
6d0f6bcf | 195 | #define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x00040000) |
0e8d1586 JCPV |
196 | #define CONFIG_ENV_SIZE 0x10000 |
197 | #define CONFIG_ENV_SECT_SIZE 0x10000 | |
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198 | #define CONFIG_ENV_OVERWRITE 1 |
199 | ||
200 | /* | |
201 | * Memory map | |
202 | */ | |
6d0f6bcf JCPV |
203 | #define CONFIG_SYS_MBAR 0xF0000000 |
204 | #define CONFIG_SYS_SDRAM_BASE 0x00000000 | |
205 | #define CONFIG_SYS_DEFAULT_MBAR 0x80000000 | |
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206 | |
207 | /* Use SRAM until RAM will be available */ | |
6d0f6bcf | 208 | #define CONFIG_SYS_INIT_RAM_ADDR MPC5XXX_SRAM |
553f0982 | 209 | #define CONFIG_SYS_INIT_RAM_SIZE MPC5XXX_SRAM_SIZE /* Size of used area in DPRAM */ |
4707fb50 | 210 | |
25ddd1fb | 211 | #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) |
6d0f6bcf | 212 | #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET |
4707fb50 | 213 | |
14d0a02a | 214 | #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE |
6d0f6bcf JCPV |
215 | #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE) |
216 | # define CONFIG_SYS_RAMBOOT 1 | |
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217 | #endif |
218 | ||
6d0f6bcf JCPV |
219 | #define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256kB for Monitor */ |
220 | #define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128kB for malloc() */ | |
221 | #define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Linux initial memory map */ | |
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222 | |
223 | /* | |
224 | * Ethernet configuration | |
225 | */ | |
226 | #define CONFIG_MPC5xxx_FEC 1 | |
86321fc1 | 227 | #define CONFIG_MPC5xxx_FEC_MII100 |
4707fb50 | 228 | #define CONFIG_PHY_ADDR 0x00 |
fcfed4f2 | 229 | #define CONFIG_MII 1 |
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230 | |
231 | /* | |
232 | * GPIO configuration | |
233 | */ | |
6d0f6bcf | 234 | #define CONFIG_SYS_GPS_PORT_CONFIG 0x90001404 |
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235 | |
236 | /* | |
237 | * Miscellaneous configurable options | |
238 | */ | |
6d0f6bcf | 239 | #define CONFIG_SYS_LONGHELP /* undef to save memory */ |
dca3b3d6 | 240 | #if defined(CONFIG_CMD_KGDB) |
6d0f6bcf | 241 | #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ |
4707fb50 | 242 | #else |
6d0f6bcf | 243 | #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ |
4707fb50 | 244 | #endif |
6d0f6bcf JCPV |
245 | #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ |
246 | #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ | |
247 | #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ | |
4707fb50 | 248 | |
6d0f6bcf JCPV |
249 | #define CONFIG_SYS_MEMTEST_START 0x00100000 /* memtest works on */ |
250 | #define CONFIG_SYS_MEMTEST_END 0x00f00000 /* 1 ... 15 MB in DRAM */ | |
4707fb50 | 251 | |
6d0f6bcf | 252 | #define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */ |
4707fb50 | 253 | |
6d0f6bcf | 254 | #define CONFIG_SYS_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */ |
dca3b3d6 | 255 | #if defined(CONFIG_CMD_KGDB) |
6d0f6bcf | 256 | # define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */ |
dca3b3d6 JL |
257 | #endif |
258 | ||
4707fb50 BS |
259 | /* |
260 | * Various low-level settings | |
261 | */ | |
6d0f6bcf JCPV |
262 | #define CONFIG_SYS_HID0_INIT HID0_ICE | HID0_ICFI |
263 | #define CONFIG_SYS_HID0_FINAL HID0_ICE | |
4707fb50 | 264 | |
6d0f6bcf JCPV |
265 | #define CONFIG_SYS_BOOTCS_START CONFIG_SYS_FLASH_BASE |
266 | #define CONFIG_SYS_BOOTCS_SIZE CONFIG_SYS_FLASH_SIZE | |
267 | #define CONFIG_SYS_BOOTCS_CFG 0x00047801 | |
268 | #define CONFIG_SYS_CS0_START CONFIG_SYS_FLASH_BASE | |
269 | #define CONFIG_SYS_CS0_SIZE CONFIG_SYS_FLASH_SIZE | |
4707fb50 | 270 | |
6d0f6bcf JCPV |
271 | #define CONFIG_SYS_CS_BURST 0x00000000 |
272 | #define CONFIG_SYS_CS_DEADCYCLE 0x33333333 | |
4707fb50 | 273 | |
6d0f6bcf | 274 | #define CONFIG_SYS_RESET_ADDRESS 0xff000000 |
4707fb50 | 275 | |
82d9c9ec BS |
276 | /* |
277 | * IDE/ATA (supports IDE harddisk) | |
4707fb50 | 278 | */ |
82d9c9ec BS |
279 | #undef CONFIG_IDE_8xx_PCCARD /* Don't use IDE with PC Card Adapter */ |
280 | #undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */ | |
281 | #undef CONFIG_IDE_LED /* LED for ide not supported */ | |
4707fb50 | 282 | |
82d9c9ec | 283 | #define CONFIG_IDE_RESET /* reset for ide supported */ |
4707fb50 BS |
284 | #define CONFIG_IDE_PREINIT |
285 | ||
6d0f6bcf JCPV |
286 | #define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE bus */ |
287 | #define CONFIG_SYS_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */ | |
4707fb50 | 288 | |
6d0f6bcf | 289 | #define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000 |
4707fb50 | 290 | |
6d0f6bcf | 291 | #define CONFIG_SYS_ATA_BASE_ADDR MPC5XXX_ATA |
4707fb50 | 292 | |
6d0f6bcf | 293 | #define CONFIG_SYS_ATA_DATA_OFFSET (0x0060) /* data I/O offset */ |
4707fb50 | 294 | |
6d0f6bcf | 295 | #define CONFIG_SYS_ATA_REG_OFFSET (CONFIG_SYS_ATA_DATA_OFFSET) /* normal register accesses offset */ |
4707fb50 | 296 | |
6d0f6bcf | 297 | #define CONFIG_SYS_ATA_ALT_OFFSET (0x005C) /* alternate registers offset */ |
4707fb50 | 298 | |
6d0f6bcf | 299 | #define CONFIG_SYS_ATA_STRIDE 4 /* Interval between registers */ |
4707fb50 | 300 | |
82d9c9ec BS |
301 | /* |
302 | * Status LED | |
303 | */ | |
304 | #define CONFIG_STATUS_LED /* Status LED enabled */ | |
305 | #define CONFIG_BOARD_SPECIFIC_LED /* version has board specific leds */ | |
4707fb50 | 306 | |
6d0f6bcf | 307 | #define CONFIG_SYS_LED_BASE MPC5XXX_GPT7_ENABLE /* Timer 7 GPIO */ |
4707fb50 | 308 | #ifndef __ASSEMBLY__ |
4707fb50 BS |
309 | typedef unsigned int led_id_t; |
310 | ||
311 | #define __led_toggle(_msk) \ | |
312 | do { \ | |
6d0f6bcf | 313 | *((volatile long *) (CONFIG_SYS_LED_BASE)) ^= (_msk); \ |
4707fb50 BS |
314 | } while(0) |
315 | ||
316 | #define __led_set(_msk, _st) \ | |
317 | do { \ | |
318 | if ((_st)) \ | |
6d0f6bcf | 319 | *((volatile long *) (CONFIG_SYS_LED_BASE)) &= ~(_msk); \ |
4707fb50 | 320 | else \ |
6d0f6bcf | 321 | *((volatile long *) (CONFIG_SYS_LED_BASE)) |= (_msk); \ |
4707fb50 BS |
322 | } while(0) |
323 | ||
324 | #define __led_init(_msk, st) \ | |
82d9c9ec | 325 | do { \ |
6d0f6bcf | 326 | *((volatile long *) (CONFIG_SYS_LED_BASE)) |= 0x34; \ |
82d9c9ec BS |
327 | } while(0) |
328 | #endif /* __ASSEMBLY__ */ | |
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329 | |
330 | #endif /* __CONFIG_H */ |