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1 | /* |
2 | * Copyright (C) 2007, Guennadi Liakhovetski <lg@denx.de> | |
3 | * | |
4 | * (C) Copyright 2009 Freescale Semiconductor, Inc. | |
5 | * | |
6 | * Configuration settings for the MX51-3Stack Freescale board. | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or | |
9 | * modify it under the terms of the GNU General Public License as | |
10 | * published by the Free Software Foundation; either version 2 of | |
11 | * the License, or (at your option) any later version. | |
12 | * | |
13 | * This program is distributed in the hope that it will be useful, | |
14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | * GNU General Public License for more details. | |
17 | * | |
18 | * You should have received a copy of the GNU General Public License | |
19 | * along with this program; if not, write to the Free Software | |
20 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | |
21 | * MA 02111-1307 USA | |
22 | */ | |
23 | ||
24 | #ifndef __CONFIG_H | |
25 | #define __CONFIG_H | |
26 | ||
27 | #include <asm/arch/imx-regs.h> | |
28 | ||
29 | #define CONFIG_MX51 /* in a mx51 */ | |
30 | #define CONFIG_L2_OFF | |
31 | ||
ff9f475d JL |
32 | #define CONFIG_SYS_MX5_HCLK 24000000 |
33 | #define CONFIG_SYS_MX5_CLK32 32768 | |
f8f8acd7 SB |
34 | #define CONFIG_DISPLAY_CPUINFO |
35 | #define CONFIG_DISPLAY_BOARDINFO | |
36 | ||
37 | #define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */ | |
38 | #define CONFIG_REVISION_TAG | |
39 | #define CONFIG_SETUP_MEMORY_TAGS | |
40 | #define CONFIG_INITRD_TAG | |
41 | #define BOARD_LATE_INIT | |
42 | ||
43 | /* | |
44 | * Size of malloc() pool | |
45 | */ | |
46 | #define CONFIG_SYS_MALLOC_LEN (2048 * 1024) | |
47 | ||
48 | /* size in bytes reserved for initial data */ | |
49 | #define CONFIG_SYS_GBL_DATA_SIZE 128 | |
50 | ||
51 | /* | |
52 | * Hardware drivers | |
53 | */ | |
54 | #define CONFIG_MXC_UART | |
55 | #define CONFIG_SYS_MX51_UART3 | |
56 | #define CONFIG_MXC_GPIO | |
57 | #define CONFIG_MXC_SPI | |
58 | #define CONFIG_HW_WATCHDOG | |
59 | ||
60 | /* | |
61 | * SPI Configs | |
62 | * */ | |
63 | #define CONFIG_FSL_SF | |
64 | #define CONFIG_CMD_SF | |
65 | ||
66 | #define CONFIG_SPI_FLASH | |
67 | #define CONFIG_SPI_FLASH_STMICRO | |
68 | ||
69 | /* | |
70 | * Use gpio 4 pin 25 as chip select for SPI flash | |
71 | * This corresponds to gpio 121 | |
72 | */ | |
73 | #define CONFIG_SPI_FLASH_CS (1 | (121 << 8)) | |
74 | #define CONFIG_SF_DEFAULT_MODE SPI_MODE_0 | |
75 | #define CONFIG_SF_DEFAULT_SPEED 25000000 | |
76 | ||
77 | #define CONFIG_ENV_SPI_CS (1 | (121 << 8)) | |
78 | #define CONFIG_ENV_SPI_BUS 0 | |
79 | #define CONFIG_ENV_SPI_MAX_HZ 25000000 | |
80 | #define CONFIG_ENV_SPI_MODE SPI_MODE_0 | |
81 | ||
82 | #define CONFIG_ENV_OFFSET (6 * 64 * 1024) | |
83 | #define CONFIG_ENV_SECT_SIZE (1 * 64 * 1024) | |
84 | #define CONFIG_ENV_SIZE (4 * 1024) | |
85 | ||
86 | #define CONFIG_FSL_ENV_IN_SF | |
87 | #define CONFIG_ENV_IS_IN_SPI_FLASH | |
88 | ||
89 | /* PMIC Controller */ | |
90 | #define CONFIG_FSL_PMIC | |
91 | #define CONFIG_FSL_PMIC_BUS 0 | |
92 | #define CONFIG_FSL_PMIC_CS 0 | |
93 | #define CONFIG_FSL_PMIC_CLK 2500000 | |
94 | #define CONFIG_FSL_PMIC_MODE SPI_MODE_0 | |
95 | #define CONFIG_RTC_MC13783 | |
96 | ||
97 | /* | |
98 | * MMC Configs | |
99 | */ | |
100 | #define CONFIG_FSL_ESDHC | |
101 | #ifdef CONFIG_FSL_ESDHC | |
102 | #define CONFIG_SYS_FSL_ESDHC_ADDR (0x70004000) | |
103 | #define CONFIG_SYS_FSL_ESDHC_NUM 1 | |
104 | ||
105 | #define CONFIG_MMC | |
106 | ||
107 | #define CONFIG_CMD_MMC | |
108 | #define CONFIG_GENERIC_MMC | |
109 | #define CONFIG_CMD_FAT | |
110 | #define CONFIG_DOS_PARTITION | |
111 | #endif | |
112 | ||
113 | #define CONFIG_CMD_DATE | |
114 | ||
115 | /* | |
116 | * Eth Configs | |
117 | */ | |
118 | #define CONFIG_HAS_ETH1 | |
119 | #define CONFIG_NET_MULTI | |
120 | #define CONFIG_MII | |
121 | #define CONFIG_DISCOVER_PHY | |
122 | ||
123 | #define CONFIG_FEC_MXC | |
124 | #define IMX_FEC_BASE FEC_BASE_ADDR | |
125 | #define CONFIG_FEC_MXC_PHYADDR 0x1F | |
126 | ||
127 | #define CONFIG_CMD_PING | |
128 | #define CONFIG_CMD_MII | |
129 | #define CONFIG_CMD_NET | |
130 | ||
131 | /* allow to overwrite serial and ethaddr */ | |
132 | #define CONFIG_ENV_OVERWRITE | |
133 | #define CONFIG_CONS_INDEX 3 | |
134 | #define CONFIG_BAUDRATE 115200 | |
135 | #define CONFIG_SYS_BAUDRATE_TABLE {9600, 19200, 38400, 57600, 115200} | |
136 | ||
137 | /*********************************************************** | |
138 | * Command definition | |
139 | ***********************************************************/ | |
140 | ||
141 | #include <config_cmd_default.h> | |
142 | ||
143 | #define CONFIG_CMD_SPI | |
144 | #undef CONFIG_CMD_IMLS | |
145 | ||
146 | #define CONFIG_BOOTDELAY 3 | |
147 | ||
148 | #define CONFIG_LOADADDR 0x90800000 /* loadaddr env var */ | |
149 | ||
150 | #define CONFIG_EXTRA_ENV_SETTINGS \ | |
151 | "netdev=eth0\0" \ | |
152 | "loadaddr=0x90800000\0" | |
153 | ||
154 | /* | |
155 | * Miscellaneous configurable options | |
156 | */ | |
157 | #define CONFIG_SYS_LONGHELP | |
158 | #define CONFIG_SYS_PROMPT "Vision II U-boot > " | |
159 | #define CONFIG_AUTO_COMPLETE | |
160 | #define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */ | |
161 | ||
162 | /* Print Buffer Size */ | |
163 | #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ | |
164 | sizeof(CONFIG_SYS_PROMPT) + 16) | |
165 | #define CONFIG_SYS_MAXARGS 64 /* max number of command args */ | |
166 | #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE | |
167 | ||
168 | #define CONFIG_SYS_MEMTEST_START 0x90000000 | |
169 | #define CONFIG_SYS_MEMTEST_END 0x10000 | |
170 | ||
171 | #define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR | |
172 | ||
173 | #define CONFIG_SYS_HZ 1000 | |
174 | #define CONFIG_CMDLINE_EDITING | |
175 | #define CONFIG_SYS_HUSH_PARSER | |
176 | #define CONFIG_SYS_PROMPT_HUSH_PS2 "Vision II U-boot > " | |
177 | ||
178 | /* | |
179 | * Stack sizes | |
180 | */ | |
181 | #define CONFIG_STACKSIZE (128 * 1024) /* regular stack */ | |
182 | ||
183 | /* | |
184 | * Physical Memory Map | |
185 | */ | |
186 | #define CONFIG_NR_DRAM_BANKS 2 | |
187 | #define PHYS_SDRAM_1 CSD0_BASE_ADDR | |
188 | #define PHYS_SDRAM_1_SIZE (256 * 1024 * 1024) | |
189 | #define PHYS_SDRAM_2 CSD1_BASE_ADDR | |
190 | #define PHYS_SDRAM_2_SIZE (256 * 1024 * 1024) | |
191 | #define CONFIG_SYS_SDRAM_BASE 0x90000000 | |
192 | #define CONFIG_SYS_INIT_RAM_ADDR 0x1FFE8000 | |
193 | ||
194 | #ifndef CONFIG_SYS_ARM_WITHOUT_RELOC | |
195 | #define CONFIG_SYS_INIT_RAM_END (64 * 1024) | |
196 | #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - \ | |
197 | CONFIG_SYS_GBL_DATA_SIZE) | |
198 | #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \ | |
199 | CONFIG_SYS_GBL_DATA_OFFSET) | |
200 | #undef CONFIG_SKIP_RELOCATE_UBOOT | |
201 | #else | |
202 | #define CONFIG_SKIP_RELOCATE_UBOOT | |
203 | #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + 0x2000) | |
204 | #endif | |
205 | ||
206 | #define CONFIG_BOARD_EARLY_INIT_F | |
207 | ||
208 | /* 166 MHz DDR RAM */ | |
209 | #define CONFIG_SYS_DDR_CLKSEL 0 | |
210 | #define CONFIG_SYS_CLKTL_CBCDR 0x19239100 | |
211 | ||
212 | #define CONFIG_SYS_NO_FLASH | |
213 | ||
a0152c4b SB |
214 | /* |
215 | * Framebuffer and LCD | |
216 | */ | |
217 | #define CONFIG_PREBOOT | |
218 | #define CONFIG_LCD | |
219 | #define CONFIG_VIDEO_MX5 | |
220 | #define CONFIG_SYS_CONSOLE_ENV_OVERWRITE | |
221 | #define CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE | |
222 | #define CONFIG_SYS_CONSOLE_IS_IN_ENV | |
223 | #define LCD_BPP LCD_COLOR16 | |
224 | #define CONFIG_SPLASH_SCREEN | |
225 | #define CONFIG_CMD_BMP | |
226 | #define CONFIG_BMP_16BPP | |
227 | ||
f8f8acd7 | 228 | #endif /* __CONFIG_H */ |