[people/ms/u-boot.git] / include / configs / vl_ma2sc.h

/*
 * (C) Copyright 2009-2012
 * Jens Scharsig  <esw@bus-elekronik.de>
 * BuS Elektronik GmbH & Co. KG
 *
 * Configuation settings for the VL_MA2SC board.
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

#ifndef __CONFIG_H
#define __CONFIG_H

/*--------------------------------------------------------------------------*/

#define CONFIG_AT91SAM9263		/* It's an Atmel AT91SAM9263 SoC*/
#define CONFIG_VL_MA2SC			/* on an VL_MA2SC Board	*/
#define CONFIG_ARCH_CPU_INIT
#define CONFIG_MISC_INIT_R

#include <asm/hardware.h>

#define MACH_TYPE_VL_MA2SC		2412
#define CONFIG_MACH_TYPE		MACH_TYPE_VL_MA2SC

#define CONFIG_SYS_DCACHE_OFF

#ifdef CONFIG_RAMLOAD
#define CONFIG_SYS_TEXT_BASE		0x21000000
#else
#define CONFIG_SYS_TEXT_BASE		0x00000000
#endif
#define CONFIG_SYS_LOAD_ADDR		0x21000000  /* default load address */

#define CONFIG_IDENT_STRING		" on MiS Activ 2"
#define CONFIG_VERSION_VARIABLE
#define CONFIG_AT91_GPIO

#if !defined(CONFIG_SYS_USE_NANDFLASH) && !defined(CONFIG_RAMLOAD)
#define CONFIG_SYS_USE_NORFLASH
#define CONFIG_SYS_USE_BOOT_NORFLASH
#endif

#define CONFIG_CMDLINE_TAG			/* enable passing of ATAGs */
#define CONFIG_SETUP_MEMORY_TAGS
#define CONFIG_INITRD_TAG

#ifndef CONFIG_SYS_USE_BOOT_NORFLASH
#define CONFIG_SKIP_LOWLEVEL_INIT
#endif

/*
 * Hardware drivers
 */

#define CONFIG_BOARD_EARLY_INIT_F

#define CONFIG_WATCHDOG

#define CONFIG_ATMEL_USART
#define CONFIG_USART_BASE		ATMEL_BASE_DBGU
#define CONFIG_USART_ID			ATMEL_ID_SYS

/* LCD */
#define CONFIG_LCD
#define CONFIG_ATMEL_LCD
#define CONFIG_SPLASH_SCREEN
#define CONFIG_SYS_BLACK_ON_WHITE
#define LCD_BPP				LCD_COLOR8
#define CONFIG_ATMEL_LCD_BGR555

#define CONFIG_SYS_CONSOLE_IS_IN_ENV
#define CONFIG_BOOTDELAY		3

/*
 * BOOTP options
 */
#define CONFIG_BOOTP_BOOTFILESIZE
#define CONFIG_BOOTP_BOOTPATH
#define CONFIG_BOOTP_GATEWAY
#define CONFIG_BOOTP_HOSTNAME

/*
 * Command line configuration.
 */
#include <config_cmd_default.h>
#undef CONFIG_CMD_BDI
#undef CONFIG_CMD_FPGA
#undef CONFIG_CMD_IMI
#undef CONFIG_CMD_LOADS

#define CONFIG_CMD_BMP
#define CONFIG_CMD_DATE
#define CONFIG_CMD_DHCP
#define CONFIG_CMD_I2C
#define CONFIG_CMD_NAND
#define CONFIG_CMD_MII
#define CONFIG_CMD_PING
#define CONFIG_CMD_MD5SUM
#define CONFIG_CMD_SHA1SUM
/*
#define CONFIG_CMD_SPI
*/
#define CONFIG_CMD_FAT
#define CONFIG_CMD_USB

#define	CONFIG_SYS_LONGHELP
#define CONFIG_MD5
#define	CONFIG_SHA1

/*----------------------------------------------------------------------------
 * Hardware confuguration
 *---------------------------------------------------------------------------*/

/* USB */
#define CONFIG_USB_ATMEL
#define CONFIG_USB_ATMEL_CLK_SEL_PLLB
#define CONFIG_USB_OHCI_NEW
#define CONFIG_DOS_PARTITION
#define CONFIG_SYS_USB_OHCI_CPU_INIT
#define CONFIG_SYS_USB_OHCI_REGS_BASE		0x00a00000	/* UHP_BASE */
#define CONFIG_SYS_USB_OHCI_SLOT_NAME		"at91sam9263"
#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS	2
#define CONFIG_USB_STORAGE
#define CONFIG_AT91C_PQFP_UHPBUG

/* I2C-Bus */

#define CONFIG_SYS_I2C_SPEED			50000
#define CONFIG_SYS_I2C_SLAVE			0		/* not used */

#ifndef CONFIG_HARD_I2C
#define CONFIG_SYS_I2C
#define CONFIG_SYS_I2C_SOFT			/* I2C bit-banged */
#define CONFIG_SYS_I2C_SOFT_SPEED	CONFIG_SYS_I2C_SPEED
#define CONFIG_SYS_I2C_SOFT_SLAVE	CONFIG_SYS_I2C_SLAVE

/* Software  I2C driver configuration */
#define I2C_DELAY	udelay(2500000/CONFIG_SYS_I2C_SPEED)

#define AT91_PIN_SDA	(1<<4)		/* AT91C_PIO_PB4 */
#define AT91_PIN_SCL	(1<<5)		/* AT91C_PIO_PB5 */

#define I2C_INIT	i2c_init_board();
#define I2C_ACTIVE	writel(AT91_PIN_SDA, &pio->piob.mddr);
#define I2C_TRISTATE	writel(AT91_PIN_SDA, &pio->piob.mder);
#define I2C_READ	((readl(&pio->piob.pdsr) & AT91_PIN_SDA) != 0)
#define I2C_SDA(bit)						\
	do {							\
		if (bit)					\
			writel(AT91_PIN_SDA, &pio->piob.sodr);	\
		else						\
			writel(AT91_PIN_SDA, &pio->piob.codr);	\
	} while (0);
#define I2C_SCL(bit)						\
	do {							\
		if (bit)					\
			writel(AT91_PIN_SCL, &pio->piob.sodr);	\
		else						\
			writel(AT91_PIN_SCL, &pio->piob.codr);	\
	} while (0);
#endif

/* I2C-RTC */

#ifdef CONFIG_CMD_DATE
#define CONFIG_RTC_DS1338
#define CONFIG_SYS_I2C_RTC_ADDR	0x68
#endif

/* EEPROM */

#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN	2
#define CONFIG_SYS_I2C_EEPROM_ADDR	0x50

/* define PDC[31:16] as DATA[31:16] */
#define CONFIG_SYS_PIOD_PDR_VAL1	0xFFFF0000
#define CONFIG_SYS_PIOD_PPUDR_VAL	0xFFFF0000

/* EBI0_CSA, CS1 SDRAM, CS3 NAND Flash, 3.3V memories */
#define CONFIG_SYS_MATRIX_EBI0CSA_VAL					\
	(AT91_MATRIX_CSA_DBPUC | AT91_MATRIX_CSA_VDDIOMSEL_3_3V |	\
	 AT91_MATRIX_CSA_EBI_CS1A)

/* user reset enable */
#define CONFIG_SYS_RSTC_RMR_VAL			\
		(AT91_RSTC_KEY |		\
		AT91_RSTC_MR_URSTEN |		\
		AT91_RSTC_MR_ERSTL(15))

/* Disable Watchdog */
#define CONFIG_SYS_WDTC_WDMR_VAL				\
		(AT91_WDT_MR_WDIDLEHLT | AT91_WDT_MR_WDDBGHLT |	\
		 AT91_WDT_MR_WDV(0xFFF) |			\
		 AT91_WDT_MR_WDDIS |				\
		 AT91_WDT_MR_WDD(0xFFF))

/* clocks */

#define CONFIG_SYS_AT91_SLOW_CLOCK	32768		/* slow clock */

#define MHZ180
#if defined(MHZ199)
/* 199,8994 MHZ */
#define MASTER_PLL_MUL		911
#define MASTER_PLL_DIV		56
#define MASTER_PLL_OUT		2
#elif defined(MHZ180)
/* 180 MHZ */
#define MASTER_PLL_MUL		1875
#define MASTER_PLL_DIV		128
#define MASTER_PLL_OUT		2
#elif defined(MHZTEST)
/* Test MHZ */
#define CONFIG_DISPLAY_CPUINFO
#define MASTER_PLL_MUL		8
#define MASTER_PLL_DIV		1
#define MASTER_PLL_OUT		2
#else
/* 176.9472 MHZ */
#define MASTER_PLL_MUL		72
#define MASTER_PLL_DIV		5
#define MASTER_PLL_OUT		2
#endif

#define CONFIG_SYS_MOR_VAL					\
	(AT91_PMC_MOR_MOSCEN | AT91_PMC_MOR_OSCOUNT(255))

#define CONFIG_SYS_PLLAR_VAL					\
	(AT91_PMC_PLLAR_29 |					\
	AT91_PMC_PLLXR_OUT(MASTER_PLL_OUT) |			\
	AT91_PMC_PLLXR_PLLCOUNT(63) |				\
	AT91_PMC_PLLXR_MUL(MASTER_PLL_MUL - 1) |		\
	AT91_PMC_PLLXR_DIV(MASTER_PLL_DIV))

/* PCK/2 = MCK Master Clock from PLLA */
#define	CONFIG_SYS_MCKR1_VAL		\
	(AT91_PMC_MCKR_CSS_SLOW | AT91_PMC_MCKR_PRES_1 |	\
	 AT91_PMC_MCKR_MDIV_2)

/* PCK/2 = MCK Master Clock from PLLA */
#define	CONFIG_SYS_MCKR2_VAL		\
	(AT91_PMC_MCKR_CSS_PLLA | AT91_PMC_MCKR_PRES_1 |	\
	AT91_PMC_MCKR_MDIV_2)

/* SDRAM */
#define CONFIG_NR_DRAM_BANKS		1
#define CONFIG_SYS_SDRAM_BASE		0x20000000
#define CONFIG_SYS_SDRAM_SIZE		0x04000000  /* 64 megs */
#define CONFIG_SYS_INIT_SP_ADDR		0x00504000  /* use internal SRAM0 */

#define CONFIG_SYS_SDRC_MR_VAL1		0
#define CONFIG_SYS_SDRC_TR_VAL1		700
#define CONFIG_SYS_SDRC_CR_VAL						\
		(AT91_SDRAMC_NC_9 |					\
		 AT91_SDRAMC_NR_13 |					\
		 AT91_SDRAMC_NB_4 |					\
		 AT91_SDRAMC_CAS_3 |					\
		 AT91_SDRAMC_DBW_32 |					\
		 (2 <<  8) |		/* Write Recovery Delay */	\
		 (7 << 12) |		/* Row Cycle Delay */		\
		 (2 << 16) |		/* Row Precharge Delay */	\
		 (2 << 20) |		/* Row to Column Delay */	\
		 (5 << 24) |		/* Active to Precharge Delay */	\
		 (8 << 28))		/* Exit Self Refresh to Active Delay */

#define CONFIG_SYS_SDRC_MDR_VAL		AT91_SDRAMC_MD_SDRAM
#define CONFIG_SYS_SDRC_MR_VAL2		AT91_SDRAMC_MODE_PRECHARGE
#define CONFIG_SYS_SDRAM_VAL1		0		/* SDRAM_BASE */
#define CONFIG_SYS_SDRC_MR_VAL3		AT91_SDRAMC_MODE_REFRESH
#define CONFIG_SYS_SDRAM_VAL2		0		/* SDRAM_BASE */
#define CONFIG_SYS_SDRAM_VAL3		0		/* SDRAM_BASE */
#define CONFIG_SYS_SDRAM_VAL4		0		/* SDRAM_BASE */
#define CONFIG_SYS_SDRAM_VAL5		0		/* SDRAM_BASE */
#define CONFIG_SYS_SDRAM_VAL6		0		/* SDRAM_BASE */
#define CONFIG_SYS_SDRAM_VAL7		0		/* SDRAM_BASE */
#define CONFIG_SYS_SDRAM_VAL8		0		/* SDRAM_BASE */
#define CONFIG_SYS_SDRAM_VAL9		0		/* SDRAM_BASE */
#define CONFIG_SYS_SDRC_MR_VAL4		AT91_SDRAMC_MODE_LMR
#define CONFIG_SYS_SDRAM_VAL10		0		/* SDRAM_BASE */
#define CONFIG_SYS_SDRC_MR_VAL5		AT91_SDRAMC_MODE_NORMAL
#define CONFIG_SYS_SDRAM_VAL11		0		/* SDRAM_BASE */
#define CONFIG_SYS_SDRC_TR_VAL2		1200		/* SDRAM_TR */
#define CONFIG_SYS_SDRAM_VAL12		0		/* SDRAM_BASE */

/* NOR flash */

#define CONFIG_FLASH_SHOW_PROGRESS	45
#define CONFIG_SYS_FLASH_CFI
#define CONFIG_FLASH_CFI_DRIVER
#define PHYS_FLASH_1			0x10000000
#define CONFIG_SYS_FLASH_BASE		PHYS_FLASH_1
#define CONFIG_SYS_MAX_FLASH_SECT	256
#define CONFIG_SYS_MAX_FLASH_BANKS	1

#define CONFIG_ENV_IS_IN_FLASH
#define CONFIG_ENV_ADDR			(CONFIG_SYS_FLASH_BASE + 0x00060000)

/* setup SMC0, CS0 (NOR Flash) - 16-bit, 15 WS */
#define CONFIG_SYS_SMC0_SETUP0_VAL				\
	(AT91_SMC_SETUP_NWE(10) | AT91_SMC_SETUP_NCS_WR(10) |	\
	 AT91_SMC_SETUP_NRD(10) | AT91_SMC_SETUP_NCS_RD(10))
#define CONFIG_SYS_SMC0_PULSE0_VAL				\
	(AT91_SMC_PULSE_NWE(11) | AT91_SMC_PULSE_NCS_WR(11) |	\
	 AT91_SMC_PULSE_NRD(11) | AT91_SMC_PULSE_NCS_RD(11))
#define CONFIG_SYS_SMC0_CYCLE0_VAL	\
	(AT91_SMC_CYCLE_NWE(22) | AT91_SMC_CYCLE_NRD(22))
#define CONFIG_SYS_SMC0_MODE0_VAL				\
	(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE |		\
	 AT91_SMC_MODE_DBW_16 |					\
	 AT91_SMC_MODE_TDF | AT91_SMC_MODE_TDF_CYCLE(6))

/* NAND flash */
#ifdef CONFIG_CMD_NAND
#define CONFIG_NAND_ATMEL
#define CONFIG_SYS_MAX_NAND_DEVICE	1
#define CONFIG_SYS_NAND_BASE		0x40000000
#define CONFIG_SYS_NAND_DBW_8		1
#define CONFIG_SYS_NAND_MASK_ALE	(1 << 21)	/* our ALE is AD21 */
#define CONFIG_SYS_NAND_MASK_CLE	(1 << 22)	/* our CLE is AD22 */
#define CONFIG_SYS_NAND_ENABLE_PIN	GPIO_PIN_PD(15)
#define CONFIG_SYS_NAND_READY_PIN	GPIO_PIN_PB(0)
#endif

/* Ethernet */
#define CONFIG_MACB
#define CONFIG_RMII
#define CONFIG_NET_RETRY_COUNT		5
#define CONFIG_AT91_WANTS_COMMON_PHY

#define CONFIG_OVERWRITE_ETHADDR_ONCE

#define CONFIG_SYS_LOAD_ADDR		0x21000000  /* default load address */

#define CONFIG_SYS_MEMTEST_START	CONFIG_SYS_SDRAM_BASE
#define CONFIG_SYS_MEMTEST_END		0x21e00000

/* Address and size of Primary Environment Sector */
#ifdef CONFIG_ENV_IS_IN_FLASH
#define CONFIG_ENV_SIZE			0x20000
#else
#define CONFIG_ENV_SIZE			0x2000
#endif

#define CONFIG_BAUDRATE			115200
#define CONFIG_SYS_BAUDRATE_TABLE	{312500, 230400, 115200, 19200, \
						38400, 57600, 9600 }

#define CONFIG_SYS_PROMPT	"U-Boot> "
#define CONFIG_SYS_CBSIZE	512		/* Console I/O Buffer Size */
#define CONFIG_SYS_MAXARGS	32		/* max number of command args */
#define CONFIG_SYS_PBSIZE	\
	(CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
#define CONFIG_CMDLINE_EDITING
#define CONFIG_AUTO_COMPLETE

/*
 * Size of malloc() pool
 */
#define CONFIG_SYS_MALLOC_LEN		\
	ROUND(3 * CONFIG_ENV_SIZE + 128 * 1024, 0x1000)

#ifndef CONFIG_RAMLOAD
#define CONFIG_BOOTCOMMAND		"run nfsboot"
#endif
#define CONFIG_BOOT_RETRY_TIME		-1
#define CONFIG_BOOT_RETRY_MIN		15

#define CONFIG_NFSBOOTCOMMAND						\
		"dhcp $(copy_addr) $(kernelname);"			\
		"run bootargsdefaults;"					\
		"set bootargs $(bootargs) boot=nfs "			\
		";echo $(bootargs)"					\
	";bootm"

#define CONFIG_EXTRA_ENV_SETTINGS					\
	"ubootaddr=10000000\0"						\
	"splashimage=10080000\0"					\
	"kerneladdr=100A0000\0"						\
	"kernelsize=00800000\0"						\
	"minifsaddr=108A0000\0"						\
	"minifssize=00060000\0"						\
	"rootfsaddr=10900000\0"						\
	"copy_addr=20200000\0"						\
	"rootfssize=01700000\0"						\
	"kernelname=uImage_vl_ma2sc\0"					\
	"bootargsdefaults=set bootargs "				\
		"console=ttyS0,115200 "					\
		"video=atmel_lcdfb "					\
		"mem=62M "						\
		"panic=10 "						\
		"boardrevison=\\\"${revision}\\\" "			\
		"uboot=\\\"${ver}\\\" "					\
		"\0"							\
	"update_all=run update_kernel;run update_root;"			\
		"run update_splash; run update_uboot\0"			\
	"update_kernel=protect off $(kerneladdr) +$(kernelsize);"	\
		"dhcp $(copy_addr) $(kernelname);"			\
		"erase $(kerneladdr) +$(kernelsize);"			\
		"cp.b $(fileaddr) $(kerneladdr) $(filesize);"		\
		"protect on $(kerneladdr) +$(kernelsize)"		\
		"\0"							\
	"update_root=protect off $(rootfsaddr) +$(rootfssize);"		\
		"dhcp $(copy_addr) vl_ma2sc.root;"			\
		"erase $(rootfsaddr) +$(rootfssize);"			\
		"cp.b $(fileaddr) $(rootfsaddr) $(filesize);"		\
		"\0"							\
	"update_splash=protect off $(splashimage) +20000;"		\
		"dhcp $(copy_addr) splash_vl_ma2sc.bmp;"		\
		"erase $(splashimage) +20000;"				\
		"cp.b $(fileaddr) 10080000 $(filesize);"		\
		"protect on $(splashimage) +20000\0"			\
	"update_uboot=protect off 10000000 1005FFFF;"			\
		"dhcp $(copy_addr) u-boot_vl_ma2sc;"			\
		"erase 10000000 1005FFFF;"				\
		"cp.b $(fileaddr) $(ubootaddr) $(filesize);"		\
		"protect on 10000000 1005FFFF;reset\0"			\
	"emergency=run bootargsdefaults;"				\
		"set bootargs $(bootargs) root=initramfs boot=emergency " \
		";bootm $(kerneladdr)\0"				\
	"netemergency=run bootargsdefaults;"				\
		"dhcp $(copy_addr) $(kernelname);"			\
		"set bootargs $(bootargs) root=initramfs boot=emergency " \
		";bootm $(copy_addr)\0"					\
	"norboot=run bootargsdefaults;"					\
		"set bootargs $(bootargs) root=initramfs boot=local quiet " \
		";bootm $(kerneladdr)\0"				\
	"nandboot=run bootargsdefaults;"				\
		"set bootargs $(bootargs) root=initramfs boot=nand "	\
		";bootm $(kerneladdr)\0"				\
	"setnorboot=set bootcmd 'run norboot'; set bootdelay 1;save\0"	\
	"clearenv=protect off 10060000 1007FFFF;"			\
		"erase 10060000 1007FFFF;reset\0"			\
	" "

#endif
Commit	Line	Data
4324c75f	1	/*
	2	* (C) Copyright 2009-2012
	3	* Jens Scharsig <esw@bus-elekronik.de>
	4	* BuS Elektronik GmbH & Co. KG
	5	*
	6	* Configuation settings for the VL_MA2SC board.
	7	*
1a459660	8	* SPDX-License-Identifier: GPL-2.0+
4324c75f	9	*/
	10
	11	#ifndef __CONFIG_H
	12	#define __CONFIG_H
	13
	14	/--------------------------------------------------------------------------/
	15
4324c75f	16	#define CONFIG_AT91SAM9263 /* It's an Atmel AT91SAM9263 SoC*/
	17	#define CONFIG_VL_MA2SC /* on an VL_MA2SC Board */
	18	#define CONFIG_ARCH_CPU_INIT
	19	#define CONFIG_MISC_INIT_R
	20
	21	#include <asm/hardware.h>
	22
	23	#define MACH_TYPE_VL_MA2SC 2412
	24	#define CONFIG_MACH_TYPE MACH_TYPE_VL_MA2SC
	25
	26	#define CONFIG_SYS_DCACHE_OFF
	27
	28	#ifdef CONFIG_RAMLOAD
	29	#define CONFIG_SYS_TEXT_BASE 0x21000000
	30	#else
	31	#define CONFIG_SYS_TEXT_BASE 0x00000000
	32	#endif
	33	#define CONFIG_SYS_LOAD_ADDR 0x21000000 /* default load address */
	34
	35	#define CONFIG_IDENT_STRING " on MiS Activ 2"
	36	#define CONFIG_VERSION_VARIABLE
	37	#define CONFIG_AT91_GPIO
	38
	39	#if !defined(CONFIG_SYS_USE_NANDFLASH) && !defined(CONFIG_RAMLOAD)
	40	#define CONFIG_SYS_USE_NORFLASH
	41	#define CONFIG_SYS_USE_BOOT_NORFLASH
	42	#endif
	43
	44	#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */
	45	#define CONFIG_SETUP_MEMORY_TAGS
	46	#define CONFIG_INITRD_TAG
	47
	48	#ifndef CONFIG_SYS_USE_BOOT_NORFLASH
	49	#define CONFIG_SKIP_LOWLEVEL_INIT
	50	#endif
	51
	52	/*
	53	* Hardware drivers
	54	*/
	55
	56	#define CONFIG_BOARD_EARLY_INIT_F
	57
	58	#define CONFIG_WATCHDOG
	59
	60	#define CONFIG_ATMEL_USART
	61	#define CONFIG_USART_BASE ATMEL_BASE_DBGU
	62	#define CONFIG_USART_ID ATMEL_ID_SYS
	63
	64	/* LCD */
	65	#define CONFIG_LCD
	66	#define CONFIG_ATMEL_LCD
	67	#define CONFIG_SPLASH_SCREEN
	68	#define CONFIG_SYS_BLACK_ON_WHITE
	69	#define LCD_BPP LCD_COLOR8
	70	#define CONFIG_ATMEL_LCD_BGR555
	71
	72	#define CONFIG_SYS_CONSOLE_IS_IN_ENV
	73	#define CONFIG_BOOTDELAY 3
	74
	75	/*
	76	* BOOTP options
	77	*/
	78	#define CONFIG_BOOTP_BOOTFILESIZE
	79	#define CONFIG_BOOTP_BOOTPATH
80	#define CONFIG_BOOTP_GATEWAY
81	#define CONFIG_BOOTP_HOSTNAME
82
83	/*
84	* Command line configuration.
85	*/
86	#include <config_cmd_default.h>
87	#undef CONFIG_CMD_BDI
88	#undef CONFIG_CMD_FPGA
89	#undef CONFIG_CMD_IMI
90	#undef CONFIG_CMD_LOADS
91
92	#define CONFIG_CMD_BMP
93	#define CONFIG_CMD_DATE
94	#define CONFIG_CMD_DHCP
95	#define CONFIG_CMD_I2C
96	#define CONFIG_CMD_NAND
97	#define CONFIG_CMD_MII
98	#define CONFIG_CMD_PING
99	#define CONFIG_CMD_MD5SUM
100	#define CONFIG_CMD_SHA1SUM
101	/*
102	#define CONFIG_CMD_SPI
103	*/
104	#define CONFIG_CMD_FAT
105	#define CONFIG_CMD_USB
106
107	#define CONFIG_SYS_LONGHELP
108	#define CONFIG_MD5
109	#define CONFIG_SHA1
110
111	/*----------------------------------------------------------------------------
112	* Hardware confuguration
113	---------------------------------------------------------------------------/
114
115	/* USB */
116	#define CONFIG_USB_ATMEL
dcd2f1a0	117	#define CONFIG_USB_ATMEL_CLK_SEL_PLLB
4324c75f	118	#define CONFIG_USB_OHCI_NEW
	119	#define CONFIG_DOS_PARTITION
	120	#define CONFIG_SYS_USB_OHCI_CPU_INIT
	121	#define CONFIG_SYS_USB_OHCI_REGS_BASE 0x00a00000 /* UHP_BASE */
	122	#define CONFIG_SYS_USB_OHCI_SLOT_NAME "at91sam9263"
	123	#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 2
	124	#define CONFIG_USB_STORAGE
	125	#define CONFIG_AT91C_PQFP_UHPBUG
	126
	127	/* I2C-Bus */
	128
	129	#define CONFIG_SYS_I2C_SPEED 50000
	130	#define CONFIG_SYS_I2C_SLAVE 0 /* not used */
	131
	132	#ifndef CONFIG_HARD_I2C
ea818dbb HS	133	#define CONFIG_SYS_I2C
	134	#define CONFIG_SYS_I2C_SOFT /* I2C bit-banged */
	135	#define CONFIG_SYS_I2C_SOFT_SPEED CONFIG_SYS_I2C_SPEED
	136	#define CONFIG_SYS_I2C_SOFT_SLAVE CONFIG_SYS_I2C_SLAVE
4324c75f	137
4324c75f	138	/* Software I2C driver configuration */
4324c75f	139	#define I2C_DELAY udelay(2500000/CONFIG_SYS_I2C_SPEED)
	140
	141	#define AT91_PIN_SDA (1<<4) /* AT91C_PIO_PB4 */
	142	#define AT91_PIN_SCL (1<<5) /* AT91C_PIO_PB5 */
	143
	144	#define I2C_INIT i2c_init_board();
	145	#define I2C_ACTIVE writel(AT91_PIN_SDA, &pio->piob.mddr);
	146	#define I2C_TRISTATE writel(AT91_PIN_SDA, &pio->piob.mder);
	147	#define I2C_READ ((readl(&pio->piob.pdsr) & AT91_PIN_SDA) != 0)
	148	#define I2C_SDA(bit) \
	149	do { \
	150	if (bit) \
	151	writel(AT91_PIN_SDA, &pio->piob.sodr); \
	152	else \
	153	writel(AT91_PIN_SDA, &pio->piob.codr); \
	154	} while (0);
	155	#define I2C_SCL(bit) \
	156	do { \
	157	if (bit) \
	158	writel(AT91_PIN_SCL, &pio->piob.sodr); \
	159	else \
	160	writel(AT91_PIN_SCL, &pio->piob.codr); \
	161	} while (0);
	162	#endif
	163
	164	/* I2C-RTC */
	165
	166	#ifdef CONFIG_CMD_DATE
	167	#define CONFIG_RTC_DS1338
	168	#define CONFIG_SYS_I2C_RTC_ADDR 0x68
	169	#endif
	170
	171	/* EEPROM */
	172
	173	#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
	174	#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50
	175
	176	/* define PDC[31:16] as DATA[31:16] */
	177	#define CONFIG_SYS_PIOD_PDR_VAL1 0xFFFF0000
	178	#define CONFIG_SYS_PIOD_PPUDR_VAL 0xFFFF0000
	179
	180	/* EBI0_CSA, CS1 SDRAM, CS3 NAND Flash, 3.3V memories */
	181	#define CONFIG_SYS_MATRIX_EBI0CSA_VAL \
	182	(AT91_MATRIX_CSA_DBPUC \| AT91_MATRIX_CSA_VDDIOMSEL_3_3V \| \
	183	AT91_MATRIX_CSA_EBI_CS1A)
	184
	185	/* user reset enable */
	186	#define CONFIG_SYS_RSTC_RMR_VAL \
	187	(AT91_RSTC_KEY \| \
	188	AT91_RSTC_MR_URSTEN \| \
	189	AT91_RSTC_MR_ERSTL(15))
	190
	191	/* Disable Watchdog */
	192	#define CONFIG_SYS_WDTC_WDMR_VAL \
	193	(AT91_WDT_MR_WDIDLEHLT \| AT91_WDT_MR_WDDBGHLT \| \
	194	AT91_WDT_MR_WDV(0xFFF) \| \
	195	AT91_WDT_MR_WDDIS \| \
	196	AT91_WDT_MR_WDD(0xFFF))
	197
	198	/* clocks */
	199
4324c75f	200	#define CONFIG_SYS_AT91_SLOW_CLOCK 32768 /* slow clock */
	201
	202	#define MHZ180
	203	#if defined(MHZ199)
	204	/* 199,8994 MHZ */
	205	#define MASTER_PLL_MUL 911
	206	#define MASTER_PLL_DIV 56
	207	#define MASTER_PLL_OUT 2
	208	#elif defined(MHZ180)
	209	/* 180 MHZ */
	210	#define MASTER_PLL_MUL 1875
	211	#define MASTER_PLL_DIV 128
	212	#define MASTER_PLL_OUT 2
	213	#elif defined(MHZTEST)
	214	/* Test MHZ */
	215	#define CONFIG_DISPLAY_CPUINFO
	216	#define MASTER_PLL_MUL 8
	217	#define MASTER_PLL_DIV 1
	218	#define MASTER_PLL_OUT 2
	219	#else
	220	/* 176.9472 MHZ */
	221	#define MASTER_PLL_MUL 72
	222	#define MASTER_PLL_DIV 5
	223	#define MASTER_PLL_OUT 2
	224	#endif
	225
	226	#define CONFIG_SYS_MOR_VAL \
	227	(AT91_PMC_MOR_MOSCEN \| AT91_PMC_MOR_OSCOUNT(255))
	228
	229	#define CONFIG_SYS_PLLAR_VAL \
	230	(AT91_PMC_PLLAR_29 \| \
	231	AT91_PMC_PLLXR_OUT(MASTER_PLL_OUT) \| \
	232	AT91_PMC_PLLXR_PLLCOUNT(63) \| \
	233	AT91_PMC_PLLXR_MUL(MASTER_PLL_MUL - 1) \| \
	234	AT91_PMC_PLLXR_DIV(MASTER_PLL_DIV))
	235
	236	/* PCK/2 = MCK Master Clock from PLLA */
	237	#define CONFIG_SYS_MCKR1_VAL \
	238	(AT91_PMC_MCKR_CSS_SLOW \| AT91_PMC_MCKR_PRES_1 \| \
	239	AT91_PMC_MCKR_MDIV_2)
	240
	241	/* PCK/2 = MCK Master Clock from PLLA */
	242	#define CONFIG_SYS_MCKR2_VAL \
	243	(AT91_PMC_MCKR_CSS_PLLA \| AT91_PMC_MCKR_PRES_1 \| \
	244	AT91_PMC_MCKR_MDIV_2)
	245
	246	/* SDRAM */
	247	#define CONFIG_NR_DRAM_BANKS 1
	248	#define CONFIG_SYS_SDRAM_BASE 0x20000000
	249	#define CONFIG_SYS_SDRAM_SIZE 0x04000000 /* 64 megs */
	250	#define CONFIG_SYS_INIT_SP_ADDR 0x00504000 /* use internal SRAM0 */
	251
	252	#define CONFIG_SYS_SDRC_MR_VAL1 0
	253	#define CONFIG_SYS_SDRC_TR_VAL1 700
	254	#define CONFIG_SYS_SDRC_CR_VAL \
	255	(AT91_SDRAMC_NC_9 \| \
	256	AT91_SDRAMC_NR_13 \| \
	257	AT91_SDRAMC_NB_4 \| \
	258	AT91_SDRAMC_CAS_3 \| \
	259	AT91_SDRAMC_DBW_32 \| \
	260	(2 << 8) \| /* Write Recovery Delay */ \
	261	(7 << 12) \| /* Row Cycle Delay */ \
	262	(2 << 16) \| /* Row Precharge Delay */ \
	263	(2 << 20) \| /* Row to Column Delay */ \
264	(5 << 24) \| /* Active to Precharge Delay */ \
265	(8 << 28)) /* Exit Self Refresh to Active Delay */
266
267	#define CONFIG_SYS_SDRC_MDR_VAL AT91_SDRAMC_MD_SDRAM
268	#define CONFIG_SYS_SDRC_MR_VAL2 AT91_SDRAMC_MODE_PRECHARGE
269	#define CONFIG_SYS_SDRAM_VAL1 0 /* SDRAM_BASE */
270	#define CONFIG_SYS_SDRC_MR_VAL3 AT91_SDRAMC_MODE_REFRESH
271	#define CONFIG_SYS_SDRAM_VAL2 0 /* SDRAM_BASE */
272	#define CONFIG_SYS_SDRAM_VAL3 0 /* SDRAM_BASE */
273	#define CONFIG_SYS_SDRAM_VAL4 0 /* SDRAM_BASE */
274	#define CONFIG_SYS_SDRAM_VAL5 0 /* SDRAM_BASE */
275	#define CONFIG_SYS_SDRAM_VAL6 0 /* SDRAM_BASE */
276	#define CONFIG_SYS_SDRAM_VAL7 0 /* SDRAM_BASE */
277	#define CONFIG_SYS_SDRAM_VAL8 0 /* SDRAM_BASE */
278	#define CONFIG_SYS_SDRAM_VAL9 0 /* SDRAM_BASE */
279	#define CONFIG_SYS_SDRC_MR_VAL4 AT91_SDRAMC_MODE_LMR
280	#define CONFIG_SYS_SDRAM_VAL10 0 /* SDRAM_BASE */
281	#define CONFIG_SYS_SDRC_MR_VAL5 AT91_SDRAMC_MODE_NORMAL
282	#define CONFIG_SYS_SDRAM_VAL11 0 /* SDRAM_BASE */
283	#define CONFIG_SYS_SDRC_TR_VAL2 1200 /* SDRAM_TR */
284	#define CONFIG_SYS_SDRAM_VAL12 0 /* SDRAM_BASE */
285
286	/* NOR flash */
287
288	#define CONFIG_FLASH_SHOW_PROGRESS 45
289	#define CONFIG_SYS_FLASH_CFI
290	#define CONFIG_FLASH_CFI_DRIVER
291	#define PHYS_FLASH_1 0x10000000
292	#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1
293	#define CONFIG_SYS_MAX_FLASH_SECT 256
294	#define CONFIG_SYS_MAX_FLASH_BANKS 1
295
296	#define CONFIG_ENV_IS_IN_FLASH
297	#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x00060000)
298
299	/* setup SMC0, CS0 (NOR Flash) - 16-bit, 15 WS */
300	#define CONFIG_SYS_SMC0_SETUP0_VAL \
301	(AT91_SMC_SETUP_NWE(10) \| AT91_SMC_SETUP_NCS_WR(10) \| \
302	AT91_SMC_SETUP_NRD(10) \| AT91_SMC_SETUP_NCS_RD(10))
303	#define CONFIG_SYS_SMC0_PULSE0_VAL \
304	(AT91_SMC_PULSE_NWE(11) \| AT91_SMC_PULSE_NCS_WR(11) \| \
305	AT91_SMC_PULSE_NRD(11) \| AT91_SMC_PULSE_NCS_RD(11))
306	#define CONFIG_SYS_SMC0_CYCLE0_VAL \
307	(AT91_SMC_CYCLE_NWE(22) \| AT91_SMC_CYCLE_NRD(22))
308	#define CONFIG_SYS_SMC0_MODE0_VAL \
309	(AT91_SMC_MODE_RM_NRD \| AT91_SMC_MODE_WM_NWE \| \
310	AT91_SMC_MODE_DBW_16 \| \
311	AT91_SMC_MODE_TDF \| AT91_SMC_MODE_TDF_CYCLE(6))
312
313	/* NAND flash */
314	#ifdef CONFIG_CMD_NAND
315	#define CONFIG_NAND_ATMEL
316	#define CONFIG_SYS_MAX_NAND_DEVICE 1
317	#define CONFIG_SYS_NAND_BASE 0x40000000
318	#define CONFIG_SYS_NAND_DBW_8 1
319	#define CONFIG_SYS_NAND_MASK_ALE (1 << 21) /* our ALE is AD21 */
320	#define CONFIG_SYS_NAND_MASK_CLE (1 << 22) /* our CLE is AD22 */
ac45bb16 AB	321	#define CONFIG_SYS_NAND_ENABLE_PIN GPIO_PIN_PD(15)
ac45bb16 AB	322	#define CONFIG_SYS_NAND_READY_PIN GPIO_PIN_PB(0)
4324c75f	323	#endif
	324
	325	/* Ethernet */
	326	#define CONFIG_MACB
	327	#define CONFIG_RMII
4324c75f	328	#define CONFIG_NET_RETRY_COUNT 5
4535a24c	329	#define CONFIG_AT91_WANTS_COMMON_PHY
4324c75f	330
	331	#define CONFIG_OVERWRITE_ETHADDR_ONCE
	332
	333	#define CONFIG_SYS_LOAD_ADDR 0x21000000 /* default load address */
	334
	335	#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE
	336	#define CONFIG_SYS_MEMTEST_END 0x21e00000
	337
	338	/* Address and size of Primary Environment Sector */
	339	#ifdef CONFIG_ENV_IS_IN_FLASH
	340	#define CONFIG_ENV_SIZE 0x20000
	341	#else
	342	#define CONFIG_ENV_SIZE 0x2000
	343	#endif
	344
	345	#define CONFIG_BAUDRATE 115200
	346	#define CONFIG_SYS_BAUDRATE_TABLE {312500, 230400, 115200, 19200, \
	347	38400, 57600, 9600 }
	348
	349	#define CONFIG_SYS_PROMPT "U-Boot> "
	350	#define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */
	351	#define CONFIG_SYS_MAXARGS 32 /* max number of command args */
	352	#define CONFIG_SYS_PBSIZE \
	353	(CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
	354	#define CONFIG_CMDLINE_EDITING
	355	#define CONFIG_AUTO_COMPLETE
	356
	357	/*
	358	* Size of malloc() pool
	359	*/
	360	#define CONFIG_SYS_MALLOC_LEN \
	361	ROUND(3 * CONFIG_ENV_SIZE + 128 * 1024, 0x1000)
4324c75f	362
4324c75f	363	#ifndef CONFIG_RAMLOAD
	364	#define CONFIG_BOOTCOMMAND "run nfsboot"
	365	#endif
	366	#define CONFIG_BOOT_RETRY_TIME -1
	367	#define CONFIG_BOOT_RETRY_MIN 15
	368
	369	#define CONFIG_NFSBOOTCOMMAND \
	370	"dhcp $(copy_addr) $(kernelname);" \
	371	"run bootargsdefaults;" \
	372	"set bootargs $(bootargs) boot=nfs " \
	373	";echo $(bootargs)" \
	374	";bootm"
	375
	376	#define CONFIG_EXTRA_ENV_SETTINGS \
	377	"ubootaddr=10000000\0" \
	378	"splashimage=10080000\0" \
	379	"kerneladdr=100A0000\0" \
	380	"kernelsize=00800000\0" \
	381	"minifsaddr=108A0000\0" \
	382	"minifssize=00060000\0" \
	383	"rootfsaddr=10900000\0" \
	384	"copy_addr=20200000\0" \
	385	"rootfssize=01700000\0" \
	386	"kernelname=uImage_vl_ma2sc\0" \
	387	"bootargsdefaults=set bootargs " \
	388	"console=ttyS0,115200 " \
	389	"video=atmel_lcdfb " \
	390	"mem=62M " \
	391	"panic=10 " \
	392	"boardrevison=\\\"${revision}\\\" " \
	393	"uboot=\\\"${ver}\\\" " \
	394	"\0" \
	395	"update_all=run update_kernel;run update_root;" \
	396	"run update_splash; run update_uboot\0" \
	397	"update_kernel=protect off $(kerneladdr) +$(kernelsize);" \
	398	"dhcp $(copy_addr) $(kernelname);" \
	399	"erase $(kerneladdr) +$(kernelsize);" \
	400	"cp.b $(fileaddr) $(kerneladdr) $(filesize);" \
	401	"protect on $(kerneladdr) +$(kernelsize)" \
	402	"\0" \
	403	"update_root=protect off $(rootfsaddr) +$(rootfssize);" \
	404	"dhcp $(copy_addr) vl_ma2sc.root;" \
	405	"erase $(rootfsaddr) +$(rootfssize);" \
	406	"cp.b $(fileaddr) $(rootfsaddr) $(filesize);" \
	407	"\0" \
	408	"update_splash=protect off $(splashimage) +20000;" \
	409	"dhcp $(copy_addr) splash_vl_ma2sc.bmp;" \
	410	"erase $(splashimage) +20000;" \
	411	"cp.b $(fileaddr) 10080000 $(filesize);" \
	412	"protect on $(splashimage) +20000\0" \
	413	"update_uboot=protect off 10000000 1005FFFF;" \
	414	"dhcp $(copy_addr) u-boot_vl_ma2sc;" \
	415	"erase 10000000 1005FFFF;" \
	416	"cp.b $(fileaddr) $(ubootaddr) $(filesize);" \
	417	"protect on 10000000 1005FFFF;reset\0" \
	418	"emergency=run bootargsdefaults;" \
	419	"set bootargs $(bootargs) root=initramfs boot=emergency " \
	420	";bootm $(kerneladdr)\0" \
	421	"netemergency=run bootargsdefaults;" \
	422	"dhcp $(copy_addr) $(kernelname);" \
	423	"set bootargs $(bootargs) root=initramfs boot=emergency " \
	424	";bootm $(copy_addr)\0" \
	425	"norboot=run bootargsdefaults;" \
	426	"set bootargs $(bootargs) root=initramfs boot=local quiet " \
427	";bootm $(kerneladdr)\0" \
428	"nandboot=run bootargsdefaults;" \
429	"set bootargs $(bootargs) root=initramfs boot=nand " \
430	";bootm $(kerneladdr)\0" \
431	"setnorboot=set bootcmd 'run norboot'; set bootdelay 1;save\0" \
432	"clearenv=protect off 10060000 1007FFFF;" \
433	"erase 10060000 1007FFFF;reset\0" \
434	" "
435
4324c75f	436	#endif