[people/ms/u-boot.git] / include / configs / voiceblue.h

/*
 * (C) Copyright 2005 2N TELEKOMUNIKACE, Ladislav Michl
 *
 * Configuation settings for the TI OMAP VoiceBlue board.
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License
 * version 2 as published by the Free Software Foundation.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */

#ifndef __CONFIG_H
#define __CONFIG_H

#include <configs/omap1510.h>

#define CONFIG_ARM925T	1		/* This is an arm925t CPU */
#define CONFIG_OMAP	1		/* in a TI OMAP core */
#define CONFIG_OMAP1510 1		/* which is in a 5910 */

/* Input clock of PLL */
#define CONFIG_SYS_CLK_FREQ		150000000	/* 150MHz */
#define CONFIG_XTAL_FREQ		12000000	/*  12MHz */

#undef CONFIG_USE_IRQ			/* we don't need IRQ/FIQ stuff */

#define CONFIG_MISC_INIT_R		/* There is nothing to really init */
#define BOARD_LATE_INIT			/* but we flash the LEDs here */

#define CONFIG_CMDLINE_TAG		1	/* enable passing of ATAGs */
#define CONFIG_SETUP_MEMORY_TAGS	1
#define CONFIG_INITRD_TAG		1

#define CONFIG_VERSION_VARIABLE	1       /* include version env variable */

/*
 * Physical Memory Map
 */
#define CONFIG_NR_DRAM_BANKS		1
#define PHYS_SDRAM_1			0x10000000
#define PHYS_SDRAM_1_SIZE		(64 * 1024 * 1024)
#define PHYS_FLASH_1			0x0000000

#define CONFIG_SYS_MONITOR_BASE		PHYS_FLASH_1
#define CONFIG_SYS_MONITOR_LEN		(256 * 1024)

/*
 * Environment settings
 */
#define CONFIG_ENV_IS_IN_FLASH
#define CONFIG_ENV_ADDR			(PHYS_FLASH_1 + CONFIG_SYS_MONITOR_LEN)
#define CONFIG_ENV_SIZE			(8 * 1024)
#define CONFIG_ENV_SECT_SIZE		(64 * 1024)
#define CONFIG_ENV_ADDR_REDUND		(CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE)
#define CONFIG_ENV_SIZE_REDUND		CONFIG_ENV_SIZE

#define CONFIG_ENV_OVERWRITE

/*
 * Size of malloc() pool and stack
 */
#define CONFIG_SYS_MALLOC_LEN		(4 * 1024 * 1024)
#define CONFIG_STACKSIZE		(1 * 1024 * 1024)

/*
 * Hardware drivers
 */
#define CONFIG_SYS_NS16550
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE	(-4)
#define CONFIG_SYS_NS16550_CLK		(CONFIG_XTAL_FREQ)
#define CONFIG_SYS_NS16550_COM1		OMAP1510_UART1_BASE

#define CONFIG_NET_MULTI
#define CONFIG_SMC91111
#define CONFIG_SMC91111_BASE		0x08000300

#define CONFIG_SYS_FLASH_BASE		PHYS_FLASH_1
#define CONFIG_SYS_MAX_FLASH_BANKS	1
#define CONFIG_SYS_MAX_FLASH_SECT	512

#define CONFIG_SYS_FLASH_CFI
#define CONFIG_FLASH_CFI_DRIVER
#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE

#define CONFIG_HARD_I2C
#define CONFIG_SYS_I2C_SPEED		100000
#define CONFIG_SYS_I2C_SLAVE		1
#define CONFIG_DRIVER_OMAP1510_I2C

#define CONFIG_RTC_DS1307
#define CONFIG_SYS_I2C_RTC_ADDR		0x68


#define CONFIG_CONS_INDEX		1
#define CONFIG_BAUDRATE			115200
#define CONFIG_SYS_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }


/*
 * Command line configuration
 */
#include <config_cmd_default.h>

#define CONFIG_CMD_BDI
#define CONFIG_CMD_BOOTD
#define CONFIG_CMD_DHCP
#define CONFIG_CMD_SAVEENV
#define CONFIG_CMD_FLASH
#define CONFIG_CMD_IMI
#define CONFIG_CMD_JFFS2
#define CONFIG_CMD_LOADB
#define CONFIG_CMD_MEMORY
#define CONFIG_CMD_NET
#define CONFIG_CMD_PING
#define CONFIG_CMD_RUN

/*
 * BOOTP options
 */
#define CONFIG_BOOTP_SUBNETMASK
#define CONFIG_BOOTP_GATEWAY
#define CONFIG_BOOTP_HOSTNAME
#define CONFIG_BOOTP_BOOTPATH

#define CONFIG_LOOPW

#define CONFIG_BOOTDELAY	3
#define CONFIG_ZERO_BOOTDELAY_CHECK	/* allow to break in always */
#undef  CONFIG_BOOTARGS			/* the boot command will set bootargs*/
#define CONFIG_SYS_AUTOLOAD		"n"
#define CONFIG_BOOTCOMMAND	"run nboot"
#define CONFIG_PREBOOT		"run setup"
#define	CONFIG_EXTRA_ENV_SETTINGS					\
	"silent=1\0"							\
	"ospart=0\0"							\
	"bootfile=/boot/uImage\0"					\
	"setpart="							\
	"if test -n $swapos; then "					\
		"setenv swapos; saveenv; "				\
		"if test $ospart -eq 0; then "				\
			"setenv ospart 1; "				\
		"else "							\
			"setenv ospart 0; "				\
		"fi; "							\
	"fi\0"								\
	"setup=setenv bootargs console=ttyS0,$baudrate "		\
		"mtdparts=$mtdparts\0"					\
	"nfsargs=setenv bootargs $bootargs "				\
		"ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname::off " \
		"nfsroot=$rootpath root=/dev/nfs\0"			\
	"flashargs=run setpart; setenv bootargs $bootargs "		\
		"root=mtd:data$ospart ro "				\
		"rootfstype=jffs2\0"					\
	"initrdargs=setenv bootargs $bootargs "				\
		"ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname::off\0" \
	"fboot=run flashargs; chpart data$ospart; fsload; bootm\0"	\
	"mboot=bootp; run initrdargs; tftp; bootm\0"			\
	"nboot=bootp; run nfsargs; tftp; bootm\0"

#define CONFIG_SILENT_CONSOLE		1	/* enable silent startup */

#if 1	/* feel free to disable for development */
#define CONFIG_AUTOBOOT_KEYED		/* Enable password protection	*/
#define CONFIG_AUTOBOOT_PROMPT	"\nVoiceBlue Enterprise - booting...\n"
#define CONFIG_AUTOBOOT_DELAY_STR	"."	/* 1st "password"	*/
#endif

/*
 * Partitions (mtdparts command line support)
 */
#define CONFIG_CMD_MTDPARTS
#define CONFIG_MTD_DEVICE		/* needed for mtdparts commands */
#define CONFIG_FLASH_CFI_MTD
#define MTDIDS_DEFAULT		"nor0=physmap-flash.0"
#define MTDPARTS_DEFAULT	"mtdparts=physmap-flash.0:" \
	"256k(u-boot),64k(env),64k(r_env),16192k(data0),-(data1)"

/*
 * Miscellaneous configurable options
 */
#define CONFIG_SYS_HUSH_PARSER
#define CONFIG_SYS_PROMPT_HUSH_PS2	"> "
#define CONFIG_AUTO_COMPLETE
#define CONFIG_SYS_LONGHELP
#define CONFIG_SYS_PROMPT		"# "
#define CONFIG_SYS_CBSIZE		256
#define CONFIG_SYS_PBSIZE		(CONFIG_SYS_CBSIZE + \
					 sizeof(CONFIG_SYS_PROMPT) + 16)
#define CONFIG_SYS_MAXARGS		16
#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE

#define CONFIG_SYS_MEMTEST_START	(PHYS_SDRAM_1)
#define CONFIG_SYS_MEMTEST_END		(PHYS_SDRAM_1 + PHYS_SDRAM_1_SIZE - \
	(CONFIG_SYS_MONITOR_LEN + CONFIG_SYS_MALLOC_LEN + CONFIG_STACKSIZE))
#define CONFIG_SYS_LOAD_ADDR		(PHYS_SDRAM_1 + 0x400000)

/*
 * The 1510 has 3 timers, they can be driven by the RefClk (12MHz) or by DPLL1.
 * This time is further subdivided by a local divisor.
 */
#define CONFIG_SYS_TIMERBASE		OMAP1510_TIMER1_BASE
#define CONFIG_SYS_PTV			7	/* 2^(PTV+1), divide by 256 */
#define CONFIG_SYS_HZ			1000

#define OMAP5910_DPLL_DIV		1
#define OMAP5910_DPLL_MUL		\
	((CONFIG_SYS_CLK_FREQ * (1 << OMAP5910_DPLL_DIV)) / CONFIG_XTAL_FREQ)

#define OMAP5910_ARM_PER_DIV	2	/* CKL/4 */
#define OMAP5910_LCD_DIV	2	/* CKL/4 */
#define OMAP5910_ARM_DIV	0	/* CKL/1 */
#define OMAP5910_DSP_DIV	0	/* CKL/1 */
#define OMAP5910_TC_DIV		1	/* CKL/2 */
#define OMAP5910_DSP_MMU_DIV	1	/* CKL/2 */
#define OMAP5910_ARM_TIM_SEL	1	/* CKL used for MPU timers */

#define OMAP5910_ARM_EN_CLK	0x03d6	/* 0000 0011 1101 0110b  Clock Enable */
#define OMAP5910_ARM_CKCTL	((OMAP5910_ARM_PER_DIV)  |	\
				 (OMAP5910_LCD_DIV << 2) |	\
				 (OMAP5910_ARM_DIV << 4) |	\
				 (OMAP5910_DSP_DIV << 6) |	\
				 (OMAP5910_TC_DIV << 8) |	\
				 (OMAP5910_DSP_MMU_DIV << 10) |	\
				 (OMAP5910_ARM_TIM_SEL << 12))

#define VOICEBLUE_LED_REG	0x04030000

#endif	/* __CONFIG_H */
Commit	Line	Data
3c2b3d45 WD	1	/*
	2	* (C) Copyright 2005 2N TELEKOMUNIKACE, Ladislav Michl
	3	*
	4	* Configuation settings for the TI OMAP VoiceBlue board.
	5	*
	6	* See file CREDITS for list of people who contributed to this
	7	* project.
	8	*
	9	* This program is free software; you can redistribute it and/or
	10	* modify it under the terms of the GNU General Public License
	11	* version 2 as published by the Free Software Foundation.
	12	*
	13	* This program is distributed in the hope that it will be useful,
	14	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	15	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	16	* GNU General Public License for more details.
	17	*
	18	* You should have received a copy of the GNU General Public License
	19	* along with this program; if not, write to the Free Software
	20	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	21	* MA 02111-1307 USA
	22	*/
	23
	24	#ifndef __CONFIG_H
	25	#define __CONFIG_H
	26
	27	#include <configs/omap1510.h>
	28
3c2b3d45 WD	29	#define CONFIG_ARM925T 1 /* This is an arm925t CPU */
	30	#define CONFIG_OMAP 1 /* in a TI OMAP core */
	31	#define CONFIG_OMAP1510 1 /* which is in a 5910 */
	32
	33	/* Input clock of PLL */
a32c1e0e LM	34	#define CONFIG_SYS_CLK_FREQ 150000000 /* 150MHz */
a32c1e0e LM	35	#define CONFIG_XTAL_FREQ 12000000 /* 12MHz */
3c2b3d45 WD	36
	37	#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */
	38
	39	#define CONFIG_MISC_INIT_R /* There is nothing to really init */
	40	#define BOARD_LATE_INIT /* but we flash the LEDs here */
	41
	42	#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */
	43	#define CONFIG_SETUP_MEMORY_TAGS 1
	44	#define CONFIG_INITRD_TAG 1
	45
cb0fdf3c HS	46	#define CONFIG_VERSION_VARIABLE 1 /* include version env variable */
cb0fdf3c HS	47
3c2b3d45 WD	48	/*
	49	* Physical Memory Map
	50	*/
a32c1e0e LM	51	#define CONFIG_NR_DRAM_BANKS 1
	52	#define PHYS_SDRAM_1 0x10000000
	53	#define PHYS_SDRAM_1_SIZE (64 * 1024 * 1024)
	54	#define PHYS_FLASH_1 0x0000000
3c2b3d45	55
a32c1e0e	56	#define CONFIG_SYS_MONITOR_BASE PHYS_FLASH_1
6d0f6bcf	57	#define CONFIG_SYS_MONITOR_LEN (256 * 1024)
3c2b3d45 WD	58
	59	/*
	60	* Environment settings
	61	*/
5a1aceb0	62	#define CONFIG_ENV_IS_IN_FLASH
a32c1e0e LM	63	#define CONFIG_ENV_ADDR (PHYS_FLASH_1 + CONFIG_SYS_MONITOR_LEN)
	64	#define CONFIG_ENV_SIZE (8 * 1024)
	65	#define CONFIG_ENV_SECT_SIZE (64 * 1024)
	66	#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE)
	67	#define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE
3c2b3d45 WD	68
	69	#define CONFIG_ENV_OVERWRITE
	70
3c2b3d45	71	/*
b77fad3b	72	* Size of malloc() pool and stack
3c2b3d45	73	*/
6d0f6bcf	74	#define CONFIG_SYS_MALLOC_LEN (4 * 1024 * 1024)
a32c1e0e	75	#define CONFIG_STACKSIZE (1 * 1024 * 1024)
3c2b3d45	76
3c2b3d45 WD	77	/*
	78	* Hardware drivers
	79	*/
a32c1e0e LM	80	#define CONFIG_SYS_NS16550
	81	#define CONFIG_SYS_NS16550_SERIAL
	82	#define CONFIG_SYS_NS16550_REG_SIZE (-4)
	83	#define CONFIG_SYS_NS16550_CLK (CONFIG_XTAL_FREQ)
	84	#define CONFIG_SYS_NS16550_COM1 OMAP1510_UART1_BASE
	85
7194ab80 BW	86	#define CONFIG_NET_MULTI
7194ab80 BW	87	#define CONFIG_SMC91111
a32c1e0e LM	88	#define CONFIG_SMC91111_BASE 0x08000300
	89
	90	#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1
	91	#define CONFIG_SYS_MAX_FLASH_BANKS 1
	92	#define CONFIG_SYS_MAX_FLASH_SECT 512
	93
	94	#define CONFIG_SYS_FLASH_CFI
	95	#define CONFIG_FLASH_CFI_DRIVER
	96	#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
3c2b3d45	97
4fedfddf	98	#define CONFIG_HARD_I2C
6d0f6bcf JCPV	99	#define CONFIG_SYS_I2C_SPEED 100000
6d0f6bcf JCPV	100	#define CONFIG_SYS_I2C_SLAVE 1
4fedfddf LM	101	#define CONFIG_DRIVER_OMAP1510_I2C
	102
	103	#define CONFIG_RTC_DS1307
a32c1e0e	104	#define CONFIG_SYS_I2C_RTC_ADDR 0x68
4fedfddf	105
3c2b3d45	106
a32c1e0e LM	107	#define CONFIG_CONS_INDEX 1
a32c1e0e LM	108	#define CONFIG_BAUDRATE 115200
6d0f6bcf	109	#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
3c2b3d45	110
dca3b3d6 JL	111
dca3b3d6 JL	112	/*
a32c1e0e	113	* Command line configuration
dca3b3d6 JL	114	*/
	115	#include <config_cmd_default.h>
	116
	117	#define CONFIG_CMD_BDI
4fedfddf LM	118	#define CONFIG_CMD_BOOTD
4fedfddf LM	119	#define CONFIG_CMD_DHCP
bdab39d3	120	#define CONFIG_CMD_SAVEENV
dca3b3d6	121	#define CONFIG_CMD_FLASH
4fedfddf LM	122	#define CONFIG_CMD_IMI
	123	#define CONFIG_CMD_JFFS2
	124	#define CONFIG_CMD_LOADB
dca3b3d6 JL	125	#define CONFIG_CMD_MEMORY
dca3b3d6 JL	126	#define CONFIG_CMD_NET
dca3b3d6 JL	127	#define CONFIG_CMD_PING
	128	#define CONFIG_CMD_RUN
	129
d3b8c1a7 JL	130	/*
	131	* BOOTP options
	132	*/
	133	#define CONFIG_BOOTP_SUBNETMASK
	134	#define CONFIG_BOOTP_GATEWAY
	135	#define CONFIG_BOOTP_HOSTNAME
	136	#define CONFIG_BOOTP_BOOTPATH
	137
3c2b3d45 WD	138	#define CONFIG_LOOPW
3c2b3d45 WD	139
3c2b3d45	140	#define CONFIG_BOOTDELAY 3
4fedfddf	141	#define CONFIG_ZERO_BOOTDELAY_CHECK /* allow to break in always */
a32c1e0e LM	142	#undef CONFIG_BOOTARGS /* the boot command will set bootargs*/
a32c1e0e LM	143	#define CONFIG_SYS_AUTOLOAD "n"
3c2b3d45 WD	144	#define CONFIG_BOOTCOMMAND "run nboot"
3c2b3d45 WD	145	#define CONFIG_PREBOOT "run setup"
a32c1e0e LM	146	#define CONFIG_EXTRA_ENV_SETTINGS \
	147	"silent=1\0" \
	148	"ospart=0\0" \
	149	"bootfile=/boot/uImage\0" \
	150	"setpart=" \
	151	"if test -n $swapos; then " \
	152	"setenv swapos; saveenv; " \
	153	"if test $ospart -eq 0; then " \
	154	"setenv ospart 1; " \
	155	"else " \
	156	"setenv ospart 0; " \
	157	"fi; " \
	158	"fi\0" \
	159	"setup=setenv bootargs console=ttyS0,$baudrate " \
	160	"mtdparts=$mtdparts\0" \
	161	"nfsargs=setenv bootargs $bootargs " \
cb0fdf3c	162	"ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname::off " \
a32c1e0e LM	163	"nfsroot=$rootpath root=/dev/nfs\0" \
	164	"flashargs=run setpart; setenv bootargs $bootargs " \
	165	"root=mtd:data$ospart ro " \
	166	"rootfstype=jffs2\0" \
	167	"initrdargs=setenv bootargs $bootargs " \
cb0fdf3c	168	"ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname::off\0" \
a32c1e0e LM	169	"fboot=run flashargs; chpart data$ospart; fsload; bootm\0" \
a32c1e0e LM	170	"mboot=bootp; run initrdargs; tftp; bootm\0" \
cb0fdf3c	171	"nboot=bootp; run nfsargs; tftp; bootm\0"
3c2b3d45	172
cb0fdf3c HS	173	#define CONFIG_SILENT_CONSOLE 1 /* enable silent startup */
	174
	175	#if 1 /* feel free to disable for development */
	176	#define CONFIG_AUTOBOOT_KEYED /* Enable password protection */
	177	#define CONFIG_AUTOBOOT_PROMPT "\nVoiceBlue Enterprise - booting...\n"
	178	#define CONFIG_AUTOBOOT_DELAY_STR "." /* 1st "password" */
	179	#endif
	180
	181	/*
a32c1e0e	182	* Partitions (mtdparts command line support)
cb0fdf3c	183	*/
68d7d651	184	#define CONFIG_CMD_MTDPARTS
942556a9 SR	185	#define CONFIG_MTD_DEVICE /* needed for mtdparts commands */
942556a9 SR	186	#define CONFIG_FLASH_CFI_MTD
a32c1e0e LM	187	#define MTDIDS_DEFAULT "nor0=physmap-flash.0"
	188	#define MTDPARTS_DEFAULT "mtdparts=physmap-flash.0:" \
	189	"256k(u-boot),64k(env),64k(r_env),16192k(data0),-(data1)"
3c2b3d45 WD	190
	191	/*
	192	* Miscellaneous configurable options
	193	*/
6d0f6bcf JCPV	194	#define CONFIG_SYS_HUSH_PARSER
6d0f6bcf JCPV	195	#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
3c2b3d45	196	#define CONFIG_AUTO_COMPLETE
a32c1e0e LM	197	#define CONFIG_SYS_LONGHELP
	198	#define CONFIG_SYS_PROMPT "# "
	199	#define CONFIG_SYS_CBSIZE 256
	200	#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
	201	sizeof(CONFIG_SYS_PROMPT) + 16)
	202	#define CONFIG_SYS_MAXARGS 16
	203	#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
	204
	205	#define CONFIG_SYS_MEMTEST_START (PHYS_SDRAM_1)
	206	#define CONFIG_SYS_MEMTEST_END (PHYS_SDRAM_1 + PHYS_SDRAM_1_SIZE - \
	207	(CONFIG_SYS_MONITOR_LEN + CONFIG_SYS_MALLOC_LEN + CONFIG_STACKSIZE))
	208	#define CONFIG_SYS_LOAD_ADDR (PHYS_SDRAM_1 + 0x400000)
3c2b3d45	209
a32c1e0e LM	210	/*
a32c1e0e LM	211	* The 1510 has 3 timers, they can be driven by the RefClk (12MHz) or by DPLL1.
3c2b3d45 WD	212	* This time is further subdivided by a local divisor.
3c2b3d45 WD	213	*/
a32c1e0e LM	214	#define CONFIG_SYS_TIMERBASE OMAP1510_TIMER1_BASE
	215	#define CONFIG_SYS_PTV 7 /* 2^(PTV+1), divide by 256 */
	216	#define CONFIG_SYS_HZ 1000
3c2b3d45	217
a32c1e0e LM	218	#define OMAP5910_DPLL_DIV 1
	219	#define OMAP5910_DPLL_MUL \
	220	((CONFIG_SYS_CLK_FREQ * (1 << OMAP5910_DPLL_DIV)) / CONFIG_XTAL_FREQ)
3c2b3d45 WD	221
	222	#define OMAP5910_ARM_PER_DIV 2 /* CKL/4 */
	223	#define OMAP5910_LCD_DIV 2 /* CKL/4 */
	224	#define OMAP5910_ARM_DIV 0 /* CKL/1 */
	225	#define OMAP5910_DSP_DIV 0 /* CKL/1 */
	226	#define OMAP5910_TC_DIV 1 /* CKL/2 */
	227	#define OMAP5910_DSP_MMU_DIV 1 /* CKL/2 */
	228	#define OMAP5910_ARM_TIM_SEL 1 /* CKL used for MPU timers */
	229
	230	#define OMAP5910_ARM_EN_CLK 0x03d6 /* 0000 0011 1101 0110b Clock Enable */
	231	#define OMAP5910_ARM_CKCTL ((OMAP5910_ARM_PER_DIV) \| \
	232	(OMAP5910_LCD_DIV << 2) \| \
	233	(OMAP5910_ARM_DIV << 4) \| \
	234	(OMAP5910_DSP_DIV << 6) \| \
	235	(OMAP5910_TC_DIV << 8) \| \
	236	(OMAP5910_DSP_MMU_DIV << 10) \| \
	237	(OMAP5910_ARM_TIM_SEL << 12))
	238
	239	#define VOICEBLUE_LED_REG 0x04030000
	240
	241	#endif /* __CONFIG_H */