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3c2b3d45 WD |
1 | /* |
2 | * (C) Copyright 2005 2N TELEKOMUNIKACE, Ladislav Michl | |
3 | * | |
4 | * Configuation settings for the TI OMAP VoiceBlue board. | |
5 | * | |
6 | * See file CREDITS for list of people who contributed to this | |
7 | * project. | |
8 | * | |
9 | * This program is free software; you can redistribute it and/or | |
10 | * modify it under the terms of the GNU General Public License | |
11 | * version 2 as published by the Free Software Foundation. | |
12 | * | |
13 | * This program is distributed in the hope that it will be useful, | |
14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | * GNU General Public License for more details. | |
17 | * | |
18 | * You should have received a copy of the GNU General Public License | |
19 | * along with this program; if not, write to the Free Software | |
20 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | |
21 | * MA 02111-1307 USA | |
22 | */ | |
23 | ||
24 | #ifndef __CONFIG_H | |
25 | #define __CONFIG_H | |
26 | ||
27 | #include <configs/omap1510.h> | |
28 | ||
3c2b3d45 WD |
29 | #define CONFIG_ARM925T 1 /* This is an arm925t CPU */ |
30 | #define CONFIG_OMAP 1 /* in a TI OMAP core */ | |
31 | #define CONFIG_OMAP1510 1 /* which is in a 5910 */ | |
32 | ||
33 | /* Input clock of PLL */ | |
34 | #define CONFIG_SYS_CLK_FREQ 150000000 /* 150MHz input clock */ | |
35 | #define CONFIG_XTAL_FREQ 12000000 | |
36 | ||
37 | #undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */ | |
38 | ||
39 | #define CONFIG_MISC_INIT_R /* There is nothing to really init */ | |
40 | #define BOARD_LATE_INIT /* but we flash the LEDs here */ | |
41 | ||
42 | #define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ | |
43 | #define CONFIG_SETUP_MEMORY_TAGS 1 | |
44 | #define CONFIG_INITRD_TAG 1 | |
45 | ||
cb0fdf3c HS |
46 | #define CONFIG_VERSION_VARIABLE 1 /* include version env variable */ |
47 | ||
3c2b3d45 WD |
48 | /* |
49 | * Physical Memory Map | |
50 | */ | |
51 | #define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */ | |
52 | #define PHYS_SDRAM_1 0x10000000 /* SDRAM Bank #1 */ | |
4fedfddf | 53 | #define PHYS_SDRAM_1_SIZE (64 * 1024 * 1024) |
3c2b3d45 WD |
54 | |
55 | #define PHYS_FLASH_1 0x00000000 /* Flash Bank #1 */ | |
3c2b3d45 | 56 | |
6d0f6bcf | 57 | #define CONFIG_SYS_LOAD_ADDR PHYS_SDRAM_1 + 0x400000 /* default load address */ |
3c2b3d45 WD |
58 | |
59 | /* | |
60 | * FLASH organization | |
61 | */ | |
6d0f6bcf | 62 | #define CONFIG_SYS_FLASH_CFI /* Flash is CFI conformant */ |
00b1883a | 63 | #define CONFIG_FLASH_CFI_DRIVER /* Use the common driver */ |
6d0f6bcf JCPV |
64 | #define CONFIG_SYS_MAX_FLASH_BANKS 1 |
65 | #define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1 | |
3c2b3d45 WD |
66 | |
67 | /* FIXME: Does not work on AMD flash */ | |
6d0f6bcf JCPV |
68 | /* #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 */ /* use buffered writes (20x faster) */ |
69 | #define CONFIG_SYS_MAX_FLASH_SECT 512 /* max # of sectors on one chip */ | |
3c2b3d45 | 70 | |
6d0f6bcf JCPV |
71 | #define CONFIG_SYS_MONITOR_BASE PHYS_FLASH_1 |
72 | #define CONFIG_SYS_MONITOR_LEN (256 * 1024) | |
3c2b3d45 WD |
73 | |
74 | /* | |
75 | * Environment settings | |
76 | */ | |
5a1aceb0 | 77 | #define CONFIG_ENV_IS_IN_FLASH |
6d0f6bcf | 78 | #define CONFIG_ENV_ADDR (PHYS_FLASH_1 + CONFIG_SYS_MONITOR_LEN) |
0e8d1586 JCPV |
79 | #define CONFIG_ENV_SIZE (8 * 1024) |
80 | #define CONFIG_ENV_SECT_SIZE (64 * 1024) | |
81 | #define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE) | |
82 | #define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE | |
3c2b3d45 WD |
83 | |
84 | #define CONFIG_ENV_OVERWRITE | |
85 | ||
3c2b3d45 | 86 | /* |
b77fad3b | 87 | * Size of malloc() pool and stack |
3c2b3d45 | 88 | */ |
6d0f6bcf JCPV |
89 | #define CONFIG_SYS_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */ |
90 | #define CONFIG_SYS_MALLOC_LEN (4 * 1024 * 1024) | |
4fedfddf | 91 | #define CONFIG_STACKSIZE (1 * 1024 * 1024) |
6d0f6bcf | 92 | #define PHYS_SDRAM_1_RESERVED (CONFIG_SYS_MONITOR_LEN + CONFIG_SYS_MALLOC_LEN + CONFIG_STACKSIZE) |
3c2b3d45 | 93 | |
3c2b3d45 WD |
94 | /* |
95 | * Hardware drivers | |
96 | */ | |
97 | #define CONFIG_DRIVER_SMC91111 | |
98 | #define CONFIG_SMC91111_BASE 0x08000300 | |
99 | ||
4fedfddf | 100 | #define CONFIG_HARD_I2C |
6d0f6bcf JCPV |
101 | #define CONFIG_SYS_I2C_SPEED 100000 |
102 | #define CONFIG_SYS_I2C_SLAVE 1 | |
4fedfddf LM |
103 | #define CONFIG_DRIVER_OMAP1510_I2C |
104 | ||
105 | #define CONFIG_RTC_DS1307 | |
6d0f6bcf | 106 | #define CONFIG_SYS_I2C_RTC_ADDR 0x68 |
4fedfddf | 107 | |
3c2b3d45 WD |
108 | /* |
109 | * NS16550 Configuration | |
110 | */ | |
6d0f6bcf JCPV |
111 | #define CONFIG_SYS_NS16550 |
112 | #define CONFIG_SYS_NS16550_SERIAL | |
113 | #define CONFIG_SYS_NS16550_REG_SIZE (-4) | |
114 | #define CONFIG_SYS_NS16550_CLK (CONFIG_XTAL_FREQ) /* can be 12M/32Khz or 48Mhz */ | |
115 | #define CONFIG_SYS_NS16550_COM1 OMAP1510_UART1_BASE /* uart1 */ | |
3c2b3d45 WD |
116 | |
117 | #define CONFIG_CONS_INDEX 1 | |
118 | #define CONFIG_BAUDRATE 115200 | |
6d0f6bcf | 119 | #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } |
3c2b3d45 | 120 | |
dca3b3d6 JL |
121 | |
122 | /* | |
123 | * Command line configuration. | |
124 | */ | |
125 | #include <config_cmd_default.h> | |
126 | ||
127 | #define CONFIG_CMD_BDI | |
4fedfddf LM |
128 | #define CONFIG_CMD_BOOTD |
129 | #define CONFIG_CMD_DHCP | |
130 | #define CONFIG_CMD_ENV | |
dca3b3d6 | 131 | #define CONFIG_CMD_FLASH |
4fedfddf LM |
132 | #define CONFIG_CMD_IMI |
133 | #define CONFIG_CMD_JFFS2 | |
134 | #define CONFIG_CMD_LOADB | |
dca3b3d6 JL |
135 | #define CONFIG_CMD_MEMORY |
136 | #define CONFIG_CMD_NET | |
dca3b3d6 JL |
137 | #define CONFIG_CMD_PING |
138 | #define CONFIG_CMD_RUN | |
139 | ||
dca3b3d6 | 140 | |
d3b8c1a7 JL |
141 | /* |
142 | * BOOTP options | |
143 | */ | |
144 | #define CONFIG_BOOTP_SUBNETMASK | |
145 | #define CONFIG_BOOTP_GATEWAY | |
146 | #define CONFIG_BOOTP_HOSTNAME | |
147 | #define CONFIG_BOOTP_BOOTPATH | |
148 | ||
149 | ||
3c2b3d45 WD |
150 | #define CONFIG_LOOPW |
151 | ||
3c2b3d45 | 152 | #define CONFIG_BOOTDELAY 3 |
4fedfddf LM |
153 | #define CONFIG_ZERO_BOOTDELAY_CHECK /* allow to break in always */ |
154 | #undef CONFIG_BOOTARGS /* the boot command will set bootargs*/ | |
6d0f6bcf | 155 | #define CONFIG_SYS_AUTOLOAD "n" /* No autoload */ |
3c2b3d45 WD |
156 | #define CONFIG_BOOTCOMMAND "run nboot" |
157 | #define CONFIG_PREBOOT "run setup" | |
158 | #define CONFIG_EXTRA_ENV_SETTINGS \ | |
cb0fdf3c | 159 | "silent=1\0" \ |
3c2b3d45 | 160 | "ospart=0\0" \ |
4fedfddf | 161 | "bootfile=/boot/uImage\0" \ |
3c2b3d45 | 162 | "setpart=" \ |
4fedfddf LM |
163 | "if test -n $swapos; then " \ |
164 | "setenv swapos; saveenv; " \ | |
165 | "if test $ospart -eq 0; then setenv ospart 1; else setenv ospart 0; fi; "\ | |
3c2b3d45 WD |
166 | "fi\0" \ |
167 | "setup=setenv bootargs console=ttyS0,$baudrate " \ | |
168 | "mtdparts=$mtdparts\0" \ | |
cb0fdf3c HS |
169 | "nfsargs=setenv bootargs $bootargs " \ |
170 | "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname::off " \ | |
171 | "nfsroot=$rootpath root=/dev/nfs\0" \ | |
b77fad3b | 172 | "flashargs=run setpart; setenv bootargs $bootargs " \ |
4fedfddf | 173 | "root=mtd:data$ospart ro " \ |
b77fad3b | 174 | "rootfstype=jffs2\0" \ |
cb0fdf3c HS |
175 | "initrdargs=setenv bootargs $bootargs " \ |
176 | "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname::off\0" \ | |
4fedfddf LM |
177 | "fboot=run flashargs; chpart data$ospart; fsload; bootm\0" \ |
178 | "mboot=bootp; run initrdargs; tftp; bootm\0" \ | |
cb0fdf3c | 179 | "nboot=bootp; run nfsargs; tftp; bootm\0" |
3c2b3d45 | 180 | |
cb0fdf3c HS |
181 | #define CONFIG_SILENT_CONSOLE 1 /* enable silent startup */ |
182 | ||
183 | #if 1 /* feel free to disable for development */ | |
184 | #define CONFIG_AUTOBOOT_KEYED /* Enable password protection */ | |
185 | #define CONFIG_AUTOBOOT_PROMPT "\nVoiceBlue Enterprise - booting...\n" | |
186 | #define CONFIG_AUTOBOOT_DELAY_STR "." /* 1st "password" */ | |
187 | #endif | |
188 | ||
189 | /* | |
190 | * JFFS2 partitions (mtdparts command line support) | |
191 | */ | |
192 | #define CONFIG_JFFS2_CMDLINE | |
193 | #define MTDIDS_DEFAULT "nor0=omapflash.0" | |
4fedfddf | 194 | #define MTDPARTS_DEFAULT "mtdparts=omapflash.0:256k(u-boot),64k(env),64k(r_env),16192k(data0),-(data1)" |
cb0fdf3c | 195 | |
3c2b3d45 WD |
196 | |
197 | /* | |
198 | * Miscellaneous configurable options | |
199 | */ | |
6d0f6bcf JCPV |
200 | #define CONFIG_SYS_HUSH_PARSER |
201 | #define CONFIG_SYS_PROMPT_HUSH_PS2 "> " | |
3c2b3d45 | 202 | #define CONFIG_AUTO_COMPLETE |
6d0f6bcf JCPV |
203 | #define CONFIG_SYS_LONGHELP /* undef to save memory */ |
204 | #define CONFIG_SYS_PROMPT "# " /* Monitor Command Prompt */ | |
205 | #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ | |
206 | #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ | |
207 | #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ | |
208 | #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ | |
3c2b3d45 | 209 | |
6d0f6bcf JCPV |
210 | #define CONFIG_SYS_MEMTEST_START PHYS_SDRAM_1 |
211 | #define CONFIG_SYS_MEMTEST_END PHYS_SDRAM_1 + PHYS_SDRAM_1_SIZE - PHYS_SDRAM_1_RESERVED | |
3c2b3d45 | 212 | |
6d0f6bcf | 213 | #undef CONFIG_SYS_CLKS_IN_HZ /* everything, incl board info, in Hz */ |
3c2b3d45 WD |
214 | |
215 | /* The 1510 has 3 timers, they can be driven by the RefClk (12Mhz) or by DPLL1. | |
216 | * This time is further subdivided by a local divisor. | |
217 | */ | |
6d0f6bcf JCPV |
218 | #define CONFIG_SYS_TIMERBASE OMAP1510_TIMER1_BASE |
219 | #define CONFIG_SYS_PVT 7 /* 2^(pvt+1), divide by 256 */ | |
220 | #define CONFIG_SYS_HZ ((CONFIG_SYS_CLK_FREQ)/(2 << CONFIG_SYS_PVT)) | |
3c2b3d45 WD |
221 | |
222 | #define OMAP5910_DPLL_DIV 1 | |
223 | #define OMAP5910_DPLL_MUL ((CONFIG_SYS_CLK_FREQ * \ | |
224 | (1 << OMAP5910_DPLL_DIV)) / CONFIG_XTAL_FREQ) | |
225 | ||
226 | #define OMAP5910_ARM_PER_DIV 2 /* CKL/4 */ | |
227 | #define OMAP5910_LCD_DIV 2 /* CKL/4 */ | |
228 | #define OMAP5910_ARM_DIV 0 /* CKL/1 */ | |
229 | #define OMAP5910_DSP_DIV 0 /* CKL/1 */ | |
230 | #define OMAP5910_TC_DIV 1 /* CKL/2 */ | |
231 | #define OMAP5910_DSP_MMU_DIV 1 /* CKL/2 */ | |
232 | #define OMAP5910_ARM_TIM_SEL 1 /* CKL used for MPU timers */ | |
233 | ||
234 | #define OMAP5910_ARM_EN_CLK 0x03d6 /* 0000 0011 1101 0110b Clock Enable */ | |
235 | #define OMAP5910_ARM_CKCTL ((OMAP5910_ARM_PER_DIV) | \ | |
236 | (OMAP5910_LCD_DIV << 2) | \ | |
237 | (OMAP5910_ARM_DIV << 4) | \ | |
238 | (OMAP5910_DSP_DIV << 6) | \ | |
239 | (OMAP5910_TC_DIV << 8) | \ | |
240 | (OMAP5910_DSP_MMU_DIV << 10) | \ | |
241 | (OMAP5910_ARM_TIM_SEL << 12)) | |
242 | ||
243 | #define VOICEBLUE_LED_REG 0x04030000 | |
244 | ||
245 | #endif /* __CONFIG_H */ |