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995b72dd SR |
1 | /* |
2 | * (C) Copyright 2009 | |
3 | * Vipin Kumar, STMicroelectronics, <vipin.kumar@st.com> | |
4 | * | |
2fbdbda1 | 5 | * Copyright (C) 2012, 2015 Stefan Roese <sr@denx.de> |
995b72dd | 6 | * |
1a459660 | 7 | * SPDX-License-Identifier: GPL-2.0+ |
995b72dd SR |
8 | */ |
9 | ||
10 | #ifndef __CONFIG_H | |
11 | #define __CONFIG_H | |
12 | ||
13 | /* | |
14 | * High Level Configuration Options | |
15 | * (easy to change) | |
16 | */ | |
17 | #define CONFIG_SPEAR600 /* SPEAr600 SoC */ | |
18 | #define CONFIG_X600 /* on X600 board */ | |
19 | ||
20 | #include <asm/arch/hardware.h> | |
21 | ||
22 | /* Timer, HZ specific defines */ | |
995b72dd SR |
23 | #define CONFIG_SYS_HZ_CLOCK 8300000 |
24 | ||
25 | #define CONFIG_SYS_TEXT_BASE 0x00800040 | |
26 | #define CONFIG_SYS_FLASH_BASE 0xf8000000 | |
27 | /* Reserve 8KiB for SPL */ | |
28 | #define CONFIG_SPL_PAD_TO 8192 /* decimal for 'dd' */ | |
29 | #define CONFIG_SYS_SPL_LEN CONFIG_SPL_PAD_TO | |
30 | #define CONFIG_SYS_UBOOT_BASE (CONFIG_SYS_FLASH_BASE + \ | |
31 | CONFIG_SYS_SPL_LEN) | |
285e266b | 32 | #define CONFIG_SYS_UBOOT_START CONFIG_SYS_TEXT_BASE |
995b72dd SR |
33 | #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE |
34 | #define CONFIG_SYS_MONITOR_LEN 0x60000 | |
35 | ||
995b72dd SR |
36 | /* Serial Configuration (PL011) */ |
37 | #define CONFIG_SYS_SERIAL0 0xD0000000 | |
38 | #define CONFIG_SYS_SERIAL1 0xD0080000 | |
39 | #define CONFIG_PL01x_PORTS { (void *)CONFIG_SYS_SERIAL0, \ | |
40 | (void *)CONFIG_SYS_SERIAL1 } | |
41 | #define CONFIG_PL011_SERIAL | |
42 | #define CONFIG_PL011_CLOCK (48 * 1000 * 1000) | |
43 | #define CONFIG_CONS_INDEX 0 | |
995b72dd SR |
44 | #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, \ |
45 | 57600, 115200 } | |
46 | #define CONFIG_SYS_LOADS_BAUD_CHANGE | |
47 | ||
48 | /* NOR FLASH config options */ | |
49 | #define CONFIG_ST_SMI | |
50 | #define CONFIG_SYS_MAX_FLASH_BANKS 1 | |
51 | #define CONFIG_SYS_FLASH_BANK_SIZE 0x01000000 | |
52 | #define CONFIG_SYS_FLASH_ADDR_BASE { CONFIG_SYS_FLASH_BASE } | |
53 | #define CONFIG_SYS_MAX_FLASH_SECT 128 | |
54 | #define CONFIG_SYS_FLASH_EMPTY_INFO | |
55 | #define CONFIG_SYS_FLASH_ERASE_TOUT (3 * CONFIG_SYS_HZ) | |
56 | #define CONFIG_SYS_FLASH_WRITE_TOUT (3 * CONFIG_SYS_HZ) | |
57 | ||
58 | /* NAND FLASH config options */ | |
59 | #define CONFIG_NAND_FSMC | |
60 | #define CONFIG_SYS_NAND_SELF_INIT | |
61 | #define CONFIG_SYS_MAX_NAND_DEVICE 1 | |
62 | #define CONFIG_SYS_NAND_BASE CONFIG_FSMC_NAND_BASE | |
63 | #define CONFIG_MTD_ECC_SOFT | |
64 | #define CONFIG_SYS_FSMC_NAND_8BIT | |
65 | #define CONFIG_SYS_NAND_ONFI_DETECTION | |
0ddc5a2d SR |
66 | #define CONFIG_NAND_ECC_BCH |
67 | #define CONFIG_BCH | |
995b72dd SR |
68 | |
69 | /* UBI/UBI config options */ | |
70 | #define CONFIG_MTD_DEVICE | |
71 | #define CONFIG_MTD_PARTITIONS | |
995b72dd SR |
72 | |
73 | /* Ethernet config options */ | |
74 | #define CONFIG_MII | |
995b72dd | 75 | #define CONFIG_PHY_RESET_DELAY 10000 /* in usec */ |
995b72dd SR |
76 | #define CONFIG_PHY_ADDR 0 /* PHY address */ |
77 | #define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */ | |
f7c32e8e SR |
78 | #define CONFIG_PHY_MICREL |
79 | #define CONFIG_PHY_MICREL_KSZ9031 | |
995b72dd SR |
80 | |
81 | #define CONFIG_SPEAR_GPIO | |
82 | ||
83 | /* I2C config options */ | |
678398b1 | 84 | #define CONFIG_SYS_I2C |
f93f589c | 85 | #define CONFIG_SYS_I2C_BASE 0xD0200000 |
995b72dd SR |
86 | #define CONFIG_SYS_I2C_SPEED 400000 |
87 | #define CONFIG_SYS_I2C_SLAVE 0x02 | |
88 | #define CONFIG_I2C_CHIPADDRESS 0x50 | |
89 | ||
90 | #define CONFIG_RTC_M41T62 1 | |
91 | #define CONFIG_SYS_I2C_RTC_ADDR 0x68 | |
92 | ||
93 | /* FPGA config options */ | |
94 | #define CONFIG_FPGA | |
95 | #define CONFIG_FPGA_XILINX | |
96 | #define CONFIG_FPGA_SPARTAN3 | |
97 | #define CONFIG_FPGA_COUNT 1 | |
98 | ||
285e266b | 99 | /* USB EHCI options */ |
285e266b | 100 | #define CONFIG_USB_EHCI_SPEAR |
285e266b SR |
101 | #define CONFIG_USB_MAX_CONTROLLER_COUNT 2 |
102 | ||
995b72dd SR |
103 | /* |
104 | * Command support defines | |
105 | */ | |
995b72dd | 106 | #define CONFIG_CMD_SAVES |
995b72dd | 107 | |
285e266b SR |
108 | /* Filesystem support (for USB key) */ |
109 | #define CONFIG_SUPPORT_VFAT | |
285e266b | 110 | |
995b72dd | 111 | |
995b72dd SR |
112 | /* |
113 | * U-Boot Environment placing definitions. | |
114 | */ | |
115 | #define CONFIG_ENV_SECT_SIZE 0x00010000 | |
116 | #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + \ | |
117 | CONFIG_SYS_MONITOR_LEN) | |
118 | #define CONFIG_ENV_SIZE 0x02000 | |
119 | #define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + \ | |
120 | CONFIG_ENV_SECT_SIZE) | |
121 | #define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE) | |
122 | ||
123 | /* Miscellaneous configurable options */ | |
124 | #define CONFIG_ARCH_CPU_INIT | |
995b72dd SR |
125 | #define CONFIG_BOOT_PARAMS_ADDR 0x00000100 |
126 | #define CONFIG_CMDLINE_TAG | |
995b72dd SR |
127 | #define CONFIG_SETUP_MEMORY_TAGS |
128 | #define CONFIG_MISC_INIT_R | |
995b72dd | 129 | #define CONFIG_MX_CYCLIC /* enable mdc/mwc commands */ |
995b72dd SR |
130 | |
131 | #define CONFIG_SYS_MEMTEST_START 0x00800000 | |
132 | #define CONFIG_SYS_MEMTEST_END 0x04000000 | |
285e266b | 133 | #define CONFIG_SYS_MALLOC_LEN (8 << 20) |
995b72dd | 134 | #define CONFIG_SYS_LONGHELP |
995b72dd | 135 | #define CONFIG_CMDLINE_EDITING |
285e266b | 136 | #define CONFIG_AUTO_COMPLETE |
995b72dd SR |
137 | #define CONFIG_SYS_CBSIZE 256 |
138 | #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ | |
139 | sizeof(CONFIG_SYS_PROMPT) + 16) | |
140 | #define CONFIG_SYS_MAXARGS 16 | |
141 | #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE | |
142 | #define CONFIG_SYS_LOAD_ADDR 0x00800000 | |
995b72dd SR |
143 | |
144 | /* Use last 2 lwords in internal SRAM for bootcounter */ | |
145 | #define CONFIG_BOOTCOUNT_LIMIT | |
2fbdbda1 SR |
146 | #define CONFIG_SYS_BOOTCOUNT_ADDR (CONFIG_SRAM_BASE + \ |
147 | CONFIG_SRAM_SIZE) | |
995b72dd SR |
148 | |
149 | #define CONFIG_HOSTNAME x600 | |
150 | #define CONFIG_UBI_PART ubi0 | |
151 | #define CONFIG_UBIFS_VOLUME rootfs | |
152 | ||
995b72dd SR |
153 | #define MTDIDS_DEFAULT "nand0=nand" |
154 | #define MTDPARTS_DEFAULT "mtdparts=nand:64M(ubi0),64M(ubi1)" | |
155 | ||
156 | #define CONFIG_EXTRA_ENV_SETTINGS \ | |
157 | "u-boot_addr=1000000\0" \ | |
4a8c3f69 | 158 | "u-boot=" __stringify(CONFIG_HOSTNAME) "/u-boot.spr\0" \ |
995b72dd | 159 | "load=tftp ${u-boot_addr} ${u-boot}\0" \ |
4a8c3f69 AG |
160 | "update=protect off " __stringify(CONFIG_SYS_MONITOR_BASE) \ |
161 | " +${filesize};" \ | |
162 | "erase " __stringify(CONFIG_SYS_MONITOR_BASE) " +${filesize};" \ | |
163 | "cp.b ${u-boot_addr} " __stringify(CONFIG_SYS_MONITOR_BASE) \ | |
995b72dd | 164 | " ${filesize};" \ |
4a8c3f69 | 165 | "protect on " __stringify(CONFIG_SYS_MONITOR_BASE) \ |
995b72dd SR |
166 | " +${filesize}\0" \ |
167 | "upd=run load update\0" \ | |
4a8c3f69 AG |
168 | "ubifs=" __stringify(CONFIG_HOSTNAME) "/ubifs.img\0" \ |
169 | "part=" __stringify(CONFIG_UBI_PART) "\0" \ | |
170 | "vol=" __stringify(CONFIG_UBIFS_VOLUME) "\0" \ | |
995b72dd SR |
171 | "load_ubifs=tftp ${kernel_addr} ${ubifs}\0" \ |
172 | "update_ubifs=ubi part ${part};ubi write ${kernel_addr} ${vol}" \ | |
173 | " ${filesize}\0" \ | |
174 | "upd_ubifs=run load_ubifs update_ubifs\0" \ | |
175 | "init_ubifs=nand erase.part ubi0;ubi part ${part};" \ | |
176 | "ubi create ${vol} 4000000\0" \ | |
177 | "netdev=eth0\0" \ | |
178 | "rootpath=/opt/eldk-4.2/arm\0" \ | |
179 | "nfsargs=setenv bootargs root=/dev/nfs rw " \ | |
180 | "nfsroot=${serverip}:${rootpath}\0" \ | |
181 | "ramargs=setenv bootargs root=/dev/ram rw\0" \ | |
182 | "boot_part=0\0" \ | |
183 | "altbootcmd=if test $boot_part -eq 0;then " \ | |
184 | "echo Switching to partition 1!;" \ | |
185 | "setenv boot_part 1;" \ | |
186 | "else; " \ | |
187 | "echo Switching to partition 0!;" \ | |
188 | "setenv boot_part 0;" \ | |
189 | "fi;" \ | |
190 | "saveenv;boot\0" \ | |
191 | "ubifsargs=set bootargs ubi.mtd=ubi${boot_part} " \ | |
192 | "root=ubi0:rootfs rootfstype=ubifs\0" \ | |
4a8c3f69 | 193 | "kernel=" __stringify(CONFIG_HOSTNAME) "/uImage\0" \ |
995b72dd SR |
194 | "kernel_fs=/boot/uImage \0" \ |
195 | "kernel_addr=1000000\0" \ | |
4a8c3f69 AG |
196 | "dtb=" __stringify(CONFIG_HOSTNAME) "/" \ |
197 | __stringify(CONFIG_HOSTNAME) ".dtb\0" \ | |
198 | "dtb_fs=/boot/" __stringify(CONFIG_HOSTNAME) ".dtb\0" \ | |
995b72dd SR |
199 | "dtb_addr=1800000\0" \ |
200 | "load_kernel=tftp ${kernel_addr} ${kernel}\0" \ | |
201 | "load_dtb=tftp ${dtb_addr} ${dtb}\0" \ | |
202 | "addip=setenv bootargs ${bootargs} " \ | |
203 | "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ | |
204 | ":${hostname}:${netdev}:off panic=1\0" \ | |
205 | "addcon=setenv bootargs ${bootargs} console=ttyAMA0," \ | |
206 | "${baudrate}\0" \ | |
207 | "addmtd=setenv bootargs ${bootargs} ${mtdparts}\0" \ | |
208 | "net_nfs=run load_dtb load_kernel; " \ | |
209 | "run nfsargs addip addcon addmtd addmisc;" \ | |
210 | "bootm ${kernel_addr} - ${dtb_addr}\0" \ | |
211 | "mtdids=" MTDIDS_DEFAULT "\0" \ | |
212 | "mtdparts=" MTDPARTS_DEFAULT "\0" \ | |
213 | "nand_ubifs=run ubifs_mount ubifs_load ubifsargs addip" \ | |
214 | " addcon addmisc addmtd;" \ | |
215 | "bootm ${kernel_addr} - ${dtb_addr}\0" \ | |
949a7710 | 216 | "ubifs_mount=ubi part ubi${boot_part};ubifsmount ubi:rootfs\0" \ |
995b72dd SR |
217 | "ubifs_load=ubifsload ${kernel_addr} ${kernel_fs};" \ |
218 | "ubifsload ${dtb_addr} ${dtb_fs};\0" \ | |
219 | "nand_ubifs=run ubifs_mount ubifs_load ubifsargs addip addcon " \ | |
220 | "addmtd addmisc;bootm ${kernel_addr} - ${dtb_addr}\0" \ | |
221 | "bootcmd=run nand_ubifs\0" \ | |
222 | "\0" | |
223 | ||
995b72dd SR |
224 | /* Physical Memory Map */ |
225 | #define CONFIG_NR_DRAM_BANKS 1 | |
226 | #define PHYS_SDRAM_1 0x00000000 | |
227 | #define PHYS_SDRAM_1_MAXSIZE 0x40000000 | |
228 | ||
229 | #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 | |
2fbdbda1 SR |
230 | #define CONFIG_SRAM_BASE 0xd2800000 |
231 | /* Preserve the last 2 lwords for the boot-counter */ | |
232 | #define CONFIG_SRAM_SIZE ((8 << 10) - 0x8) | |
233 | #define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SRAM_BASE | |
234 | #define CONFIG_SYS_INIT_RAM_SIZE CONFIG_SRAM_SIZE | |
995b72dd SR |
235 | |
236 | #define CONFIG_SYS_INIT_SP_OFFSET \ | |
237 | (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) | |
238 | ||
239 | #define CONFIG_SYS_INIT_SP_ADDR \ | |
240 | (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) | |
241 | ||
242 | /* | |
243 | * SPL related defines | |
244 | */ | |
2fbdbda1 SR |
245 | #define CONFIG_SPL_TEXT_BASE 0xd2800b00 |
246 | #define CONFIG_SPL_MAX_SIZE (CONFIG_SRAM_SIZE - 0xb00) | |
995b72dd SR |
247 | #define CONFIG_SPL_START_S_PATH "arch/arm/cpu/arm926ejs/spear" |
248 | #define CONFIG_SPL_LDSCRIPT "arch/arm/cpu/arm926ejs/spear/u-boot-spl.lds" | |
249 | ||
2fbdbda1 | 250 | #define CONFIG_SPL_FRAMEWORK |
995b72dd SR |
251 | |
252 | /* | |
253 | * Please select/define only one of the following | |
254 | * Each definition corresponds to a supported DDR chip. | |
255 | * DDR configuration is based on the following selection | |
256 | */ | |
257 | #define CONFIG_DDR_MT47H64M16 1 | |
258 | #define CONFIG_DDR_MT47H32M16 0 | |
259 | #define CONFIG_DDR_MT47H128M8 0 | |
260 | ||
261 | /* | |
262 | * Synchronous/Asynchronous operation of DDR | |
263 | * | |
264 | * Select CONFIG_DDR_2HCLK for DDR clk = 333MHz, synchronous operation | |
265 | * Select CONFIG_DDR_HCLK for DDR clk = 166MHz, synchronous operation | |
266 | * Select CONFIG_DDR_PLL2 for DDR clk = PLL2, asynchronous operation | |
267 | */ | |
268 | #define CONFIG_DDR_2HCLK 1 | |
269 | #define CONFIG_DDR_HCLK 0 | |
270 | #define CONFIG_DDR_PLL2 0 | |
271 | ||
272 | /* | |
273 | * xxx_BOOT_SUPPORTED macro defines whether a booting type is supported | |
274 | * or not. Modify/Add to only these macros to define new boot types | |
275 | */ | |
276 | #define USB_BOOT_SUPPORTED 0 | |
277 | #define PCIE_BOOT_SUPPORTED 0 | |
278 | #define SNOR_BOOT_SUPPORTED 1 | |
279 | #define NAND_BOOT_SUPPORTED 1 | |
280 | #define PNOR_BOOT_SUPPORTED 0 | |
281 | #define TFTP_BOOT_SUPPORTED 0 | |
282 | #define UART_BOOT_SUPPORTED 0 | |
283 | #define SPI_BOOT_SUPPORTED 0 | |
284 | #define I2C_BOOT_SUPPORTED 0 | |
285 | #define MMC_BOOT_SUPPORTED 0 | |
286 | ||
287 | #endif /* __CONFIG_H */ |