[people/ms/u-boot.git] / include / configs / xpedite550x.h

/*
 * Copyright 2010 Extreme Engineering Solutions, Inc.
 * Copyright 2007-2008 Freescale Semiconductor, Inc.
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

/*
 * xpedite550x board configuration file
 */
#ifndef __CONFIG_H
#define __CONFIG_H

/*
 * High Level Configuration Options
 */
#define CONFIG_SYS_BOARD_NAME	"XPedite5500"
#define CONFIG_SYS_FORM_PMC_XMC	1
#define CONFIG_PRPMC_PCI_ALIAS	"pci0"	/* Processor PMC interface on pci0 */
#define CONFIG_BOARD_EARLY_INIT_R	/* Call board_pre_init */

#ifndef CONFIG_SYS_TEXT_BASE
#define CONFIG_SYS_TEXT_BASE	0xfff80000
#endif

#define CONFIG_PCI_SCAN_SHOW	1	/* show pci devices on startup */
#define CONFIG_PCIE1		1	/* PCIE controller 1 (PEX8112 or XMC) */
#define CONFIG_FSL_PCI_INIT	1	/* Use common FSL init code */
#define CONFIG_PCI_INDIRECT_BRIDGE 1	/* indirect PCI bridge support */
#define CONFIG_SYS_PCI_64BIT	1	/* enable 64-bit PCI resources */
#define CONFIG_FSL_PCIE_RESET	1	/* need PCIe reset errata */

/*
 * Multicore config
 */
#define CONFIG_MP
#define CONFIG_BPTR_VIRT_ADDR	0xee000000	/* virt boot page address */
#define CONFIG_MPC8xxx_DISABLE_BPTR		/* Don't leave BPTR enabled */

/*
 * DDR config
 */
#define CONFIG_SPD_EEPROM		/* Use SPD EEPROM for DDR setup */
#define CONFIG_DDR_SPD
#define CONFIG_MEM_INIT_VALUE		0xdeadbeef
#define SPD_EEPROM_ADDRESS			0x54
#define SPD_EEPROM_OFFSET		0x200	/* OFFSET of SPD in EEPROM */
#define CONFIG_DIMM_SLOTS_PER_CTLR	1
#define CONFIG_CHIP_SELECTS_PER_CTRL 2
#define CONFIG_DDR_ECC
#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
#define CONFIG_SYS_DDR_SDRAM_BASE	0x00000000 /* DDR is system memory*/
#define CONFIG_SYS_SDRAM_BASE		CONFIG_SYS_DDR_SDRAM_BASE
#define CONFIG_VERY_BIG_RAM

#ifndef __ASSEMBLY__
extern unsigned long get_board_sys_clk(unsigned long dummy);
extern unsigned long get_board_ddr_clk(unsigned long dummy);
#endif

#define CONFIG_SYS_CLK_FREQ	get_board_sys_clk(0) /* sysclk for MPC85xx */
#define CONFIG_DDR_CLK_FREQ	get_board_ddr_clk(0) /* ddrclk for MPC85xx */

/*
 * These can be toggled for performance analysis, otherwise use default.
 */
#define CONFIG_L2_CACHE			/* toggle L2 cache */
#define CONFIG_BTB			/* toggle branch predition */
#define CONFIG_ENABLE_36BIT_PHYS	1

#define CONFIG_SYS_CCSRBAR		0xef000000
#define CONFIG_SYS_CCSRBAR_PHYS_LOW	CONFIG_SYS_CCSRBAR

/*
 * Diagnostics
 */
#define CONFIG_SYS_ALT_MEMTEST
#define CONFIG_SYS_MEMTEST_START	0x10000000
#define CONFIG_SYS_MEMTEST_END		0x20000000
#define CONFIG_POST			(CONFIG_SYS_POST_MEMORY | \
					 CONFIG_SYS_POST_I2C)
#define I2C_ADDR_LIST			{CONFIG_SYS_I2C_EEPROM_ADDR,	\
					 CONFIG_SYS_I2C_LM75_ADDR,	\
					 CONFIG_SYS_I2C_LM90_ADDR,	\
					 CONFIG_SYS_I2C_PCA953X_ADDR0,	\
					 CONFIG_SYS_I2C_PCA953X_ADDR2,	\
					 CONFIG_SYS_I2C_PCA953X_ADDR3,	\
					 CONFIG_SYS_I2C_RTC_ADDR}

/*
 * Memory map
 * 0x0000_0000 0x7fff_ffff	DDR			2G Cacheable
 * 0x8000_0000 0xbfff_ffff	PCIe1 Mem		1G non-cacheable
 * 0xe000_0000 0xe7ff_ffff	SRAM/SSRAM/L1 Cache	128M non-cacheable
 * 0xe800_0000 0xe87f_ffff	PCIe1 IO		8M non-cacheable
 * 0xee00_0000 0xee00_ffff	Boot page translation	4K non-cacheable
 * 0xef00_0000 0xef0f_ffff	CCSR/IMMR		1M non-cacheable
 * 0xef80_0000 0xef8f_ffff	NAND Flash		1M non-cacheable
 * 0xf000_0000 0xf7ff_ffff	NOR Flash 2		128M non-cacheable
 * 0xf800_0000 0xffff_ffff	NOR Flash 1		128M non-cacheable
 */

#define CONFIG_SYS_LBC_LCRR	(LCRR_CLKDIV_8 | LCRR_EADC_3)

/*
 * NAND flash configuration
 */
#define CONFIG_SYS_NAND_BASE		0xef800000
#define CONFIG_SYS_NAND_BASE2		0xef840000 /* Unused at this time */
#define CONFIG_SYS_NAND_BASE_LIST	{CONFIG_SYS_NAND_BASE, \
					 CONFIG_SYS_NAND_BASE2}
#define CONFIG_SYS_MAX_NAND_DEVICE	2
#define CONFIG_NAND_FSL_ELBC

/*
 * NOR flash configuration
 */
#define CONFIG_SYS_FLASH_BASE		0xf8000000
#define CONFIG_SYS_FLASH_BASE2		0xf0000000
#define CONFIG_SYS_FLASH_BANKS_LIST	{CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE2}
#define CONFIG_SYS_MAX_FLASH_BANKS	2		/* number of banks */
#define CONFIG_SYS_MAX_FLASH_SECT	1024		/* sectors per device */
#define CONFIG_SYS_FLASH_ERASE_TOUT	60000		/* Flash Erase Timeout (ms) */
#define CONFIG_SYS_FLASH_WRITE_TOUT	500		/* Flash Write Timeout (ms) */
#define CONFIG_FLASH_CFI_DRIVER
#define CONFIG_SYS_FLASH_CFI
#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
#define CONFIG_SYS_FLASH_AUTOPROTECT_LIST	{ {0xfff40000, 0xc0000}, \
						  {0xf7f40000, 0xc0000} }
#define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_TEXT_BASE	/* start of monitor */

/*
 * Chip select configuration
 */
/* NOR Flash 0 on CS0 */
#define CONFIG_SYS_BR0_PRELIM	(CONFIG_SYS_FLASH_BASE	| \
				 BR_PS_16		| \
				 BR_V)
#define CONFIG_SYS_OR0_PRELIM	(OR_AM_128MB		| \
				 OR_GPCM_CSNT		| \
				 OR_GPCM_XACS		| \
				 OR_GPCM_ACS_DIV2	| \
				 OR_GPCM_SCY_8		| \
				 OR_GPCM_TRLX		| \
				 OR_GPCM_EHTR		| \
				 OR_GPCM_EAD)

/* NOR Flash 1 on CS1 */
#define CONFIG_SYS_BR1_PRELIM	(CONFIG_SYS_FLASH_BASE2	| \
				 BR_PS_16		| \
				 BR_V)
#define CONFIG_SYS_OR1_PRELIM	CONFIG_SYS_OR0_PRELIM

/* NAND flash on CS2 */
#define CONFIG_SYS_BR2_PRELIM	(CONFIG_SYS_NAND_BASE	| \
				 (2<<BR_DECC_SHIFT)	| \
				 BR_PS_8		| \
				 BR_MS_FCM		| \
				 BR_V)

/* NAND flash on CS2 */
#define CONFIG_SYS_OR2_PRELIM	(OR_AM_256KB	| \
				 OR_FCM_PGS	| \
				 OR_FCM_CSCT	| \
				 OR_FCM_CST	| \
				 OR_FCM_CHT	| \
				 OR_FCM_SCY_1	| \
				 OR_FCM_TRLX	| \
				 OR_FCM_EHTR)

/* NAND flash on CS3 */
#define CONFIG_SYS_BR3_PRELIM	(CONFIG_SYS_NAND_BASE2	| \
				 (2<<BR_DECC_SHIFT)	| \
				 BR_PS_8		| \
				 BR_MS_FCM		| \
				 BR_V)
#define CONFIG_SYS_OR3_PRELIM	CONFIG_SYS_OR2_PRELIM

/*
 * Use L1 as initial stack
 */
#define CONFIG_SYS_INIT_RAM_LOCK	1
#define CONFIG_SYS_INIT_RAM_ADDR	0xe0000000
#define CONFIG_SYS_INIT_RAM_SIZE		0x00004000

#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET

#define CONFIG_SYS_MONITOR_LEN		(512 * 1024)	/* Reserve 512 KB for Mon */
#define CONFIG_SYS_MALLOC_LEN		(1024 * 1024)	/* Reserved for malloc */

/*
 * Serial Port
 */
#define CONFIG_CONS_INDEX		1
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE	1
#define CONFIG_SYS_NS16550_CLK		get_bus_freq(0)
#define CONFIG_SYS_NS16550_COM1	(CONFIG_SYS_CCSRBAR+0x4500)
#define CONFIG_SYS_NS16550_COM2	(CONFIG_SYS_CCSRBAR+0x4600)
#define CONFIG_SYS_BAUDRATE_TABLE	\
	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
#define CONFIG_LOADS_ECHO		1	/* echo on for serial download */
#define CONFIG_SYS_LOADS_BAUD_CHANGE	1	/* allow baudrate change */


/*
 * I2C
 */
#define CONFIG_SYS_I2C
#define CONFIG_SYS_I2C_FSL
#define CONFIG_SYS_FSL_I2C_SPEED	400000
#define CONFIG_SYS_FSL_I2C_SLAVE	0x7F
#define CONFIG_SYS_FSL_I2C_OFFSET	0x3000
#define CONFIG_SYS_FSL_I2C2_SPEED	400000
#define CONFIG_SYS_FSL_I2C2_SLAVE	0x7F
#define CONFIG_SYS_FSL_I2C2_OFFSET	0x3100

/* I2C DS7505 temperature sensor */
#define CONFIG_SYS_I2C_LM75_ADDR	0x48

/* I2C ADT7461 temperature sensor */
#define CONFIG_SYS_I2C_LM90_ADDR	0x4C

/* I2C EEPROM - AT24C128B */
#define CONFIG_SYS_I2C_EEPROM_ADDR		0x54
#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN		2
#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS	6	/* 64 byte pages */
#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS	10	/* take up to 10 msec */

/* I2C RTC */
#define CONFIG_RTC_M41T11		1
#define CONFIG_SYS_I2C_RTC_ADDR		0x68
#define CONFIG_SYS_M41T11_BASE_YEAR	2000

/* GPIO */
#define CONFIG_PCA953X
#define CONFIG_SYS_I2C_PCA953X_ADDR0	0x18
#define CONFIG_SYS_I2C_PCA953X_ADDR1	0x1c
#define CONFIG_SYS_I2C_PCA953X_ADDR2	0x1e
#define CONFIG_SYS_I2C_PCA953X_ADDR3	0x1f
#define CONFIG_SYS_I2C_PCA953X_ADDR	CONFIG_SYS_I2C_PCA953X_ADDR0

/*
 * GPIO pin definitions, PU = pulled high, PD = pulled low
 */
/* PCA9557 @ 0x18*/
#define CONFIG_SYS_PCA953X_C0_SER0_EN		0x01 /* PU; UART0 enable (1: enabled) */
#define CONFIG_SYS_PCA953X_C0_SER0_MODE		0x02 /* PU; UART0 serial mode select (1: RS-485, 0: RS-232) */
#define CONFIG_SYS_PCA953X_C0_SER1_EN		0x04 /* PU; UART1 enable (1: enabled) */
#define CONFIG_SYS_PCA953X_C0_SER1_MODE		0x08 /* PU; UART1 serial mode select (1: RS-485, 0: RS-232) */
#define CONFIG_SYS_PCA953X_C0_FLASH_PASS_CS	0x10 /* PU; Boot flash CS select */
#define CONFIG_SYS_PCA953X_NVM_WP		0x20 /* PU; Write protection (0: disabled, 1: enabled) */

/* PCA9557 @ 0x1e*/
#define CONFIG_SYS_PCA953X_XMC_GA0		0x01 /* PU; */
#define CONFIG_SYS_PCA953X_XMC_GA1		0x02 /* PU; */
#define CONFIG_SYS_PCA953X_XMC_GA2		0x04 /* PU; */
#define CONFIG_SYS_PCA953X_XMC_WAKE		0x10 /* PU; */
#define CONFIG_SYS_PCA953X_XMC_BIST		0x20 /* Enable XMC BIST */
#define CONFIG_SYS_PCA953X_PMC_EREADY		0x40 /* PU; PMC PCI eready */
#define CONFIG_SYS_PCA953X_PMC_MONARCH		0x80 /* PMC monarch mode enable */

/* PCA9557 @ 0x1f */
#define CONFIG_SYS_PCA953X_MC_GPIO0		0x01 /* PU; */
#define CONFIG_SYS_PCA953X_MC_GPIO1		0x02 /* PU; */
#define CONFIG_SYS_PCA953X_MC_GPIO2		0x04 /* PU; */
#define CONFIG_SYS_PCA953X_MC_GPIO3		0x08 /* PU; */
#define CONFIG_SYS_PCA953X_MC_GPIO4		0x10 /* PU; */
#define CONFIG_SYS_PCA953X_MC_GPIO5		0x20 /* PU; */
#define CONFIG_SYS_PCA953X_MC_GPIO6		0x40 /* PU; */
#define CONFIG_SYS_PCA953X_MC_GPIO7		0x80 /* PU; */

/*
 * General PCI
 * Memory space is mapped 1-1, but I/O space must start from 0.
 */

/* controller 1 - PEX8112 or XMC, depending on build option */
#define CONFIG_SYS_PCIE1_MEM_BUS	0x80000000
#define CONFIG_SYS_PCIE1_MEM_PHYS	CONFIG_SYS_PCIE1_MEM_BUS
#define CONFIG_SYS_PCIE1_MEM_SIZE	0x40000000	/* 1G */
#define CONFIG_SYS_PCIE1_IO_BUS		0x00000000
#define CONFIG_SYS_PCIE1_IO_PHYS	0xe8000000
#define CONFIG_SYS_PCIE1_IO_SIZE	0x00800000	/* 8M */

/*
 * Networking options
 */
#define CONFIG_TSEC_ENET		/* tsec ethernet support */
#define CONFIG_TSEC_TBI
#define CONFIG_MII		1	/* MII PHY management */
#define CONFIG_MII_DEFAULT_TSEC	1	/* Allow unregistered phys */
#define CONFIG_ETHPRIME		"eTSEC2"

/*
 * In-band SGMII auto-negotiation between TBI and BCM5482S PHY fails, force
 * 1000mbps SGMII link
 */
#define CONFIG_TSEC_TBICR_SETTINGS ( \
		TBICR_PHY_RESET \
		| TBICR_FULL_DUPLEX \
		| TBICR_SPEED1_SET \
		)

#define CONFIG_TSEC1		1
#define CONFIG_TSEC1_NAME	"eTSEC1"
#define TSEC1_FLAGS		(TSEC_GIGABIT | TSEC_REDUCED)
#define TSEC1_PHY_ADDR		1
#define TSEC1_PHYIDX		0
#define CONFIG_HAS_ETH0

#define CONFIG_TSEC2		1
#define CONFIG_TSEC2_NAME	"eTSEC2"
#define TSEC2_FLAGS		(TSEC_GIGABIT | TSEC_REDUCED)
#define TSEC2_PHY_ADDR		2
#define TSEC2_PHYIDX		0
#define CONFIG_HAS_ETH1

#define CONFIG_TSEC3		1
#define CONFIG_TSEC3_NAME	"eTSEC3"
#define TSEC3_FLAGS		(TSEC_GIGABIT | TSEC_REDUCED)
#define TSEC3_PHY_ADDR		3
#define TSEC3_PHYIDX		0
#define CONFIG_HAS_ETH2

/*
 * USB
 */
#define CONFIG_USB_EHCI_FSL
#define CONFIG_EHCI_HCD_INIT_AFTER_RESET

/*
 * Miscellaneous configurable options
 */
#define CONFIG_SYS_LONGHELP			/* undef to save memory	*/
#define CONFIG_SYS_LOAD_ADDR	0x2000000	/* default load address */
#define CONFIG_CMDLINE_EDITING	1		/* add command line history	*/
#define CONFIG_AUTO_COMPLETE	1		/* add autocompletion support */
#define CONFIG_LOADADDR		0x1000000	/* default location for tftp and bootm */
#define CONFIG_PREBOOT				/* enable preboot variable */
#define CONFIG_INTEGRITY			/* support booting INTEGRITY OS */

/*
 * For booting Linux, the board info and command line data
 * have to be in the first 16 MB of memory, since this is
 * the maximum mapped by the Linux kernel during initialization.
 */
#define CONFIG_SYS_BOOTMAPSZ	(16 << 20)	/* Initial Memory map for Linux*/
#define CONFIG_SYS_BOOTM_LEN	(16 << 20)	/* Increase max gunzip size */

/*
 * Environment Configuration
 */
#define CONFIG_ENV_SECT_SIZE	0x20000		/* 128k (one sector) for env */
#define CONFIG_ENV_SIZE		0x8000
#define CONFIG_ENV_ADDR		(CONFIG_SYS_MONITOR_BASE - (256 * 1024))

/*
 * Flash memory map:
 * fff80000 - ffffffff     Pri U-Boot (512 KB)
 * fff40000 - fff7ffff     Pri U-Boot Environment (256 KB)
 * fff00000 - fff3ffff     Pri FDT (256KB)
 * fef00000 - ffefffff     Pri OS image (16MB)
 * f8000000 - feefffff     Pri OS Use/Filesystem (111MB)
 *
 * f7f80000 - f7ffffff     Sec U-Boot (512 KB)
 * f7f40000 - f7f7ffff     Sec U-Boot Environment (256 KB)
 * f7f00000 - f7f3ffff     Sec FDT (256KB)
 * f6f00000 - f7efffff     Sec OS image (16MB)
 * f0000000 - f6efffff     Sec OS Use/Filesystem (111MB)
 */
#define CONFIG_UBOOT1_ENV_ADDR	__stringify(0xfff80000)
#define CONFIG_UBOOT2_ENV_ADDR	__stringify(0xf7f80000)
#define CONFIG_FDT1_ENV_ADDR	__stringify(0xfff00000)
#define CONFIG_FDT2_ENV_ADDR	__stringify(0xf7f00000)
#define CONFIG_OS1_ENV_ADDR	__stringify(0xfef00000)
#define CONFIG_OS2_ENV_ADDR	__stringify(0xf6f00000)

#define CONFIG_PROG_UBOOT1						\
	"$download_cmd $loadaddr $ubootfile; "				\
	"if test $? -eq 0; then "					\
		"protect off "CONFIG_UBOOT1_ENV_ADDR" +80000; "		\
		"erase "CONFIG_UBOOT1_ENV_ADDR" +80000; "		\
		"cp.w $loadaddr "CONFIG_UBOOT1_ENV_ADDR" 40000; "	\
		"protect on "CONFIG_UBOOT1_ENV_ADDR" +80000; "		\
		"cmp.b $loadaddr "CONFIG_UBOOT1_ENV_ADDR" 80000; "	\
		"if test $? -ne 0; then "				\
			"echo PROGRAM FAILED; "				\
		"else; "						\
			"echo PROGRAM SUCCEEDED; "			\
		"fi; "							\
	"else; "							\
		"echo DOWNLOAD FAILED; "				\
	"fi;"

#define CONFIG_PROG_UBOOT2						\
	"$download_cmd $loadaddr $ubootfile; "				\
	"if test $? -eq 0; then "					\
		"protect off "CONFIG_UBOOT2_ENV_ADDR" +80000; "		\
		"erase "CONFIG_UBOOT2_ENV_ADDR" +80000; "		\
		"cp.w $loadaddr "CONFIG_UBOOT2_ENV_ADDR" 40000; "	\
		"protect on "CONFIG_UBOOT2_ENV_ADDR" +80000; "		\
		"cmp.b $loadaddr "CONFIG_UBOOT2_ENV_ADDR" 80000; "	\
		"if test $? -ne 0; then "				\
			"echo PROGRAM FAILED; "				\
		"else; "						\
			"echo PROGRAM SUCCEEDED; "			\
		"fi; "							\
	"else; "							\
		"echo DOWNLOAD FAILED; "				\
	"fi;"

#define CONFIG_BOOT_OS_NET						\
	"$download_cmd $osaddr $osfile; "				\
	"if test $? -eq 0; then "					\
		"if test -n $fdtaddr; then "				\
			"$download_cmd $fdtaddr $fdtfile; "		\
			"if test $? -eq 0; then "			\
				"bootm $osaddr - $fdtaddr; "		\
			"else; "					\
				"echo FDT DOWNLOAD FAILED; "		\
			"fi; "						\
		"else; "						\
			"bootm $osaddr; "				\
		"fi; "							\
	"else; "							\
		"echo OS DOWNLOAD FAILED; "				\
	"fi;"

#define CONFIG_PROG_OS1							\
	"$download_cmd $osaddr $osfile; "				\
	"if test $? -eq 0; then "					\
		"erase "CONFIG_OS1_ENV_ADDR" +$filesize; "		\
		"cp.b $osaddr "CONFIG_OS1_ENV_ADDR" $filesize; "	\
		"cmp.b $osaddr "CONFIG_OS1_ENV_ADDR" $filesize; "	\
		"if test $? -ne 0; then "				\
			"echo OS PROGRAM FAILED; "			\
		"else; "						\
			"echo OS PROGRAM SUCCEEDED; "			\
		"fi; "							\
	"else; "							\
		"echo OS DOWNLOAD FAILED; "				\
	"fi;"

#define CONFIG_PROG_OS2							\
	"$download_cmd $osaddr $osfile; "				\
	"if test $? -eq 0; then "					\
		"erase "CONFIG_OS2_ENV_ADDR" +$filesize; "		\
		"cp.b $osaddr "CONFIG_OS2_ENV_ADDR" $filesize; "	\
		"cmp.b $osaddr "CONFIG_OS2_ENV_ADDR" $filesize; "	\
		"if test $? -ne 0; then "				\
			"echo OS PROGRAM FAILED; "			\
		"else; "						\
			"echo OS PROGRAM SUCCEEDED; "			\
		"fi; "							\
	"else; "							\
		"echo OS DOWNLOAD FAILED; "				\
	"fi;"

#define CONFIG_PROG_FDT1						\
	"$download_cmd $fdtaddr $fdtfile; "				\
	"if test $? -eq 0; then "					\
		"erase "CONFIG_FDT1_ENV_ADDR" +$filesize;"		\
		"cp.b $fdtaddr "CONFIG_FDT1_ENV_ADDR" $filesize; "	\
		"cmp.b $fdtaddr "CONFIG_FDT1_ENV_ADDR" $filesize; "	\
		"if test $? -ne 0; then "				\
			"echo FDT PROGRAM FAILED; "			\
		"else; "						\
			"echo FDT PROGRAM SUCCEEDED; "			\
		"fi; "							\
	"else; "							\
		"echo FDT DOWNLOAD FAILED; "				\
	"fi;"

#define CONFIG_PROG_FDT2						\
	"$download_cmd $fdtaddr $fdtfile; "				\
	"if test $? -eq 0; then "					\
		"erase "CONFIG_FDT2_ENV_ADDR" +$filesize;"		\
		"cp.b $fdtaddr "CONFIG_FDT2_ENV_ADDR" $filesize; "	\
		"cmp.b $fdtaddr "CONFIG_FDT2_ENV_ADDR" $filesize; "	\
		"if test $? -ne 0; then "				\
			"echo FDT PROGRAM FAILED; "			\
		"else; "						\
			"echo FDT PROGRAM SUCCEEDED; "			\
		"fi; "							\
	"else; "							\
		"echo FDT DOWNLOAD FAILED; "				\
	"fi;"

#define CONFIG_EXTRA_ENV_SETTINGS					\
	"autoload=yes\0"						\
	"download_cmd=tftp\0"						\
	"console_args=console=ttyS0,115200\0"				\
	"root_args=root=/dev/nfs rw\0"					\
	"misc_args=ip=on\0"						\
	"set_bootargs=setenv bootargs ${console_args} ${root_args} ${misc_args}\0" \
	"bootfile=/home/user/file\0"					\
	"osfile=/home/user/board.uImage\0"				\
	"fdtfile=/home/user/board.dtb\0"				\
	"ubootfile=/home/user/u-boot.bin\0"				\
	"fdtaddr=0x1e00000\0"						\
	"osaddr=0x1000000\0"						\
	"loadaddr=0x1000000\0"						\
	"prog_uboot1="CONFIG_PROG_UBOOT1"\0"				\
	"prog_uboot2="CONFIG_PROG_UBOOT2"\0"				\
	"prog_os1="CONFIG_PROG_OS1"\0"					\
	"prog_os2="CONFIG_PROG_OS2"\0"					\
	"prog_fdt1="CONFIG_PROG_FDT1"\0"				\
	"prog_fdt2="CONFIG_PROG_FDT2"\0"				\
	"bootcmd_net=run set_bootargs; "CONFIG_BOOT_OS_NET"\0"		\
	"bootcmd_flash1=run set_bootargs; "				\
		"bootm "CONFIG_OS1_ENV_ADDR" - "CONFIG_FDT1_ENV_ADDR"\0"\
	"bootcmd_flash2=run set_bootargs; "				\
		"bootm "CONFIG_OS2_ENV_ADDR" - "CONFIG_FDT2_ENV_ADDR"\0"\
	"bootcmd=run bootcmd_flash1\0"
#endif	/* __CONFIG_H */
Commit	Line	Data
bfe18815 JS	1	/*
	2	* Copyright 2010 Extreme Engineering Solutions, Inc.
	3	* Copyright 2007-2008 Freescale Semiconductor, Inc.
	4	*
1a459660	5	* SPDX-License-Identifier: GPL-2.0+
bfe18815 JS	6	*/
	7
	8	/*
	9	* xpedite550x board configuration file
	10	*/
	11	#ifndef __CONFIG_H
	12	#define __CONFIG_H
	13
	14	/*
	15	* High Level Configuration Options
	16	*/
bfe18815 JS	17	#define CONFIG_SYS_BOARD_NAME "XPedite5500"
	18	#define CONFIG_SYS_FORM_PMC_XMC 1
	19	#define CONFIG_PRPMC_PCI_ALIAS "pci0" /* Processor PMC interface on pci0 */
	20	#define CONFIG_BOARD_EARLY_INIT_R /* Call board_pre_init */
	21
	22	#ifndef CONFIG_SYS_TEXT_BASE
	23	#define CONFIG_SYS_TEXT_BASE 0xfff80000
	24	#endif
	25
bfe18815	26	#define CONFIG_PCI_SCAN_SHOW 1 /* show pci devices on startup */
b38eaec5	27	#define CONFIG_PCIE1 1 /* PCIE controller 1 (PEX8112 or XMC) */
bfe18815	28	#define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */
842033e6	29	#define CONFIG_PCI_INDIRECT_BRIDGE 1 /* indirect PCI bridge support */
bfe18815 JS	30	#define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */
bfe18815 JS	31	#define CONFIG_FSL_PCIE_RESET 1 /* need PCIe reset errata */
bfe18815 JS	32
	33	/*
	34	* Multicore config
	35	*/
	36	#define CONFIG_MP
	37	#define CONFIG_BPTR_VIRT_ADDR 0xee000000 /* virt boot page address */
	38	#define CONFIG_MPC8xxx_DISABLE_BPTR /* Don't leave BPTR enabled */
	39
	40	/*
	41	* DDR config
	42	*/
bfe18815 JS	43	#define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */
	44	#define CONFIG_DDR_SPD
	45	#define CONFIG_MEM_INIT_VALUE 0xdeadbeef
c39f44dc	46	#define SPD_EEPROM_ADDRESS 0x54
bfe18815	47	#define SPD_EEPROM_OFFSET 0x200 /* OFFSET of SPD in EEPROM */
bfe18815 JS	48	#define CONFIG_DIMM_SLOTS_PER_CTLR 1
	49	#define CONFIG_CHIP_SELECTS_PER_CTRL 2
	50	#define CONFIG_DDR_ECC
	51	#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
	52	#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory*/
	53	#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
	54	#define CONFIG_VERY_BIG_RAM
	55
	56	#ifndef __ASSEMBLY__
	57	extern unsigned long get_board_sys_clk(unsigned long dummy);
	58	extern unsigned long get_board_ddr_clk(unsigned long dummy);
	59	#endif
	60
	61	#define CONFIG_SYS_CLK_FREQ get_board_sys_clk(0) /* sysclk for MPC85xx */
	62	#define CONFIG_DDR_CLK_FREQ get_board_ddr_clk(0) /* ddrclk for MPC85xx */
	63
	64	/*
	65	* These can be toggled for performance analysis, otherwise use default.
	66	*/
	67	#define CONFIG_L2_CACHE /* toggle L2 cache */
	68	#define CONFIG_BTB /* toggle branch predition */
	69	#define CONFIG_ENABLE_36BIT_PHYS 1
	70
e46fedfe TT	71	#define CONFIG_SYS_CCSRBAR 0xef000000
e46fedfe TT	72	#define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR
bfe18815 JS	73
	74	/*
	75	* Diagnostics
	76	*/
	77	#define CONFIG_SYS_ALT_MEMTEST
	78	#define CONFIG_SYS_MEMTEST_START 0x10000000
	79	#define CONFIG_SYS_MEMTEST_END 0x20000000
	80	#define CONFIG_POST (CONFIG_SYS_POST_MEMORY \| \
	81	CONFIG_SYS_POST_I2C)
	82	#define I2C_ADDR_LIST {CONFIG_SYS_I2C_EEPROM_ADDR, \
	83	CONFIG_SYS_I2C_LM75_ADDR, \
	84	CONFIG_SYS_I2C_LM90_ADDR, \
	85	CONFIG_SYS_I2C_PCA953X_ADDR0, \
	86	CONFIG_SYS_I2C_PCA953X_ADDR2, \
	87	CONFIG_SYS_I2C_PCA953X_ADDR3, \
	88	CONFIG_SYS_I2C_RTC_ADDR}
	89
	90	/*
	91	* Memory map
	92	* 0x0000_0000 0x7fff_ffff DDR 2G Cacheable
	93	* 0x8000_0000 0xbfff_ffff PCIe1 Mem 1G non-cacheable
	94	* 0xe000_0000 0xe7ff_ffff SRAM/SSRAM/L1 Cache 128M non-cacheable
	95	* 0xe800_0000 0xe87f_ffff PCIe1 IO 8M non-cacheable
	96	* 0xee00_0000 0xee00_ffff Boot page translation 4K non-cacheable
	97	* 0xef00_0000 0xef0f_ffff CCSR/IMMR 1M non-cacheable
	98	* 0xef80_0000 0xef8f_ffff NAND Flash 1M non-cacheable
	99	* 0xf000_0000 0xf7ff_ffff NOR Flash 2 128M non-cacheable
	100	* 0xf800_0000 0xffff_ffff NOR Flash 1 128M non-cacheable
	101	*/
	102
	103	#define CONFIG_SYS_LBC_LCRR (LCRR_CLKDIV_8 \| LCRR_EADC_3)
	104
	105	/*
	106	* NAND flash configuration
	107	*/
	108	#define CONFIG_SYS_NAND_BASE 0xef800000
	109	#define CONFIG_SYS_NAND_BASE2 0xef840000 /* Unused at this time */
	110	#define CONFIG_SYS_NAND_BASE_LIST {CONFIG_SYS_NAND_BASE, \
	111	CONFIG_SYS_NAND_BASE2}
	112	#define CONFIG_SYS_MAX_NAND_DEVICE 2
bfe18815 JS	113	#define CONFIG_NAND_FSL_ELBC
	114
	115	/*
	116	* NOR flash configuration
	117	*/
	118	#define CONFIG_SYS_FLASH_BASE 0xf8000000
	119	#define CONFIG_SYS_FLASH_BASE2 0xf0000000
	120	#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE2}
	121	#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */
	122	#define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */
	123	#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
	124	#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
	125	#define CONFIG_FLASH_CFI_DRIVER
	126	#define CONFIG_SYS_FLASH_CFI
	127	#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
	128	#define CONFIG_SYS_FLASH_AUTOPROTECT_LIST { {0xfff40000, 0xc0000}, \
	129	{0xf7f40000, 0xc0000} }
	130	#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
	131
	132	/*
	133	* Chip select configuration
	134	*/
	135	/* NOR Flash 0 on CS0 */
	136	#define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE \| \
	137	BR_PS_16 \| \
	138	BR_V)
	139	#define CONFIG_SYS_OR0_PRELIM (OR_AM_128MB \| \
	140	OR_GPCM_CSNT \| \
	141	OR_GPCM_XACS \| \
	142	OR_GPCM_ACS_DIV2 \| \
	143	OR_GPCM_SCY_8 \| \
	144	OR_GPCM_TRLX \| \
	145	OR_GPCM_EHTR \| \
	146	OR_GPCM_EAD)
	147
	148	/* NOR Flash 1 on CS1 */
	149	#define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_FLASH_BASE2 \| \
	150	BR_PS_16 \| \
	151	BR_V)
	152	#define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_OR0_PRELIM
	153
	154	/* NAND flash on CS2 */
	155	#define CONFIG_SYS_BR2_PRELIM (CONFIG_SYS_NAND_BASE \| \
	156	(2<<BR_DECC_SHIFT) \| \
	157	BR_PS_8 \| \
	158	BR_MS_FCM \| \
	159	BR_V)
	160
	161	/* NAND flash on CS2 */
	162	#define CONFIG_SYS_OR2_PRELIM (OR_AM_256KB \| \
	163	OR_FCM_PGS \| \
	164	OR_FCM_CSCT \| \
	165	OR_FCM_CST \| \
	166	OR_FCM_CHT \| \
	167	OR_FCM_SCY_1 \| \
	168	OR_FCM_TRLX \| \
	169	OR_FCM_EHTR)
	170
	171	/* NAND flash on CS3 */
	172	#define CONFIG_SYS_BR3_PRELIM (CONFIG_SYS_NAND_BASE2 \| \
	173	(2<<BR_DECC_SHIFT) \| \
	174	BR_PS_8 \| \
	175	BR_MS_FCM \| \
	176	BR_V)
177	#define CONFIG_SYS_OR3_PRELIM CONFIG_SYS_OR2_PRELIM
178
179	/*
180	* Use L1 as initial stack
181	*/
182	#define CONFIG_SYS_INIT_RAM_LOCK 1
183	#define CONFIG_SYS_INIT_RAM_ADDR 0xe0000000
553f0982	184	#define CONFIG_SYS_INIT_RAM_SIZE 0x00004000
bfe18815	185
25ddd1fb	186	#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
bfe18815 JS	187	#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
	188
	189	#define CONFIG_SYS_MONITOR_LEN (512 * 1024) /* Reserve 512 KB for Mon */
	190	#define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc */
	191
	192	/*
	193	* Serial Port
	194	*/
	195	#define CONFIG_CONS_INDEX 1
bfe18815 JS	196	#define CONFIG_SYS_NS16550_SERIAL
	197	#define CONFIG_SYS_NS16550_REG_SIZE 1
	198	#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
	199	#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
	200	#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
	201	#define CONFIG_SYS_BAUDRATE_TABLE \
	202	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
bfe18815 JS	203	#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
	204	#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
	205
bfe18815 JS	206
	207	/*
	208	* I2C
	209	*/
00f792e0 HS	210	#define CONFIG_SYS_I2C
	211	#define CONFIG_SYS_I2C_FSL
	212	#define CONFIG_SYS_FSL_I2C_SPEED 400000
	213	#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
	214	#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
	215	#define CONFIG_SYS_FSL_I2C2_SPEED 400000
	216	#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
	217	#define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100
bfe18815 JS	218
bfe18815 JS	219	/* I2C DS7505 temperature sensor */
bfe18815 JS	220	#define CONFIG_SYS_I2C_LM75_ADDR 0x48
	221
	222	/* I2C ADT7461 temperature sensor */
	223	#define CONFIG_SYS_I2C_LM90_ADDR 0x4C
	224
	225	/* I2C EEPROM - AT24C128B */
	226	#define CONFIG_SYS_I2C_EEPROM_ADDR 0x54
	227	#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
	228	#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 6 /* 64 byte pages */
	229	#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* take up to 10 msec */
	230
	231	/* I2C RTC */
	232	#define CONFIG_RTC_M41T11 1
	233	#define CONFIG_SYS_I2C_RTC_ADDR 0x68
	234	#define CONFIG_SYS_M41T11_BASE_YEAR 2000
	235
	236	/* GPIO */
	237	#define CONFIG_PCA953X
	238	#define CONFIG_SYS_I2C_PCA953X_ADDR0 0x18
	239	#define CONFIG_SYS_I2C_PCA953X_ADDR1 0x1c
	240	#define CONFIG_SYS_I2C_PCA953X_ADDR2 0x1e
	241	#define CONFIG_SYS_I2C_PCA953X_ADDR3 0x1f
	242	#define CONFIG_SYS_I2C_PCA953X_ADDR CONFIG_SYS_I2C_PCA953X_ADDR0
	243
	244	/*
	245	* GPIO pin definitions, PU = pulled high, PD = pulled low
	246	*/
	247	/* PCA9557 @ 0x18*/
	248	#define CONFIG_SYS_PCA953X_C0_SER0_EN 0x01 /* PU; UART0 enable (1: enabled) */
	249	#define CONFIG_SYS_PCA953X_C0_SER0_MODE 0x02 /* PU; UART0 serial mode select (1: RS-485, 0: RS-232) */
	250	#define CONFIG_SYS_PCA953X_C0_SER1_EN 0x04 /* PU; UART1 enable (1: enabled) */
	251	#define CONFIG_SYS_PCA953X_C0_SER1_MODE 0x08 /* PU; UART1 serial mode select (1: RS-485, 0: RS-232) */
	252	#define CONFIG_SYS_PCA953X_C0_FLASH_PASS_CS 0x10 /* PU; Boot flash CS select */
	253	#define CONFIG_SYS_PCA953X_NVM_WP 0x20 /* PU; Write protection (0: disabled, 1: enabled) */
	254
	255	/* PCA9557 @ 0x1e*/
	256	#define CONFIG_SYS_PCA953X_XMC_GA0 0x01 /* PU; */
	257	#define CONFIG_SYS_PCA953X_XMC_GA1 0x02 /* PU; */
	258	#define CONFIG_SYS_PCA953X_XMC_GA2 0x04 /* PU; */
	259	#define CONFIG_SYS_PCA953X_XMC_WAKE 0x10 /* PU; */
	260	#define CONFIG_SYS_PCA953X_XMC_BIST 0x20 /* Enable XMC BIST */
	261	#define CONFIG_SYS_PCA953X_PMC_EREADY 0x40 /* PU; PMC PCI eready */
	262	#define CONFIG_SYS_PCA953X_PMC_MONARCH 0x80 /* PMC monarch mode enable */
	263
	264	/* PCA9557 @ 0x1f */
	265	#define CONFIG_SYS_PCA953X_MC_GPIO0 0x01 /* PU; */
	266	#define CONFIG_SYS_PCA953X_MC_GPIO1 0x02 /* PU; */
	267	#define CONFIG_SYS_PCA953X_MC_GPIO2 0x04 /* PU; */
	268	#define CONFIG_SYS_PCA953X_MC_GPIO3 0x08 /* PU; */
	269	#define CONFIG_SYS_PCA953X_MC_GPIO4 0x10 /* PU; */
	270	#define CONFIG_SYS_PCA953X_MC_GPIO5 0x20 /* PU; */
	271	#define CONFIG_SYS_PCA953X_MC_GPIO6 0x40 /* PU; */
	272	#define CONFIG_SYS_PCA953X_MC_GPIO7 0x80 /* PU; */
	273
	274	/*
	275	* General PCI
	276	* Memory space is mapped 1-1, but I/O space must start from 0.
	277	*/
	278
	279	/* controller 1 - PEX8112 or XMC, depending on build option */
	280	#define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000
	281	#define CONFIG_SYS_PCIE1_MEM_PHYS CONFIG_SYS_PCIE1_MEM_BUS
	282	#define CONFIG_SYS_PCIE1_MEM_SIZE 0x40000000 /* 1G */
	283	#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
284	#define CONFIG_SYS_PCIE1_IO_PHYS 0xe8000000
285	#define CONFIG_SYS_PCIE1_IO_SIZE 0x00800000 /* 8M */
286
bfe18815 JS	287	/*
	288	* Networking options
	289	*/
	290	#define CONFIG_TSEC_ENET /* tsec ethernet support */
bfe18815 JS	291	#define CONFIG_TSEC_TBI
	292	#define CONFIG_MII 1 /* MII PHY management */
	293	#define CONFIG_MII_DEFAULT_TSEC 1 /* Allow unregistered phys */
	294	#define CONFIG_ETHPRIME "eTSEC2"
	295
72c96a68 KG	296	/*
	297	* In-band SGMII auto-negotiation between TBI and BCM5482S PHY fails, force
	298	* 1000mbps SGMII link
	299	*/
	300	#define CONFIG_TSEC_TBICR_SETTINGS ( \
	301	TBICR_PHY_RESET \
	302	\| TBICR_FULL_DUPLEX \
	303	\| TBICR_SPEED1_SET \
	304	)
	305
bfe18815 JS	306	#define CONFIG_TSEC1 1
	307	#define CONFIG_TSEC1_NAME "eTSEC1"
	308	#define TSEC1_FLAGS (TSEC_GIGABIT \| TSEC_REDUCED)
	309	#define TSEC1_PHY_ADDR 1
	310	#define TSEC1_PHYIDX 0
	311	#define CONFIG_HAS_ETH0
	312
	313	#define CONFIG_TSEC2 1
	314	#define CONFIG_TSEC2_NAME "eTSEC2"
	315	#define TSEC2_FLAGS (TSEC_GIGABIT \| TSEC_REDUCED)
	316	#define TSEC2_PHY_ADDR 2
	317	#define TSEC2_PHYIDX 0
	318	#define CONFIG_HAS_ETH1
	319
	320	#define CONFIG_TSEC3 1
	321	#define CONFIG_TSEC3_NAME "eTSEC3"
	322	#define TSEC3_FLAGS (TSEC_GIGABIT \| TSEC_REDUCED)
	323	#define TSEC3_PHY_ADDR 3
	324	#define TSEC3_PHYIDX 0
	325	#define CONFIG_HAS_ETH2
	326
	327	/*
	328	* USB
	329	*/
bfe18815 JS	330	#define CONFIG_USB_EHCI_FSL
bfe18815 JS	331	#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
bfe18815	332
bfe18815 JS	333	/*
	334	* Miscellaneous configurable options
	335	*/
	336	#define CONFIG_SYS_LONGHELP /* undef to save memory */
	337	#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
bfe18815 JS	338	#define CONFIG_CMDLINE_EDITING 1 /* add command line history */
	339	#define CONFIG_AUTO_COMPLETE 1 /* add autocompletion support */
	340	#define CONFIG_LOADADDR 0x1000000 /* default location for tftp and bootm */
bfe18815	341	#define CONFIG_PREBOOT /* enable preboot variable */
bfe18815 JS	342	#define CONFIG_INTEGRITY /* support booting INTEGRITY OS */
	343
	344	/*
	345	* For booting Linux, the board info and command line data
	346	* have to be in the first 16 MB of memory, since this is
	347	* the maximum mapped by the Linux kernel during initialization.
	348	*/
	349	#define CONFIG_SYS_BOOTMAPSZ (16 << 20) /* Initial Memory map for Linux*/
	350	#define CONFIG_SYS_BOOTM_LEN (16 << 20) /* Increase max gunzip size */
	351
bfe18815 JS	352	/*
	353	* Environment Configuration
	354	*/
bfe18815 JS	355	#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128k (one sector) for env */
	356	#define CONFIG_ENV_SIZE 0x8000
	357	#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - (256 * 1024))
	358
	359	/*
	360	* Flash memory map:
	361	* fff80000 - ffffffff Pri U-Boot (512 KB)
	362	* fff40000 - fff7ffff Pri U-Boot Environment (256 KB)
	363	* fff00000 - fff3ffff Pri FDT (256KB)
	364	* fef00000 - ffefffff Pri OS image (16MB)
	365	* f8000000 - feefffff Pri OS Use/Filesystem (111MB)
	366	*
	367	* f7f80000 - f7ffffff Sec U-Boot (512 KB)
	368	* f7f40000 - f7f7ffff Sec U-Boot Environment (256 KB)
	369	* f7f00000 - f7f3ffff Sec FDT (256KB)
	370	* f6f00000 - f7efffff Sec OS image (16MB)
	371	* f0000000 - f6efffff Sec OS Use/Filesystem (111MB)
	372	*/
5368c55d MV	373	#define CONFIG_UBOOT1_ENV_ADDR __stringify(0xfff80000)
	374	#define CONFIG_UBOOT2_ENV_ADDR __stringify(0xf7f80000)
	375	#define CONFIG_FDT1_ENV_ADDR __stringify(0xfff00000)
	376	#define CONFIG_FDT2_ENV_ADDR __stringify(0xf7f00000)
	377	#define CONFIG_OS1_ENV_ADDR __stringify(0xfef00000)
	378	#define CONFIG_OS2_ENV_ADDR __stringify(0xf6f00000)
bfe18815 JS	379
	380	#define CONFIG_PROG_UBOOT1 \
	381	"$download_cmd $loadaddr $ubootfile; " \
	382	"if test $? -eq 0; then " \
	383	"protect off "CONFIG_UBOOT1_ENV_ADDR" +80000; " \
	384	"erase "CONFIG_UBOOT1_ENV_ADDR" +80000; " \
	385	"cp.w $loadaddr "CONFIG_UBOOT1_ENV_ADDR" 40000; " \
	386	"protect on "CONFIG_UBOOT1_ENV_ADDR" +80000; " \
	387	"cmp.b $loadaddr "CONFIG_UBOOT1_ENV_ADDR" 80000; " \
	388	"if test $? -ne 0; then " \
	389	"echo PROGRAM FAILED; " \
	390	"else; " \
	391	"echo PROGRAM SUCCEEDED; " \
	392	"fi; " \
	393	"else; " \
	394	"echo DOWNLOAD FAILED; " \
	395	"fi;"
	396
	397	#define CONFIG_PROG_UBOOT2 \
	398	"$download_cmd $loadaddr $ubootfile; " \
	399	"if test $? -eq 0; then " \
	400	"protect off "CONFIG_UBOOT2_ENV_ADDR" +80000; " \
	401	"erase "CONFIG_UBOOT2_ENV_ADDR" +80000; " \
	402	"cp.w $loadaddr "CONFIG_UBOOT2_ENV_ADDR" 40000; " \
	403	"protect on "CONFIG_UBOOT2_ENV_ADDR" +80000; " \
	404	"cmp.b $loadaddr "CONFIG_UBOOT2_ENV_ADDR" 80000; " \
	405	"if test $? -ne 0; then " \
	406	"echo PROGRAM FAILED; " \
	407	"else; " \
	408	"echo PROGRAM SUCCEEDED; " \
	409	"fi; " \
	410	"else; " \
	411	"echo DOWNLOAD FAILED; " \
	412	"fi;"
	413
	414	#define CONFIG_BOOT_OS_NET \
	415	"$download_cmd $osaddr $osfile; " \
	416	"if test $? -eq 0; then " \
	417	"if test -n $fdtaddr; then " \
	418	"$download_cmd $fdtaddr $fdtfile; " \
	419	"if test $? -eq 0; then " \
	420	"bootm $osaddr - $fdtaddr; " \
	421	"else; " \
	422	"echo FDT DOWNLOAD FAILED; " \
	423	"fi; " \
	424	"else; " \
	425	"bootm $osaddr; " \
	426	"fi; " \
	427	"else; " \
	428	"echo OS DOWNLOAD FAILED; " \
	429	"fi;"
	430
	431	#define CONFIG_PROG_OS1 \
	432	"$download_cmd $osaddr $osfile; " \
	433	"if test $? -eq 0; then " \
	434	"erase "CONFIG_OS1_ENV_ADDR" +$filesize; " \
	435	"cp.b $osaddr "CONFIG_OS1_ENV_ADDR" $filesize; " \
	436	"cmp.b $osaddr "CONFIG_OS1_ENV_ADDR" $filesize; " \
	437	"if test $? -ne 0; then " \
	438	"echo OS PROGRAM FAILED; " \
	439	"else; " \
	440	"echo OS PROGRAM SUCCEEDED; " \
	441	"fi; " \
	442	"else; " \
443	"echo OS DOWNLOAD FAILED; " \
444	"fi;"
445
446	#define CONFIG_PROG_OS2 \
447	"$download_cmd $osaddr $osfile; " \
448	"if test $? -eq 0; then " \
449	"erase "CONFIG_OS2_ENV_ADDR" +$filesize; " \
450	"cp.b $osaddr "CONFIG_OS2_ENV_ADDR" $filesize; " \
451	"cmp.b $osaddr "CONFIG_OS2_ENV_ADDR" $filesize; " \
452	"if test $? -ne 0; then " \
453	"echo OS PROGRAM FAILED; " \
454	"else; " \
455	"echo OS PROGRAM SUCCEEDED; " \
456	"fi; " \
457	"else; " \
458	"echo OS DOWNLOAD FAILED; " \
459	"fi;"
460
461	#define CONFIG_PROG_FDT1 \
462	"$download_cmd $fdtaddr $fdtfile; " \
463	"if test $? -eq 0; then " \
464	"erase "CONFIG_FDT1_ENV_ADDR" +$filesize;" \
465	"cp.b $fdtaddr "CONFIG_FDT1_ENV_ADDR" $filesize; " \
466	"cmp.b $fdtaddr "CONFIG_FDT1_ENV_ADDR" $filesize; " \
467	"if test $? -ne 0; then " \
468	"echo FDT PROGRAM FAILED; " \
469	"else; " \
470	"echo FDT PROGRAM SUCCEEDED; " \
471	"fi; " \
472	"else; " \
473	"echo FDT DOWNLOAD FAILED; " \
474	"fi;"
475
476	#define CONFIG_PROG_FDT2 \
477	"$download_cmd $fdtaddr $fdtfile; " \
478	"if test $? -eq 0; then " \
479	"erase "CONFIG_FDT2_ENV_ADDR" +$filesize;" \
480	"cp.b $fdtaddr "CONFIG_FDT2_ENV_ADDR" $filesize; " \
481	"cmp.b $fdtaddr "CONFIG_FDT2_ENV_ADDR" $filesize; " \
482	"if test $? -ne 0; then " \
483	"echo FDT PROGRAM FAILED; " \
484	"else; " \
485	"echo FDT PROGRAM SUCCEEDED; " \
486	"fi; " \
487	"else; " \
488	"echo FDT DOWNLOAD FAILED; " \
489	"fi;"
490
491	#define CONFIG_EXTRA_ENV_SETTINGS \
492	"autoload=yes\0" \
493	"download_cmd=tftp\0" \
494	"console_args=console=ttyS0,115200\0" \
495	"root_args=root=/dev/nfs rw\0" \
496	"misc_args=ip=on\0" \
497	"set_bootargs=setenv bootargs ${console_args} ${root_args} ${misc_args}\0" \
498	"bootfile=/home/user/file\0" \
499	"osfile=/home/user/board.uImage\0" \
500	"fdtfile=/home/user/board.dtb\0" \
501	"ubootfile=/home/user/u-boot.bin\0" \
b24a4f62	502	"fdtaddr=0x1e00000\0" \
bfe18815 JS	503	"osaddr=0x1000000\0" \
	504	"loadaddr=0x1000000\0" \
	505	"prog_uboot1="CONFIG_PROG_UBOOT1"\0" \
	506	"prog_uboot2="CONFIG_PROG_UBOOT2"\0" \
	507	"prog_os1="CONFIG_PROG_OS1"\0" \
	508	"prog_os2="CONFIG_PROG_OS2"\0" \
	509	"prog_fdt1="CONFIG_PROG_FDT1"\0" \
	510	"prog_fdt2="CONFIG_PROG_FDT2"\0" \
	511	"bootcmd_net=run set_bootargs; "CONFIG_BOOT_OS_NET"\0" \
	512	"bootcmd_flash1=run set_bootargs; " \
	513	"bootm "CONFIG_OS1_ENV_ADDR" - "CONFIG_FDT1_ENV_ADDR"\0"\
	514	"bootcmd_flash2=run set_bootargs; " \
	515	"bootm "CONFIG_OS2_ENV_ADDR" - "CONFIG_FDT2_ENV_ADDR"\0"\
	516	"bootcmd=run bootcmd_flash1\0"
	517	#endif /* __CONFIG_H */