[people/ms/u-boot.git] / include / configs / xupv2p.h

/*
 * (C) Copyright 2007-2008 Michal Simek
 *
 * Michal SIMEK <monstr@monstr.eu>
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */

#ifndef __CONFIG_H
#define __CONFIG_H

#include "../board/xilinx/xupv2p/xparameters.h"

#define	CONFIG_MICROBLAZE	1	/* MicroBlaze CPU */
#define	CONFIG_XUPV2P		1

/* uart */
#ifdef XILINX_UARTLITE_BASEADDR
#define	CONFIG_XILINX_UARTLITE
#define	CONFIG_SERIAL_BASE	XILINX_UARTLITE_BASEADDR
#define	CONFIG_BAUDRATE		XILINX_UARTLITE_BAUDRATE
#define	CFG_BAUDRATE_TABLE	{ CONFIG_BAUDRATE }
#else
#ifdef XILINX_UART16550_BASEADDR
#define CFG_NS16550
#define CFG_NS16550_SERIAL
#define CFG_NS16550_REG_SIZE	4
#define CONFIG_CONS_INDEX	1
#define CFG_NS16550_COM1	XILINX_UART16550_BASEADDR
#define CFG_NS16550_CLK		XILINX_UART16550_CLOCK_HZ
#define	CONFIG_BAUDRATE		115200
#define	CFG_BAUDRATE_TABLE	{ 9600, 115200 }
#endif
#endif

/*
 * setting reset address
 *
 * TEXT_BASE is set to place, where the U-BOOT run in RAM, but
 * if you want to store U-BOOT in flash, set CFG_RESET_ADDRESS
 * to FLASH memory and after loading bitstream jump to FLASH.
 * U-BOOT auto-relocate to TEXT_BASE. After RESET command Microblaze
 * jump to CFG_RESET_ADDRESS where is the original U-BOOT code.
 */
/* #define	CFG_RESET_ADDRESS	0x36000000 */

/* ethernet */
#ifdef XILINX_EMAC_BASEADDR
#define CONFIG_XILINX_EMAC	1
#define CFG_ENET
#else
#ifdef XILINX_EMACLITE_BASEADDR
#define CONFIG_XILINX_EMACLITE	1
#define CFG_ENET
#endif
#endif
#undef ET_DEBUG

/* gpio */
#ifdef XILINX_GPIO_BASEADDR
#define	CFG_GPIO_0		1
#define	CFG_GPIO_0_ADDR		XILINX_GPIO_BASEADDR
#endif

/* interrupt controller */
#ifdef XILINX_INTC_BASEADDR
#define	CFG_INTC_0		1
#define	CFG_INTC_0_ADDR		XILINX_INTC_BASEADDR
#define	CFG_INTC_0_NUM		XILINX_INTC_NUM_INTR_INPUTS
#endif

/* timer */
#ifdef XILINX_TIMER_BASEADDR
#if (XILINX_TIMER_IRQ != -1)
#define	CFG_TIMER_0		1
#define	CFG_TIMER_0_ADDR	XILINX_TIMER_BASEADDR
#define	CFG_TIMER_0_IRQ		XILINX_TIMER_IRQ
#define	FREQUENCE		XILINX_CLOCK_FREQ
#define	CFG_TIMER_0_PRELOAD	( FREQUENCE/1000 )
#endif
#else
#ifdef XILINX_CLOCK_FREQ
#define	CONFIG_XILINX_CLOCK_FREQ	XILINX_CLOCK_FREQ
#else
#error BAD CLOCK FREQ
#endif
#endif
/*
 * memory layout - Example
 * TEXT_BASE = 0x3600_0000;
 * CFG_SRAM_BASE = 0x3000_0000;
 * CFG_SRAM_SIZE = 0x1000_0000;
 *
 * CFG_GBL_DATA_OFFSET = 0x3000_0000 + 0x1000_0000 - 0x1000 = 0x3FFF_F000
 * CFG_MONITOR_BASE = 0x3FFF_F000 - 0x40000 = 0x3FFB_F000
 * CFG_MALLOC_BASE = 0x3FFB_F000 - 0x40000 = 0x3FF7_F000
 *
 * 0x3000_0000	CFG_SDRAM_BASE
 *					FREE
 * 0x3600_0000	TEXT_BASE
 *		U-BOOT code
 * 0x3602_0000
 *					FREE
 *
 *					STACK
 * 0x3FF7_F000	CFG_MALLOC_BASE
 *					MALLOC_AREA	256kB	Alloc
 * 0x3FFB_F000	CFG_MONITOR_BASE
 *					MONITOR_CODE	256kB	Env
 * 0x3FFF_F000	CFG_GBL_DATA_OFFSET
 *					GLOBAL_DATA	4kB	bd, gd
 * 0x4000_0000	CFG_SDRAM_BASE + CFG_SDRAM_SIZE
 */

/* ddr sdram - main memory */
#define	CFG_SDRAM_BASE		XILINX_RAM_START
#define	CFG_SDRAM_SIZE		XILINX_RAM_SIZE
#define	CFG_MEMTEST_START	CFG_SDRAM_BASE
#define	CFG_MEMTEST_END		(CFG_SDRAM_BASE + 0x1000)

/* global pointer */
#define	CFG_GBL_DATA_SIZE	0x1000	/* size of global data */
#define	CFG_GBL_DATA_OFFSET     (CFG_SDRAM_BASE + CFG_SDRAM_SIZE - CFG_GBL_DATA_SIZE) /* start of global data */

/* monitor code */
#define	SIZE			0x40000
#define	CFG_MONITOR_LEN		SIZE
#define	CFG_MONITOR_BASE	(CFG_GBL_DATA_OFFSET - CFG_MONITOR_LEN)
#define	CFG_MONITOR_END		(CFG_MONITOR_BASE + CFG_MONITOR_LEN)
#define	CFG_MALLOC_LEN		SIZE
#define	CFG_MALLOC_BASE		(CFG_MONITOR_BASE - CFG_MALLOC_LEN)

/* stack */
#define	CFG_INIT_SP_OFFSET	CFG_MALLOC_BASE

#define	CFG_NO_FLASH		1
#define	CONFIG_ENV_IS_NOWHERE	1
#define	CONFIG_ENV_SIZE		0x1000
#define	CONFIG_ENV_ADDR		(CFG_MONITOR_BASE - CONFIG_ENV_SIZE)

/*
 * BOOTP options
 */
#define CONFIG_BOOTP_BOOTFILESIZE
#define CONFIG_BOOTP_BOOTPATH
#define CONFIG_BOOTP_GATEWAY
#define CONFIG_BOOTP_HOSTNAME

/*
 * Command line configuration.
 */
#include <config_cmd_default.h>

#undef CONFIG_CMD_FLASH
#undef CONFIG_CMD_JFFS2
#undef CONFIG_CMD_IMLS

#define CONFIG_CMD_ASKENV
#define CONFIG_CMD_CACHE
#define CONFIG_CMD_IRQ

#ifndef CFG_ENET
	#undef CONFIG_CMD_NET
#else
	#define CONFIG_CMD_PING
#endif

#ifdef XILINX_SYSACE_BASEADDR
#define CONFIG_CMD_EXT2
#define CONFIG_CMD_FAT
#endif

/* Miscellaneous configurable options */
#define	CFG_PROMPT	"U-Boot-mONStR> "
#define	CFG_CBSIZE	512	/* size of console buffer */
#define	CFG_PBSIZE	(CFG_CBSIZE + sizeof(CFG_PROMPT) + 16) /* print buffer size */
#define	CFG_MAXARGS	15	/* max number of command args */
#define	CFG_LONGHELP
#define	CFG_LOAD_ADDR	0x12000000 /* default load address */

#define	CONFIG_BOOTDELAY	30
#define	CONFIG_BOOTARGS		"root=romfs"
#define	CONFIG_HOSTNAME		"xupv2p"
#define	CONFIG_BOOTCOMMAND	"base 0;tftp 11000000 image.img;bootm"
#define	CONFIG_IPADDR		192.168.0.3
#define	CONFIG_SERVERIP		192.168.0.5
#define	CONFIG_GATEWAYIP	192.168.0.1
#define	CONFIG_ETHADDR		00:E0:0C:00:00:FD

/* architecture dependent code */
#define	CFG_USR_EXCEP	/* user exception */
#define CFG_HZ	1000

#define CONFIG_PREBOOT	"echo U-BOOT by mONStR;"	\
	"base 0;" \
	"echo"

/* system ace */
#ifdef XILINX_SYSACE_BASEADDR
#define	CONFIG_SYSTEMACE
/* #define DEBUG_SYSTEMACE */
#define	SYSTEMACE_CONFIG_FPGA
#define	CFG_SYSTEMACE_BASE	XILINX_SYSACE_BASEADDR
#define	CFG_SYSTEMACE_WIDTH	XILINX_SYSACE_MEM_WIDTH
#define	CONFIG_DOS_PARTITION
#endif

#define CONFIG_CMDLINE_EDITING
#define CONFIG_OF_LIBFDT	1 /* flat device tree */

#endif	/* __CONFIG_H */
Commit	Line	Data
17980495	1	/*
cf5c679c	2	* (C) Copyright 2007-2008 Michal Simek
17980495 MS	3	*
	4	* Michal SIMEK <monstr@monstr.eu>
	5	*
	6	* See file CREDITS for list of people who contributed to this
	7	* project.
	8	*
	9	* This program is free software; you can redistribute it and/or
	10	* modify it under the terms of the GNU General Public License as
	11	* published by the Free Software Foundation; either version 2 of
	12	* the License, or (at your option) any later version.
	13	*
	14	* This program is distributed in the hope that it will be useful,
	15	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	16	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	17	* GNU General Public License for more details.
	18	*
	19	* You should have received a copy of the GNU General Public License
	20	* along with this program; if not, write to the Free Software
	21	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	22	* MA 02111-1307 USA
	23	*/
	24
	25	#ifndef __CONFIG_H
	26	#define __CONFIG_H
	27
	28	#include "../board/xilinx/xupv2p/xparameters.h"
	29
	30	#define CONFIG_MICROBLAZE 1 /* MicroBlaze CPU */
	31	#define CONFIG_XUPV2P 1
	32
	33	/* uart */
af7ae1a4	34	#ifdef XILINX_UARTLITE_BASEADDR
f8bf9046	35	#define CONFIG_XILINX_UARTLITE
af7ae1a4 MS	36	#define CONFIG_SERIAL_BASE XILINX_UARTLITE_BASEADDR
af7ae1a4 MS	37	#define CONFIG_BAUDRATE XILINX_UARTLITE_BAUDRATE
17980495	38	#define CFG_BAUDRATE_TABLE { CONFIG_BAUDRATE }
af7ae1a4 MS	39	#else
	40	#ifdef XILINX_UART16550_BASEADDR
	41	#define CFG_NS16550
	42	#define CFG_NS16550_SERIAL
	43	#define CFG_NS16550_REG_SIZE 4
	44	#define CONFIG_CONS_INDEX 1
	45	#define CFG_NS16550_COM1 XILINX_UART16550_BASEADDR
	46	#define CFG_NS16550_CLK XILINX_UART16550_CLOCK_HZ
	47	#define CONFIG_BAUDRATE 115200
	48	#define CFG_BAUDRATE_TABLE { 9600, 115200 }
	49	#endif
	50	#endif
17980495	51
17980495 MS	52	/*
17980495 MS	53	* setting reset address
31c98a88	54	*
17980495 MS	55	* TEXT_BASE is set to place, where the U-BOOT run in RAM, but
	56	* if you want to store U-BOOT in flash, set CFG_RESET_ADDRESS
	57	* to FLASH memory and after loading bitstream jump to FLASH.
	58	* U-BOOT auto-relocate to TEXT_BASE. After RESET command Microblaze
	59	* jump to CFG_RESET_ADDRESS where is the original U-BOOT code.
	60	*/
f8bf9046	61	/* #define CFG_RESET_ADDRESS 0x36000000 */
17980495	62
e5845e21 MS	63	/* ethernet */
	64	#ifdef XILINX_EMAC_BASEADDR
	65	#define CONFIG_XILINX_EMAC 1
4d49b280	66	#define CFG_ENET
e5845e21 MS	67	#else
	68	#ifdef XILINX_EMACLITE_BASEADDR
	69	#define CONFIG_XILINX_EMACLITE 1
4d49b280	70	#define CFG_ENET
e5845e21 MS	71	#endif
	72	#endif
	73	#undef ET_DEBUG
	74
17980495	75	/* gpio */
f8bf9046	76	#ifdef XILINX_GPIO_BASEADDR
17980495 MS	77	#define CFG_GPIO_0 1
17980495 MS	78	#define CFG_GPIO_0_ADDR XILINX_GPIO_BASEADDR
f8bf9046	79	#endif
17980495 MS	80
17980495 MS	81	/* interrupt controller */
4d49b280	82	#ifdef XILINX_INTC_BASEADDR
17980495 MS	83	#define CFG_INTC_0 1
	84	#define CFG_INTC_0_ADDR XILINX_INTC_BASEADDR
	85	#define CFG_INTC_0_NUM XILINX_INTC_NUM_INTR_INPUTS
4d49b280	86	#endif
17980495 MS	87
17980495 MS	88	/* timer */
4d49b280 MS	89	#ifdef XILINX_TIMER_BASEADDR
4d49b280 MS	90	#if (XILINX_TIMER_IRQ != -1)
17980495 MS	91	#define CFG_TIMER_0 1
	92	#define CFG_TIMER_0_ADDR XILINX_TIMER_BASEADDR
	93	#define CFG_TIMER_0_IRQ XILINX_TIMER_IRQ
	94	#define FREQUENCE XILINX_CLOCK_FREQ
	95	#define CFG_TIMER_0_PRELOAD ( FREQUENCE/1000 )
4d49b280 MS	96	#endif
	97	#else
	98	#ifdef XILINX_CLOCK_FREQ
f8bf9046	99	#define CONFIG_XILINX_CLOCK_FREQ XILINX_CLOCK_FREQ
4d49b280 MS	100	#else
	101	#error BAD CLOCK FREQ
	102	#endif
	103	#endif
17980495 MS	104	/*
	105	* memory layout - Example
	106	* TEXT_BASE = 0x3600_0000;
	107	* CFG_SRAM_BASE = 0x3000_0000;
	108	* CFG_SRAM_SIZE = 0x1000_0000;
	109	*
	110	* CFG_GBL_DATA_OFFSET = 0x3000_0000 + 0x1000_0000 - 0x1000 = 0x3FFF_F000
	111	* CFG_MONITOR_BASE = 0x3FFF_F000 - 0x40000 = 0x3FFB_F000
	112	* CFG_MALLOC_BASE = 0x3FFB_F000 - 0x40000 = 0x3FF7_F000
	113	*
	114	* 0x3000_0000 CFG_SDRAM_BASE
	115	* FREE
	116	* 0x3600_0000 TEXT_BASE
	117	* U-BOOT code
	118	* 0x3602_0000
	119	* FREE
	120	*
	121	* STACK
	122	* 0x3FF7_F000 CFG_MALLOC_BASE
	123	* MALLOC_AREA 256kB Alloc
	124	* 0x3FFB_F000 CFG_MONITOR_BASE
	125	* MONITOR_CODE 256kB Env
	126	* 0x3FFF_F000 CFG_GBL_DATA_OFFSET
53677ef1	127	* GLOBAL_DATA 4kB bd, gd
17980495 MS	128	* 0x4000_0000 CFG_SDRAM_BASE + CFG_SDRAM_SIZE
	129	*/
	130
	131	/* ddr sdram - main memory */
	132	#define CFG_SDRAM_BASE XILINX_RAM_START
	133	#define CFG_SDRAM_SIZE XILINX_RAM_SIZE
	134	#define CFG_MEMTEST_START CFG_SDRAM_BASE
	135	#define CFG_MEMTEST_END (CFG_SDRAM_BASE + 0x1000)
	136
	137	/* global pointer */
	138	#define CFG_GBL_DATA_SIZE 0x1000 /* size of global data */
	139	#define CFG_GBL_DATA_OFFSET (CFG_SDRAM_BASE + CFG_SDRAM_SIZE - CFG_GBL_DATA_SIZE) /* start of global data */
	140
	141	/* monitor code */
	142	#define SIZE 0x40000
	143	#define CFG_MONITOR_LEN SIZE
	144	#define CFG_MONITOR_BASE (CFG_GBL_DATA_OFFSET - CFG_MONITOR_LEN)
	145	#define CFG_MONITOR_END (CFG_MONITOR_BASE + CFG_MONITOR_LEN)
	146	#define CFG_MALLOC_LEN SIZE
	147	#define CFG_MALLOC_BASE (CFG_MONITOR_BASE - CFG_MALLOC_LEN)
	148
	149	/* stack */
	150	#define CFG_INIT_SP_OFFSET CFG_MALLOC_BASE
	151
	152	#define CFG_NO_FLASH 1
93f6d725	153	#define CONFIG_ENV_IS_NOWHERE 1
0e8d1586 JCPV	154	#define CONFIG_ENV_SIZE 0x1000
0e8d1586 JCPV	155	#define CONFIG_ENV_ADDR (CFG_MONITOR_BASE - CONFIG_ENV_SIZE)
17980495	156
079a136c JL	157	/*
	158	* BOOTP options
	159	*/
	160	#define CONFIG_BOOTP_BOOTFILESIZE
	161	#define CONFIG_BOOTP_BOOTPATH
	162	#define CONFIG_BOOTP_GATEWAY
	163	#define CONFIG_BOOTP_HOSTNAME
	164
dca3b3d6 JL	165	/*
	166	* Command line configuration.
	167	*/
	168	#include <config_cmd_default.h>
	169
f8bf9046	170	#undef CONFIG_CMD_FLASH
cf5c679c	171	#undef CONFIG_CMD_JFFS2
f8bf9046 MS	172	#undef CONFIG_CMD_IMLS
f8bf9046 MS	173
b90c045f	174	#define CONFIG_CMD_ASKENV
f8bf9046 MS	175	#define CONFIG_CMD_CACHE
f8bf9046 MS	176	#define CONFIG_CMD_IRQ
4d49b280 MS	177
	178	#ifndef CFG_ENET
	179	#undef CONFIG_CMD_NET
	180	#else
	181	#define CONFIG_CMD_PING
	182	#endif
dca3b3d6	183
f8bf9046 MS	184	#ifdef XILINX_SYSACE_BASEADDR
	185	#define CONFIG_CMD_EXT2
	186	#define CONFIG_CMD_FAT
	187	#endif
17980495 MS	188
	189	/* Miscellaneous configurable options */
	190	#define CFG_PROMPT "U-Boot-mONStR> "
	191	#define CFG_CBSIZE 512 /* size of console buffer */
	192	#define CFG_PBSIZE (CFG_CBSIZE + sizeof(CFG_PROMPT) + 16) /* print buffer size */
	193	#define CFG_MAXARGS 15 /* max number of command args */
	194	#define CFG_LONGHELP
	195	#define CFG_LOAD_ADDR 0x12000000 /* default load address */
	196
53677ef1	197	#define CONFIG_BOOTDELAY 30
17980495	198	#define CONFIG_BOOTARGS "root=romfs"
f8bf9046	199	#define CONFIG_HOSTNAME "xupv2p"
53677ef1	200	#define CONFIG_BOOTCOMMAND "base 0;tftp 11000000 image.img;bootm"
17980495	201	#define CONFIG_IPADDR 192.168.0.3
53677ef1 WD	202	#define CONFIG_SERVERIP 192.168.0.5
53677ef1 WD	203	#define CONFIG_GATEWAYIP 192.168.0.1
17980495 MS	204	#define CONFIG_ETHADDR 00:E0:0C:00:00:FD
	205
	206	/* architecture dependent code */
	207	#define CFG_USR_EXCEP /* user exception */
	208	#define CFG_HZ 1000
	209
	210	#define CONFIG_PREBOOT "echo U-BOOT by mONStR;" \
	211	"base 0;" \
	212	"echo"
	213
17980495	214	/* system ace */
f8bf9046	215	#ifdef XILINX_SYSACE_BASEADDR
32556443 MS	216	#define CONFIG_SYSTEMACE
	217	/* #define DEBUG_SYSTEMACE */
	218	#define SYSTEMACE_CONFIG_FPGA
	219	#define CFG_SYSTEMACE_BASE XILINX_SYSACE_BASEADDR
	220	#define CFG_SYSTEMACE_WIDTH XILINX_SYSACE_MEM_WIDTH
	221	#define CONFIG_DOS_PARTITION
f8bf9046	222	#endif
17980495	223
cf5c679c MS	224	#define CONFIG_CMDLINE_EDITING
	225	#define CONFIG_OF_LIBFDT 1 /* flat device tree */
	226
17980495	227	#endif /* __CONFIG_H */