[people/ms/u-boot.git] / include / configs / zmx25.h

/*
 * (c) 2011 Graf-Syteco, Matthias Weisser
 * <weisserm@arcor.de>
 *
 * Configuation settings for the zmx25 board
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

#ifndef __CONFIG_H
#define __CONFIG_H

#include <asm/arch/imx-regs.h>

#define CONFIG_MX25
#define CONFIG_SYS_TEXT_BASE		0xA0000000

#define CONFIG_SYS_TIMER_RATE		32768
#define CONFIG_SYS_TIMER_COUNTER	\
	(&((struct gpt_regs *)IMX_GPT1_BASE)->counter)

#define CONFIG_MACH_TYPE	MACH_TYPE_ZMX25
/*
 * Environment settings
 */
#define CONFIG_EXTRA_ENV_SETTINGS \
	"gs_fast_boot=setenv bootdelay 5\0" \
	"gs_slow_boot=setenv bootdelay 10\0" \
	"bootcmd=dcache off; mw.l 0x81000000 0 1024; usb start;" \
		"fatls usb 0; fatload usb 0 0x81000000 zmx25-init.bin;" \
		"bootm 0x81000000; bootelf 0x81000000\0"

#define CONFIG_CMDLINE_TAG		/* enable passing of ATAGs	*/
#define CONFIG_SETUP_MEMORY_TAGS
#define CONFIG_INITRD_TAG

/*
 * Compressions
 */
#define CONFIG_LZO

/*
 * Hardware drivers
 */

/*
 * GPIO
 */
#define CONFIG_MXC_GPIO

/*
 * Serial
 */
#define CONFIG_MXC_UART
#define CONFIG_MXC_UART_BASE	UART2_BASE
#define CONFIG_CONS_INDEX	1	/* use UART2 for console */
#define CONFIG_BAUDRATE		115200	/* Default baud rate */

/*
 * Ethernet
 */
#define CONFIG_FEC_MXC
#define CONFIG_FEC_MXC_PHYADDR		0x00
#define CONFIG_MII

/*
 * BOOTP options
 */
#define CONFIG_BOOTP_BOOTFILESIZE
#define CONFIG_BOOTP_BOOTPATH
#define CONFIG_BOOTP_GATEWAY
#define CONFIG_BOOTP_HOSTNAME

/*
 * Command line configuration.
 */

/*
 * Additional command
 */

/*
 * USB
 */
#ifdef CONFIG_CMD_USB
#define CONFIG_USB_EHCI			/* Enable EHCI USB support */
#define CONFIG_USB_EHCI_MXC
#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
#define CONFIG_MXC_USB_PORT	1
#define CONFIG_MXC_USB_PORTSC	MXC_EHCI_MODE_SERIAL
#define CONFIG_MXC_USB_FLAGS	(MXC_EHCI_INTERNAL_PHY | MXC_EHCI_IPPUE_DOWN)
#define CONFIG_EHCI_IS_TDI
#define CONFIG_SUPPORT_VFAT
#endif /* CONFIG_CMD_USB */

/* SDRAM */
#define CONFIG_NR_DRAM_BANKS	1
#define PHYS_SDRAM		0x80000000	/* start address of LPDDRRAM */
#define PHYS_SDRAM_SIZE		0x04000000	/* 64 megs */

#define CONFIG_SYS_SDRAM_BASE	PHYS_SDRAM
#define CONFIG_SYS_INIT_SP_ADDR	0x78020000	/* end of internal SRAM */

/*
 * FLASH and environment organization
 */
#define CONFIG_SYS_FLASH_BASE		0xA0000000
#define CONFIG_SYS_MAX_FLASH_BANKS	1
#define CONFIG_SYS_MAX_FLASH_SECT	256

#define CONFIG_ENV_ADDR			(CONFIG_SYS_FLASH_BASE + 0x00040000)
#define CONFIG_ENV_IS_IN_FLASH		1
#define CONFIG_ENV_SECT_SIZE		(128 * 1024)
#define CONFIG_ENV_SIZE			(128 * 1024)

/*
 * CFI FLASH driver setup
 */
#define CONFIG_SYS_FLASH_CFI
#define CONFIG_FLASH_CFI_DRIVER
#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE	/* ~10x faster */

#define CONFIG_SYS_LOAD_ADDR		CONFIG_SYS_SDRAM_BASE

#define CONFIG_SYS_MEMTEST_START	(PHYS_SDRAM + (512*1024))
#define CONFIG_SYS_MEMTEST_END		(PHYS_SDRAM + PHYS_SDRAM_SIZE)

#define CONFIG_SYS_CBSIZE	256
#define CONFIG_SYS_MAXARGS	16
#define CONFIG_SYS_PBSIZE	(CONFIG_SYS_CBSIZE + \
				sizeof(CONFIG_SYS_PROMPT) + 16)
#define CONFIG_SYS_LONGHELP
#define CONFIG_CMDLINE_EDITING

#define CONFIG_PREBOOT  ""


/*
 * Size of malloc() pool
 */
#define CONFIG_SYS_MALLOC_LEN		(0x400000 - 0x8000)

#endif	/* __CONFIG_H */
Commit	Line	Data
39f0023e MW	1	/*
	2	* (c) 2011 Graf-Syteco, Matthias Weisser
	3	* <weisserm@arcor.de>
	4	*
	5	* Configuation settings for the zmx25 board
	6	*
1a459660	7	* SPDX-License-Identifier: GPL-2.0+
39f0023e MW	8	*/
	9
	10	#ifndef __CONFIG_H
	11	#define __CONFIG_H
	12
3dae5b51 RH	13	#include <asm/arch/imx-regs.h>
3dae5b51 RH	14
39f0023e	15	#define CONFIG_MX25
39f0023e MW	16	#define CONFIG_SYS_TEXT_BASE 0xA0000000
39f0023e MW	17
3dae5b51 RH	18	#define CONFIG_SYS_TIMER_RATE 32768
	19	#define CONFIG_SYS_TIMER_COUNTER \
	20	(&((struct gpt_regs *)IMX_GPT1_BASE)->counter)
	21
94ba26f2	22	#define CONFIG_MACH_TYPE MACH_TYPE_ZMX25
39f0023e MW	23	/*
	24	* Environment settings
	25	*/
	26	#define CONFIG_EXTRA_ENV_SETTINGS \
	27	"gs_fast_boot=setenv bootdelay 5\0" \
	28	"gs_slow_boot=setenv bootdelay 10\0" \
	29	"bootcmd=dcache off; mw.l 0x81000000 0 1024; usb start;" \
	30	"fatls usb 0; fatload usb 0 0x81000000 zmx25-init.bin;" \
	31	"bootm 0x81000000; bootelf 0x81000000\0"
	32
	33	#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */
	34	#define CONFIG_SETUP_MEMORY_TAGS
	35	#define CONFIG_INITRD_TAG
39f0023e MW	36
	37	/*
	38	* Compressions
	39	*/
	40	#define CONFIG_LZO
	41
	42	/*
	43	* Hardware drivers
	44	*/
	45
	46	/*
	47	* GPIO
	48	*/
	49	#define CONFIG_MXC_GPIO
	50
	51	/*
	52	* Serial
	53	*/
	54	#define CONFIG_MXC_UART
40f6fffe	55	#define CONFIG_MXC_UART_BASE UART2_BASE
39f0023e MW	56	#define CONFIG_CONS_INDEX 1 /* use UART2 for console */
39f0023e MW	57	#define CONFIG_BAUDRATE 115200 /* Default baud rate */
39f0023e MW	58
	59	/*
	60	* Ethernet
	61	*/
	62	#define CONFIG_FEC_MXC
	63	#define CONFIG_FEC_MXC_PHYADDR 0x00
	64	#define CONFIG_MII
39f0023e MW	65
	66	/*
	67	* BOOTP options
	68	*/
	69	#define CONFIG_BOOTP_BOOTFILESIZE
	70	#define CONFIG_BOOTP_BOOTPATH
	71	#define CONFIG_BOOTP_GATEWAY
	72	#define CONFIG_BOOTP_HOSTNAME
	73
	74	/*
	75	* Command line configuration.
	76	*/
39f0023e	77
39f0023e MW	78	/*
	79	* Additional command
	80	*/
39f0023e	81
39f0023e MW	82	/*
	83	* USB
	84	*/
	85	#ifdef CONFIG_CMD_USB
	86	#define CONFIG_USB_EHCI /* Enable EHCI USB support */
	87	#define CONFIG_USB_EHCI_MXC
	88	#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
9fa3d093 BT	89	#define CONFIG_MXC_USB_PORT 1
	90	#define CONFIG_MXC_USB_PORTSC MXC_EHCI_MODE_SERIAL
	91	#define CONFIG_MXC_USB_FLAGS (MXC_EHCI_INTERNAL_PHY \| MXC_EHCI_IPPUE_DOWN)
39f0023e	92	#define CONFIG_EHCI_IS_TDI
39f0023e MW	93	#define CONFIG_SUPPORT_VFAT
	94	#endif /* CONFIG_CMD_USB */
	95
	96	/* SDRAM */
	97	#define CONFIG_NR_DRAM_BANKS 1
	98	#define PHYS_SDRAM 0x80000000 /* start address of LPDDRRAM */
	99	#define PHYS_SDRAM_SIZE 0x04000000 /* 64 megs */
	100
	101	#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM
	102	#define CONFIG_SYS_INIT_SP_ADDR 0x78020000 /* end of internal SRAM */
	103
	104	/*
	105	* FLASH and environment organization
	106	*/
	107	#define CONFIG_SYS_FLASH_BASE 0xA0000000
	108	#define CONFIG_SYS_MAX_FLASH_BANKS 1
	109	#define CONFIG_SYS_MAX_FLASH_SECT 256
	110
	111	#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x00040000)
	112	#define CONFIG_ENV_IS_IN_FLASH 1
	113	#define CONFIG_ENV_SECT_SIZE (128 * 1024)
	114	#define CONFIG_ENV_SIZE (128 * 1024)
	115
	116	/*
	117	* CFI FLASH driver setup
	118	*/
	119	#define CONFIG_SYS_FLASH_CFI
	120	#define CONFIG_FLASH_CFI_DRIVER
	121	#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE /* ~10x faster */
	122
	123	#define CONFIG_SYS_LOAD_ADDR CONFIG_SYS_SDRAM_BASE
	124
	125	#define CONFIG_SYS_MEMTEST_START (PHYS_SDRAM + (512*1024))
	126	#define CONFIG_SYS_MEMTEST_END (PHYS_SDRAM + PHYS_SDRAM_SIZE)
	127
39f0023e MW	128	#define CONFIG_SYS_CBSIZE 256
	129	#define CONFIG_SYS_MAXARGS 16
	130	#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
	131	sizeof(CONFIG_SYS_PROMPT) + 16)
	132	#define CONFIG_SYS_LONGHELP
	133	#define CONFIG_CMDLINE_EDITING
	134
	135	#define CONFIG_PREBOOT ""
	136
39f0023e MW	137
	138	/*
	139	* Size of malloc() pool
	140	*/
	141	#define CONFIG_SYS_MALLOC_LEN (0x400000 - 0x8000)
39f0023e MW	142
39f0023e MW	143	#endif /* __CONFIG_H */