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6c9a1003 VM |
1 | #ifndef DT_BINDINGS_STM32_SDRAM_H |
2 | #define DT_BINDINGS_STM32_SDRAM_H | |
3 | ||
4 | #define NO_COL_8 0x0 | |
5 | #define NO_COL_9 0x1 | |
6 | #define NO_COL_10 0x2 | |
7 | #define NO_COL_11 0x3 | |
8 | ||
9 | #define NO_ROW_11 0x0 | |
10 | #define NO_ROW_12 0x1 | |
11 | #define NO_ROW_13 0x2 | |
12 | ||
13 | #define MWIDTH_8 0x0 | |
14 | #define MWIDTH_16 0x1 | |
15 | #define MWIDTH_32 0x2 | |
16 | #define BANKS_2 0x0 | |
17 | #define BANKS_4 0x1 | |
18 | #define CAS_1 0x1 | |
19 | #define CAS_2 0x2 | |
20 | #define CAS_3 0x3 | |
a1e384b4 | 21 | #define SDCLK_DIS 0x0 |
bfea69ad | 22 | #define SDCLK_2 0x2 |
a1e384b4 | 23 | #define SDCLK_3 0x3 |
6c9a1003 VM |
24 | #define RD_BURST_EN 0x1 |
25 | #define RD_BURST_DIS 0x0 | |
26 | #define RD_PIPE_DL_0 0x0 | |
27 | #define RD_PIPE_DL_1 0x1 | |
28 | #define RD_PIPE_DL_2 0x2 | |
29 | ||
bfea69ad | 30 | /* Timing = value +1 cycles */ |
a1e384b4 | 31 | #define TMRD_1 (1 - 1) |
bfea69ad | 32 | #define TMRD_2 (2 - 1) |
791651e3 | 33 | #define TMRD_3 (3 - 1) |
a1e384b4 | 34 | #define TXSR_1 (1 - 1) |
bfea69ad | 35 | #define TXSR_6 (6 - 1) |
791651e3 | 36 | #define TXSR_7 (7 - 1) |
a1e384b4 | 37 | #define TRAS_1 (1 - 1) |
bfea69ad VM |
38 | #define TRAS_4 (4 - 1) |
39 | #define TRC_6 (6 - 1) | |
a1e384b4 | 40 | #define TWR_1 (1 - 1) |
bfea69ad VM |
41 | #define TWR_2 (2 - 1) |
42 | #define TRP_2 (2 - 1) | |
a1e384b4 | 43 | #define TRCD_1 (1 - 1) |
bfea69ad | 44 | #define TRCD_2 (2 - 1) |
6c9a1003 VM |
45 | |
46 | #endif |