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d789b5f5 DD |
1 | /* |
2 | * Copyright 2010-2011 Freescale Semiconductor, Inc. | |
3 | * Author: Dipen Dudhat <dipen.dudhat@freescale.com> | |
4 | * | |
1a459660 | 5 | * SPDX-License-Identifier: GPL-2.0+ |
d789b5f5 DD |
6 | */ |
7 | ||
0b66513b YS |
8 | #ifndef __FSL_IFC_H |
9 | #define __FSL_IFC_H | |
d789b5f5 | 10 | |
362ee04b | 11 | #ifdef CONFIG_FSL_IFC |
d789b5f5 DD |
12 | #include <config.h> |
13 | #include <common.h> | |
14 | ||
15 | /* | |
16 | * CSPR - Chip Select Property Register | |
17 | */ | |
18 | #define CSPR_BA 0xFFFF0000 | |
19 | #define CSPR_BA_SHIFT 16 | |
20 | #define CSPR_PORT_SIZE 0x00000180 | |
21 | #define CSPR_PORT_SIZE_SHIFT 7 | |
22 | /* Port Size 8 bit */ | |
23 | #define CSPR_PORT_SIZE_8 0x00000080 | |
24 | /* Port Size 16 bit */ | |
25 | #define CSPR_PORT_SIZE_16 0x00000100 | |
26 | /* Port Size 32 bit */ | |
27 | #define CSPR_PORT_SIZE_32 0x00000180 | |
28 | /* Write Protect */ | |
29 | #define CSPR_WP 0x00000040 | |
30 | #define CSPR_WP_SHIFT 6 | |
31 | /* Machine Select */ | |
32 | #define CSPR_MSEL 0x00000006 | |
33 | #define CSPR_MSEL_SHIFT 1 | |
34 | /* NOR */ | |
35 | #define CSPR_MSEL_NOR 0x00000000 | |
36 | /* NAND */ | |
37 | #define CSPR_MSEL_NAND 0x00000002 | |
38 | /* GPCM */ | |
39 | #define CSPR_MSEL_GPCM 0x00000004 | |
40 | /* Bank Valid */ | |
41 | #define CSPR_V 0x00000001 | |
42 | #define CSPR_V_SHIFT 0 | |
43 | ||
44 | /* Convert an address into the right format for the CSPR Registers */ | |
45 | #define CSPR_PHYS_ADDR(x) (((uint64_t)x) & 0xffff0000) | |
46 | ||
47 | /* | |
48 | * Address Mask Register | |
49 | */ | |
50 | #define IFC_AMASK_MASK 0xFFFF0000 | |
51 | #define IFC_AMASK_SHIFT 16 | |
52 | #define IFC_AMASK(n) (IFC_AMASK_MASK << \ | |
53 | (__ilog2(n) - IFC_AMASK_SHIFT)) | |
54 | ||
55 | /* | |
56 | * Chip Select Option Register IFC_NAND Machine | |
57 | */ | |
58 | /* Enable ECC Encoder */ | |
59 | #define CSOR_NAND_ECC_ENC_EN 0x80000000 | |
52f90dad | 60 | #define CSOR_NAND_ECC_MODE_MASK 0x30000000 |
d789b5f5 DD |
61 | /* 4 bit correction per 520 Byte sector */ |
62 | #define CSOR_NAND_ECC_MODE_4 0x00000000 | |
63 | /* 8 bit correction per 528 Byte sector */ | |
64 | #define CSOR_NAND_ECC_MODE_8 0x10000000 | |
65 | /* Enable ECC Decoder */ | |
66 | #define CSOR_NAND_ECC_DEC_EN 0x04000000 | |
67 | /* Row Address Length */ | |
68 | #define CSOR_NAND_RAL_MASK 0x01800000 | |
69 | #define CSOR_NAND_RAL_SHIFT 20 | |
70 | #define CSOR_NAND_RAL_1 0x00000000 | |
71 | #define CSOR_NAND_RAL_2 0x00800000 | |
72 | #define CSOR_NAND_RAL_3 0x01000000 | |
73 | #define CSOR_NAND_RAL_4 0x01800000 | |
74 | /* Page Size 512b, 2k, 4k */ | |
75 | #define CSOR_NAND_PGS_MASK 0x00180000 | |
76 | #define CSOR_NAND_PGS_SHIFT 16 | |
77 | #define CSOR_NAND_PGS_512 0x00000000 | |
78 | #define CSOR_NAND_PGS_2K 0x00080000 | |
79 | #define CSOR_NAND_PGS_4K 0x00100000 | |
71220f80 | 80 | #define CSOR_NAND_PGS_8K 0x00180000 |
d789b5f5 DD |
81 | /* Spare region Size */ |
82 | #define CSOR_NAND_SPRZ_MASK 0x0000E000 | |
83 | #define CSOR_NAND_SPRZ_SHIFT 13 | |
84 | #define CSOR_NAND_SPRZ_16 0x00000000 | |
85 | #define CSOR_NAND_SPRZ_64 0x00002000 | |
86 | #define CSOR_NAND_SPRZ_128 0x00004000 | |
87 | #define CSOR_NAND_SPRZ_210 0x00006000 | |
88 | #define CSOR_NAND_SPRZ_218 0x00008000 | |
89 | #define CSOR_NAND_SPRZ_224 0x0000A000 | |
71220f80 | 90 | #define CSOR_NAND_SPRZ_CSOR_EXT 0x0000C000 |
d789b5f5 DD |
91 | /* Pages Per Block */ |
92 | #define CSOR_NAND_PB_MASK 0x00000700 | |
93 | #define CSOR_NAND_PB_SHIFT 8 | |
94 | #define CSOR_NAND_PB(n) ((__ilog2(n) - 5) << CSOR_NAND_PB_SHIFT) | |
95 | /* Time for Read Enable High to Output High Impedance */ | |
96 | #define CSOR_NAND_TRHZ_MASK 0x0000001C | |
97 | #define CSOR_NAND_TRHZ_SHIFT 2 | |
98 | #define CSOR_NAND_TRHZ_20 0x00000000 | |
99 | #define CSOR_NAND_TRHZ_40 0x00000004 | |
100 | #define CSOR_NAND_TRHZ_60 0x00000008 | |
101 | #define CSOR_NAND_TRHZ_80 0x0000000C | |
102 | #define CSOR_NAND_TRHZ_100 0x00000010 | |
103 | /* Buffer control disable */ | |
104 | #define CSOR_NAND_BCTLD 0x00000001 | |
105 | ||
106 | /* | |
107 | * Chip Select Option Register - NOR Flash Mode | |
108 | */ | |
109 | /* Enable Address shift Mode */ | |
110 | #define CSOR_NOR_ADM_SHFT_MODE_EN 0x80000000 | |
111 | /* Page Read Enable from NOR device */ | |
112 | #define CSOR_NOR_PGRD_EN 0x10000000 | |
113 | /* AVD Toggle Enable during Burst Program */ | |
114 | #define CSOR_NOR_AVD_TGL_PGM_EN 0x01000000 | |
115 | /* Address Data Multiplexing Shift */ | |
116 | #define CSOR_NOR_ADM_MASK 0x0003E000 | |
117 | #define CSOR_NOR_ADM_SHIFT_SHIFT 13 | |
118 | #define CSOR_NOR_ADM_SHIFT(n) ((n) << CSOR_NOR_ADM_SHIFT_SHIFT) | |
119 | /* Type of the NOR device hooked */ | |
120 | #define CSOR_NOR_NOR_MODE_AYSNC_NOR 0x00000000 | |
121 | #define CSOR_NOR_NOR_MODE_AVD_NOR 0x00000020 | |
122 | /* Time for Read Enable High to Output High Impedance */ | |
123 | #define CSOR_NOR_TRHZ_MASK 0x0000001C | |
124 | #define CSOR_NOR_TRHZ_SHIFT 2 | |
125 | #define CSOR_NOR_TRHZ_20 0x00000000 | |
126 | #define CSOR_NOR_TRHZ_40 0x00000004 | |
127 | #define CSOR_NOR_TRHZ_60 0x00000008 | |
128 | #define CSOR_NOR_TRHZ_80 0x0000000C | |
129 | #define CSOR_NOR_TRHZ_100 0x00000010 | |
130 | /* Buffer control disable */ | |
131 | #define CSOR_NOR_BCTLD 0x00000001 | |
132 | ||
133 | /* | |
134 | * Chip Select Option Register - GPCM Mode | |
135 | */ | |
136 | /* GPCM Mode - Normal */ | |
137 | #define CSOR_GPCM_GPMODE_NORMAL 0x00000000 | |
138 | /* GPCM Mode - GenericASIC */ | |
139 | #define CSOR_GPCM_GPMODE_ASIC 0x80000000 | |
140 | /* Parity Mode odd/even */ | |
141 | #define CSOR_GPCM_PARITY_EVEN 0x40000000 | |
142 | /* Parity Checking enable/disable */ | |
143 | #define CSOR_GPCM_PAR_EN 0x20000000 | |
144 | /* GPCM Timeout Count */ | |
145 | #define CSOR_GPCM_GPTO_MASK 0x0F000000 | |
146 | #define CSOR_GPCM_GPTO_SHIFT 24 | |
147 | #define CSOR_GPCM_GPTO(n) ((__ilog2(n) - 8) << CSOR_GPCM_GPTO_SHIFT) | |
148 | /* GPCM External Access Termination mode for read access */ | |
149 | #define CSOR_GPCM_RGETA_EXT 0x00080000 | |
150 | /* GPCM External Access Termination mode for write access */ | |
151 | #define CSOR_GPCM_WGETA_EXT 0x00040000 | |
152 | /* Address Data Multiplexing Shift */ | |
153 | #define CSOR_GPCM_ADM_MASK 0x0003E000 | |
154 | #define CSOR_GPCM_ADM_SHIFT_SHIFT 13 | |
155 | #define CSOR_GPCM_ADM_SHIFT(n) ((n) << CSOR_GPCM_ADM_SHIFT_SHIFT) | |
156 | /* Generic ASIC Parity error indication delay */ | |
157 | #define CSOR_GPCM_GAPERRD_MASK 0x00000180 | |
158 | #define CSOR_GPCM_GAPERRD_SHIFT 7 | |
159 | #define CSOR_GPCM_GAPERRD(n) (((n) - 1) << CSOR_GPCM_GAPERRD_SHIFT) | |
160 | /* Time for Read Enable High to Output High Impedance */ | |
161 | #define CSOR_GPCM_TRHZ_MASK 0x0000001C | |
162 | #define CSOR_GPCM_TRHZ_20 0x00000000 | |
163 | #define CSOR_GPCM_TRHZ_40 0x00000004 | |
164 | #define CSOR_GPCM_TRHZ_60 0x00000008 | |
165 | #define CSOR_GPCM_TRHZ_80 0x0000000C | |
166 | #define CSOR_GPCM_TRHZ_100 0x00000010 | |
167 | /* Buffer control disable */ | |
168 | #define CSOR_GPCM_BCTLD 0x00000001 | |
169 | ||
170 | /* | |
171 | * Flash Timing Registers (FTIM0 - FTIM2_CSn) | |
172 | */ | |
173 | /* | |
174 | * FTIM0 - NAND Flash Mode | |
175 | */ | |
176 | #define FTIM0_NAND 0x7EFF3F3F | |
177 | #define FTIM0_NAND_TCCST_SHIFT 25 | |
178 | #define FTIM0_NAND_TCCST(n) ((n) << FTIM0_NAND_TCCST_SHIFT) | |
179 | #define FTIM0_NAND_TWP_SHIFT 16 | |
180 | #define FTIM0_NAND_TWP(n) ((n) << FTIM0_NAND_TWP_SHIFT) | |
181 | #define FTIM0_NAND_TWCHT_SHIFT 8 | |
182 | #define FTIM0_NAND_TWCHT(n) ((n) << FTIM0_NAND_TWCHT_SHIFT) | |
183 | #define FTIM0_NAND_TWH_SHIFT 0 | |
184 | #define FTIM0_NAND_TWH(n) ((n) << FTIM0_NAND_TWH_SHIFT) | |
185 | /* | |
186 | * FTIM1 - NAND Flash Mode | |
187 | */ | |
188 | #define FTIM1_NAND 0xFFFF3FFF | |
189 | #define FTIM1_NAND_TADLE_SHIFT 24 | |
190 | #define FTIM1_NAND_TADLE(n) ((n) << FTIM1_NAND_TADLE_SHIFT) | |
191 | #define FTIM1_NAND_TWBE_SHIFT 16 | |
192 | #define FTIM1_NAND_TWBE(n) ((n) << FTIM1_NAND_TWBE_SHIFT) | |
193 | #define FTIM1_NAND_TRR_SHIFT 8 | |
194 | #define FTIM1_NAND_TRR(n) ((n) << FTIM1_NAND_TRR_SHIFT) | |
195 | #define FTIM1_NAND_TRP_SHIFT 0 | |
196 | #define FTIM1_NAND_TRP(n) ((n) << FTIM1_NAND_TRP_SHIFT) | |
197 | /* | |
198 | * FTIM2 - NAND Flash Mode | |
199 | */ | |
200 | #define FTIM2_NAND 0x1FE1F8FF | |
201 | #define FTIM2_NAND_TRAD_SHIFT 21 | |
202 | #define FTIM2_NAND_TRAD(n) ((n) << FTIM2_NAND_TRAD_SHIFT) | |
203 | #define FTIM2_NAND_TREH_SHIFT 11 | |
204 | #define FTIM2_NAND_TREH(n) ((n) << FTIM2_NAND_TREH_SHIFT) | |
205 | #define FTIM2_NAND_TWHRE_SHIFT 0 | |
206 | #define FTIM2_NAND_TWHRE(n) ((n) << FTIM2_NAND_TWHRE_SHIFT) | |
207 | /* | |
208 | * FTIM3 - NAND Flash Mode | |
209 | */ | |
210 | #define FTIM3_NAND 0xFF000000 | |
211 | #define FTIM3_NAND_TWW_SHIFT 24 | |
212 | #define FTIM3_NAND_TWW(n) ((n) << FTIM3_NAND_TWW_SHIFT) | |
213 | ||
214 | /* | |
215 | * FTIM0 - NOR Flash Mode | |
216 | */ | |
217 | #define FTIM0_NOR 0xF03F3F3F | |
218 | #define FTIM0_NOR_TACSE_SHIFT 28 | |
219 | #define FTIM0_NOR_TACSE(n) ((n) << FTIM0_NOR_TACSE_SHIFT) | |
220 | #define FTIM0_NOR_TEADC_SHIFT 16 | |
221 | #define FTIM0_NOR_TEADC(n) ((n) << FTIM0_NOR_TEADC_SHIFT) | |
222 | #define FTIM0_NOR_TAVDS_SHIFT 8 | |
223 | #define FTIM0_NOR_TAVDS(n) ((n) << FTIM0_NOR_TAVDS_SHIFT) | |
224 | #define FTIM0_NOR_TEAHC_SHIFT 0 | |
225 | #define FTIM0_NOR_TEAHC(n) ((n) << FTIM0_NOR_TEAHC_SHIFT) | |
226 | /* | |
227 | * FTIM1 - NOR Flash Mode | |
228 | */ | |
229 | #define FTIM1_NOR 0xFF003F3F | |
230 | #define FTIM1_NOR_TACO_SHIFT 24 | |
231 | #define FTIM1_NOR_TACO(n) ((n) << FTIM1_NOR_TACO_SHIFT) | |
232 | #define FTIM1_NOR_TRAD_NOR_SHIFT 8 | |
233 | #define FTIM1_NOR_TRAD_NOR(n) ((n) << FTIM1_NOR_TRAD_NOR_SHIFT) | |
234 | #define FTIM1_NOR_TSEQRAD_NOR_SHIFT 0 | |
235 | #define FTIM1_NOR_TSEQRAD_NOR(n) ((n) << FTIM1_NOR_TSEQRAD_NOR_SHIFT) | |
236 | /* | |
237 | * FTIM2 - NOR Flash Mode | |
238 | */ | |
239 | #define FTIM2_NOR 0x0F3CFCFF | |
240 | #define FTIM2_NOR_TCS_SHIFT 24 | |
241 | #define FTIM2_NOR_TCS(n) ((n) << FTIM2_NOR_TCS_SHIFT) | |
242 | #define FTIM2_NOR_TCH_SHIFT 18 | |
243 | #define FTIM2_NOR_TCH(n) ((n) << FTIM2_NOR_TCH_SHIFT) | |
244 | #define FTIM2_NOR_TWPH_SHIFT 10 | |
245 | #define FTIM2_NOR_TWPH(n) ((n) << FTIM2_NOR_TWPH_SHIFT) | |
246 | #define FTIM2_NOR_TWP_SHIFT 0 | |
247 | #define FTIM2_NOR_TWP(n) ((n) << FTIM2_NOR_TWP_SHIFT) | |
248 | ||
249 | /* | |
250 | * FTIM0 - Normal GPCM Mode | |
251 | */ | |
252 | #define FTIM0_GPCM 0xF03F3F3F | |
253 | #define FTIM0_GPCM_TACSE_SHIFT 28 | |
254 | #define FTIM0_GPCM_TACSE(n) ((n) << FTIM0_GPCM_TACSE_SHIFT) | |
255 | #define FTIM0_GPCM_TEADC_SHIFT 16 | |
256 | #define FTIM0_GPCM_TEADC(n) ((n) << FTIM0_GPCM_TEADC_SHIFT) | |
257 | #define FTIM0_GPCM_TAVDS_SHIFT 8 | |
258 | #define FTIM0_GPCM_TAVDS(n) ((n) << FTIM0_GPCM_TAVDS_SHIFT) | |
259 | #define FTIM0_GPCM_TEAHC_SHIFT 0 | |
260 | #define FTIM0_GPCM_TEAHC(n) ((n) << FTIM0_GPCM_TEAHC_SHIFT) | |
261 | /* | |
262 | * FTIM1 - Normal GPCM Mode | |
263 | */ | |
264 | #define FTIM1_GPCM 0xFF003F00 | |
265 | #define FTIM1_GPCM_TACO_SHIFT 24 | |
266 | #define FTIM1_GPCM_TACO(n) ((n) << FTIM1_GPCM_TACO_SHIFT) | |
267 | #define FTIM1_GPCM_TRAD_SHIFT 8 | |
268 | #define FTIM1_GPCM_TRAD(n) ((n) << FTIM1_GPCM_TRAD_SHIFT) | |
269 | /* | |
270 | * FTIM2 - Normal GPCM Mode | |
271 | */ | |
272 | #define FTIM2_GPCM 0x0F3C00FF | |
273 | #define FTIM2_GPCM_TCS_SHIFT 24 | |
274 | #define FTIM2_GPCM_TCS(n) ((n) << FTIM2_GPCM_TCS_SHIFT) | |
275 | #define FTIM2_GPCM_TCH_SHIFT 18 | |
276 | #define FTIM2_GPCM_TCH(n) ((n) << FTIM2_GPCM_TCH_SHIFT) | |
277 | #define FTIM2_GPCM_TWP_SHIFT 0 | |
278 | #define FTIM2_GPCM_TWP(n) ((n) << FTIM2_GPCM_TWP_SHIFT) | |
279 | ||
280 | /* | |
281 | * Ready Busy Status Register (RB_STAT) | |
282 | */ | |
283 | /* CSn is READY */ | |
284 | #define IFC_RB_STAT_READY_CS0 0x80000000 | |
285 | #define IFC_RB_STAT_READY_CS1 0x40000000 | |
286 | #define IFC_RB_STAT_READY_CS2 0x20000000 | |
287 | #define IFC_RB_STAT_READY_CS3 0x10000000 | |
288 | ||
289 | /* | |
290 | * General Control Register (GCR) | |
291 | */ | |
292 | #define IFC_GCR_MASK 0x8000F800 | |
293 | /* reset all IFC hardware */ | |
294 | #define IFC_GCR_SOFT_RST_ALL 0x80000000 | |
295 | /* Turnaroud Time of external buffer */ | |
296 | #define IFC_GCR_TBCTL_TRN_TIME 0x0000F800 | |
297 | #define IFC_GCR_TBCTL_TRN_TIME_SHIFT 11 | |
298 | ||
299 | /* | |
300 | * Common Event and Error Status Register (CM_EVTER_STAT) | |
301 | */ | |
302 | /* Chip select error */ | |
303 | #define IFC_CM_EVTER_STAT_CSER 0x80000000 | |
304 | ||
305 | /* | |
306 | * Common Event and Error Enable Register (CM_EVTER_EN) | |
307 | */ | |
308 | /* Chip select error checking enable */ | |
309 | #define IFC_CM_EVTER_EN_CSEREN 0x80000000 | |
310 | ||
311 | /* | |
312 | * Common Event and Error Interrupt Enable Register (CM_EVTER_INTR_EN) | |
313 | */ | |
314 | /* Chip select error interrupt enable */ | |
315 | #define IFC_CM_EVTER_INTR_EN_CSERIREN 0x80000000 | |
316 | ||
317 | /* | |
318 | * Common Transfer Error Attribute Register-0 (CM_ERATTR0) | |
319 | */ | |
320 | /* transaction type of error Read/Write */ | |
321 | #define IFC_CM_ERATTR0_ERTYP_READ 0x80000000 | |
322 | #define IFC_CM_ERATTR0_ERAID 0x0FF00000 | |
323 | #define IFC_CM_ERATTR0_ESRCID 0x0000FF00 | |
324 | ||
325 | /* | |
326 | * Clock Control Register (CCR) | |
327 | */ | |
328 | #define IFC_CCR_MASK 0x0F0F8800 | |
329 | /* Clock division ratio */ | |
330 | #define IFC_CCR_CLK_DIV_MASK 0x0F000000 | |
331 | #define IFC_CCR_CLK_DIV_SHIFT 24 | |
332 | #define IFC_CCR_CLK_DIV(n) ((n-1) << IFC_CCR_CLK_DIV_SHIFT) | |
333 | /* IFC Clock Delay */ | |
334 | #define IFC_CCR_CLK_DLY_MASK 0x000F0000 | |
335 | #define IFC_CCR_CLK_DLY_SHIFT 16 | |
336 | #define IFC_CCR_CLK_DLY(n) ((n) << IFC_CCR_CLK_DLY_SHIFT) | |
337 | /* Invert IFC clock before sending out */ | |
338 | #define IFC_CCR_INV_CLK_EN 0x00008000 | |
339 | /* Fedback IFC Clock */ | |
340 | #define IFC_CCR_FB_IFC_CLK_SEL 0x00000800 | |
341 | ||
342 | /* | |
343 | * Clock Status Register (CSR) | |
344 | */ | |
345 | /* Clk is stable */ | |
346 | #define IFC_CSR_CLK_STAT_STABLE 0x80000000 | |
347 | ||
348 | /* | |
349 | * IFC_NAND Machine Specific Registers | |
350 | */ | |
351 | /* | |
352 | * NAND Configuration Register (NCFGR) | |
353 | */ | |
354 | /* Auto Boot Mode */ | |
355 | #define IFC_NAND_NCFGR_BOOT 0x80000000 | |
356 | /* Addressing Mode-ROW0+n/COL0 */ | |
357 | #define IFC_NAND_NCFGR_ADDR_MODE_RC0 0x00000000 | |
358 | /* Addressing Mode-ROW0+n/COL0+n */ | |
359 | #define IFC_NAND_NCFGR_ADDR_MODE_RC1 0x00400000 | |
360 | /* Number of loop iterations of FIR sequences for multi page operations */ | |
361 | #define IFC_NAND_NCFGR_NUM_LOOP_MASK 0x0000F000 | |
362 | #define IFC_NAND_NCFGR_NUM_LOOP_SHIFT 12 | |
363 | #define IFC_NAND_NCFGR_NUM_LOOP(n) ((n) << IFC_NAND_NCFGR_NUM_LOOP_SHIFT) | |
364 | /* Number of wait cycles */ | |
365 | #define IFC_NAND_NCFGR_NUM_WAIT_MASK 0x000000FF | |
366 | #define IFC_NAND_NCFGR_NUM_WAIT_SHIFT 0 | |
367 | ||
368 | /* | |
369 | * NAND Flash Command Registers (NAND_FCR0/NAND_FCR1) | |
370 | */ | |
371 | /* General purpose FCM flash command bytes CMD0-CMD7 */ | |
372 | #define IFC_NAND_FCR0_CMD0 0xFF000000 | |
373 | #define IFC_NAND_FCR0_CMD0_SHIFT 24 | |
374 | #define IFC_NAND_FCR0_CMD1 0x00FF0000 | |
375 | #define IFC_NAND_FCR0_CMD1_SHIFT 16 | |
376 | #define IFC_NAND_FCR0_CMD2 0x0000FF00 | |
377 | #define IFC_NAND_FCR0_CMD2_SHIFT 8 | |
378 | #define IFC_NAND_FCR0_CMD3 0x000000FF | |
379 | #define IFC_NAND_FCR0_CMD3_SHIFT 0 | |
380 | #define IFC_NAND_FCR1_CMD4 0xFF000000 | |
381 | #define IFC_NAND_FCR1_CMD4_SHIFT 24 | |
382 | #define IFC_NAND_FCR1_CMD5 0x00FF0000 | |
383 | #define IFC_NAND_FCR1_CMD5_SHIFT 16 | |
384 | #define IFC_NAND_FCR1_CMD6 0x0000FF00 | |
385 | #define IFC_NAND_FCR1_CMD6_SHIFT 8 | |
386 | #define IFC_NAND_FCR1_CMD7 0x000000FF | |
387 | #define IFC_NAND_FCR1_CMD7_SHIFT 0 | |
388 | ||
389 | /* | |
390 | * Flash ROW and COL Address Register (ROWn, COLn) | |
391 | */ | |
392 | /* Main/spare region locator */ | |
393 | #define IFC_NAND_COL_MS 0x80000000 | |
394 | /* Column Address */ | |
395 | #define IFC_NAND_COL_CA_MASK 0x00000FFF | |
396 | ||
397 | /* | |
398 | * NAND Flash Byte Count Register (NAND_BC) | |
399 | */ | |
400 | /* Byte Count for read/Write */ | |
401 | #define IFC_NAND_BC 0x000001FF | |
402 | ||
403 | /* | |
404 | * NAND Flash Instruction Registers (NAND_FIR0/NAND_FIR1/NAND_FIR2) | |
405 | */ | |
406 | /* NAND Machine specific opcodes OP0-OP14*/ | |
407 | #define IFC_NAND_FIR0_OP0 0xFC000000 | |
408 | #define IFC_NAND_FIR0_OP0_SHIFT 26 | |
409 | #define IFC_NAND_FIR0_OP1 0x03F00000 | |
410 | #define IFC_NAND_FIR0_OP1_SHIFT 20 | |
411 | #define IFC_NAND_FIR0_OP2 0x000FC000 | |
412 | #define IFC_NAND_FIR0_OP2_SHIFT 14 | |
413 | #define IFC_NAND_FIR0_OP3 0x00003F00 | |
414 | #define IFC_NAND_FIR0_OP3_SHIFT 8 | |
415 | #define IFC_NAND_FIR0_OP4 0x000000FC | |
416 | #define IFC_NAND_FIR0_OP4_SHIFT 2 | |
417 | #define IFC_NAND_FIR1_OP5 0xFC000000 | |
418 | #define IFC_NAND_FIR1_OP5_SHIFT 26 | |
419 | #define IFC_NAND_FIR1_OP6 0x03F00000 | |
420 | #define IFC_NAND_FIR1_OP6_SHIFT 20 | |
421 | #define IFC_NAND_FIR1_OP7 0x000FC000 | |
422 | #define IFC_NAND_FIR1_OP7_SHIFT 14 | |
423 | #define IFC_NAND_FIR1_OP8 0x00003F00 | |
424 | #define IFC_NAND_FIR1_OP8_SHIFT 8 | |
425 | #define IFC_NAND_FIR1_OP9 0x000000FC | |
426 | #define IFC_NAND_FIR1_OP9_SHIFT 2 | |
427 | #define IFC_NAND_FIR2_OP10 0xFC000000 | |
428 | #define IFC_NAND_FIR2_OP10_SHIFT 26 | |
429 | #define IFC_NAND_FIR2_OP11 0x03F00000 | |
430 | #define IFC_NAND_FIR2_OP11_SHIFT 20 | |
431 | #define IFC_NAND_FIR2_OP12 0x000FC000 | |
432 | #define IFC_NAND_FIR2_OP12_SHIFT 14 | |
433 | #define IFC_NAND_FIR2_OP13 0x00003F00 | |
434 | #define IFC_NAND_FIR2_OP13_SHIFT 8 | |
435 | #define IFC_NAND_FIR2_OP14 0x000000FC | |
436 | #define IFC_NAND_FIR2_OP14_SHIFT 2 | |
437 | ||
438 | /* | |
439 | * Instruction opcodes to be programmed | |
440 | * in FIR registers- 6bits | |
441 | */ | |
442 | enum ifc_nand_fir_opcodes { | |
443 | IFC_FIR_OP_NOP, | |
444 | IFC_FIR_OP_CA0, | |
445 | IFC_FIR_OP_CA1, | |
446 | IFC_FIR_OP_CA2, | |
447 | IFC_FIR_OP_CA3, | |
448 | IFC_FIR_OP_RA0, | |
449 | IFC_FIR_OP_RA1, | |
450 | IFC_FIR_OP_RA2, | |
451 | IFC_FIR_OP_RA3, | |
452 | IFC_FIR_OP_CMD0, | |
453 | IFC_FIR_OP_CMD1, | |
454 | IFC_FIR_OP_CMD2, | |
455 | IFC_FIR_OP_CMD3, | |
456 | IFC_FIR_OP_CMD4, | |
457 | IFC_FIR_OP_CMD5, | |
458 | IFC_FIR_OP_CMD6, | |
459 | IFC_FIR_OP_CMD7, | |
460 | IFC_FIR_OP_CW0, | |
461 | IFC_FIR_OP_CW1, | |
462 | IFC_FIR_OP_CW2, | |
463 | IFC_FIR_OP_CW3, | |
464 | IFC_FIR_OP_CW4, | |
465 | IFC_FIR_OP_CW5, | |
466 | IFC_FIR_OP_CW6, | |
467 | IFC_FIR_OP_CW7, | |
468 | IFC_FIR_OP_WBCD, | |
469 | IFC_FIR_OP_RBCD, | |
470 | IFC_FIR_OP_BTRD, | |
471 | IFC_FIR_OP_RDSTAT, | |
472 | IFC_FIR_OP_NWAIT, | |
473 | IFC_FIR_OP_WFR, | |
474 | IFC_FIR_OP_SBRD, | |
475 | IFC_FIR_OP_UA, | |
476 | IFC_FIR_OP_RB, | |
477 | }; | |
478 | ||
479 | /* | |
480 | * NAND Chip Select Register (NAND_CSEL) | |
481 | */ | |
482 | #define IFC_NAND_CSEL 0x0C000000 | |
483 | #define IFC_NAND_CSEL_SHIFT 26 | |
484 | #define IFC_NAND_CSEL_CS0 0x00000000 | |
485 | #define IFC_NAND_CSEL_CS1 0x04000000 | |
486 | #define IFC_NAND_CSEL_CS2 0x08000000 | |
487 | #define IFC_NAND_CSEL_CS3 0x0C000000 | |
488 | ||
489 | /* | |
490 | * NAND Operation Sequence Start (NANDSEQ_STRT) | |
491 | */ | |
492 | /* NAND Flash Operation Start */ | |
493 | #define IFC_NAND_SEQ_STRT_FIR_STRT 0x80000000 | |
494 | /* Automatic Erase */ | |
495 | #define IFC_NAND_SEQ_STRT_AUTO_ERS 0x00800000 | |
496 | /* Automatic Program */ | |
497 | #define IFC_NAND_SEQ_STRT_AUTO_PGM 0x00100000 | |
498 | /* Automatic Copyback */ | |
499 | #define IFC_NAND_SEQ_STRT_AUTO_CPB 0x00020000 | |
500 | /* Automatic Read Operation */ | |
501 | #define IFC_NAND_SEQ_STRT_AUTO_RD 0x00004000 | |
502 | /* Automatic Status Read */ | |
503 | #define IFC_NAND_SEQ_STRT_AUTO_STAT_RD 0x00000800 | |
504 | ||
505 | /* | |
506 | * NAND Event and Error Status Register (NAND_EVTER_STAT) | |
507 | */ | |
508 | /* Operation Complete */ | |
509 | #define IFC_NAND_EVTER_STAT_OPC 0x80000000 | |
510 | /* Flash Timeout Error */ | |
511 | #define IFC_NAND_EVTER_STAT_FTOER 0x08000000 | |
512 | /* Write Protect Error */ | |
513 | #define IFC_NAND_EVTER_STAT_WPER 0x04000000 | |
514 | /* ECC Error */ | |
515 | #define IFC_NAND_EVTER_STAT_ECCER 0x02000000 | |
516 | /* RCW Load Done */ | |
517 | #define IFC_NAND_EVTER_STAT_RCW_DN 0x00008000 | |
518 | /* Boot Loadr Done */ | |
519 | #define IFC_NAND_EVTER_STAT_BOOT_DN 0x00004000 | |
520 | /* Bad Block Indicator search select */ | |
521 | #define IFC_NAND_EVTER_STAT_BBI_SRCH_SE 0x00000800 | |
522 | ||
523 | /* | |
524 | * NAND Flash Page Read Completion Event Status Register | |
525 | * (PGRDCMPL_EVT_STAT) | |
526 | */ | |
527 | #define PGRDCMPL_EVT_STAT_MASK 0xFFFF0000 | |
528 | /* Small Page 0-15 Done */ | |
529 | #define PGRDCMPL_EVT_STAT_SECTION_SP(n) (1 << (31 - (n))) | |
530 | /* Large Page(2K) 0-3 Done */ | |
531 | #define PGRDCMPL_EVT_STAT_LP_2K(n) (0xF << (28 - (n)*4)) | |
532 | /* Large Page(4K) 0-1 Done */ | |
533 | #define PGRDCMPL_EVT_STAT_LP_4K(n) (0xFF << (24 - (n)*8)) | |
534 | ||
535 | /* | |
536 | * NAND Event and Error Enable Register (NAND_EVTER_EN) | |
537 | */ | |
538 | /* Operation complete event enable */ | |
539 | #define IFC_NAND_EVTER_EN_OPC_EN 0x80000000 | |
540 | /* Page read complete event enable */ | |
541 | #define IFC_NAND_EVTER_EN_PGRDCMPL_EN 0x20000000 | |
542 | /* Flash Timeout error enable */ | |
543 | #define IFC_NAND_EVTER_EN_FTOER_EN 0x08000000 | |
544 | /* Write Protect error enable */ | |
545 | #define IFC_NAND_EVTER_EN_WPER_EN 0x04000000 | |
546 | /* ECC error logging enable */ | |
547 | #define IFC_NAND_EVTER_EN_ECCER_EN 0x02000000 | |
548 | ||
549 | /* | |
550 | * NAND Event and Error Interrupt Enable Register (NAND_EVTER_INTR_EN) | |
551 | */ | |
552 | /* Enable interrupt for operation complete */ | |
553 | #define IFC_NAND_EVTER_INTR_OPCIR_EN 0x80000000 | |
554 | /* Enable interrupt for Page read complete */ | |
555 | #define IFC_NAND_EVTER_INTR_PGRDCMPLIR_EN 0x20000000 | |
556 | /* Enable interrupt for Flash timeout error */ | |
557 | #define IFC_NAND_EVTER_INTR_FTOERIR_EN 0x08000000 | |
558 | /* Enable interrupt for Write protect error */ | |
559 | #define IFC_NAND_EVTER_INTR_WPERIR_EN 0x04000000 | |
560 | /* Enable interrupt for ECC error*/ | |
561 | #define IFC_NAND_EVTER_INTR_ECCERIR_EN 0x02000000 | |
562 | ||
563 | /* | |
564 | * NAND Transfer Error Attribute Register-0 (NAND_ERATTR0) | |
565 | */ | |
566 | #define IFC_NAND_ERATTR0_MASK 0x0C080000 | |
567 | /* Error on CS0-3 for NAND */ | |
568 | #define IFC_NAND_ERATTR0_ERCS_CS0 0x00000000 | |
569 | #define IFC_NAND_ERATTR0_ERCS_CS1 0x04000000 | |
570 | #define IFC_NAND_ERATTR0_ERCS_CS2 0x08000000 | |
571 | #define IFC_NAND_ERATTR0_ERCS_CS3 0x0C000000 | |
572 | /* Transaction type of error Read/Write */ | |
573 | #define IFC_NAND_ERATTR0_ERTTYPE_READ 0x00080000 | |
574 | ||
575 | /* | |
576 | * NAND Flash Status Register (NAND_FSR) | |
577 | */ | |
578 | /* First byte of data read from read status op */ | |
579 | #define IFC_NAND_NFSR_RS0 0xFF000000 | |
580 | /* Second byte of data read from read status op */ | |
581 | #define IFC_NAND_NFSR_RS1 0x00FF0000 | |
582 | ||
583 | /* | |
584 | * ECC Error Status Registers (ECCSTAT0-ECCSTAT3) | |
585 | */ | |
586 | /* Number of ECC errors on sector n (n = 0-15) */ | |
587 | #define IFC_NAND_ECCSTAT0_ERRCNT_SECTOR0_MASK 0x0F000000 | |
588 | #define IFC_NAND_ECCSTAT0_ERRCNT_SECTOR0_SHIFT 24 | |
589 | #define IFC_NAND_ECCSTAT0_ERRCNT_SECTOR1_MASK 0x000F0000 | |
590 | #define IFC_NAND_ECCSTAT0_ERRCNT_SECTOR1_SHIFT 16 | |
591 | #define IFC_NAND_ECCSTAT0_ERRCNT_SECTOR2_MASK 0x00000F00 | |
592 | #define IFC_NAND_ECCSTAT0_ERRCNT_SECTOR2_SHIFT 8 | |
593 | #define IFC_NAND_ECCSTAT0_ERRCNT_SECTOR3_MASK 0x0000000F | |
594 | #define IFC_NAND_ECCSTAT0_ERRCNT_SECTOR3_SHIFT 0 | |
595 | #define IFC_NAND_ECCSTAT1_ERRCNT_SECTOR4_MASK 0x0F000000 | |
596 | #define IFC_NAND_ECCSTAT1_ERRCNT_SECTOR4_SHIFT 24 | |
597 | #define IFC_NAND_ECCSTAT1_ERRCNT_SECTOR5_MASK 0x000F0000 | |
598 | #define IFC_NAND_ECCSTAT1_ERRCNT_SECTOR5_SHIFT 16 | |
599 | #define IFC_NAND_ECCSTAT1_ERRCNT_SECTOR6_MASK 0x00000F00 | |
600 | #define IFC_NAND_ECCSTAT1_ERRCNT_SECTOR6_SHIFT 8 | |
601 | #define IFC_NAND_ECCSTAT1_ERRCNT_SECTOR7_MASK 0x0000000F | |
602 | #define IFC_NAND_ECCSTAT1_ERRCNT_SECTOR7_SHIFT 0 | |
603 | #define IFC_NAND_ECCSTAT2_ERRCNT_SECTOR8_MASK 0x0F000000 | |
604 | #define IFC_NAND_ECCSTAT2_ERRCNT_SECTOR8_SHIFT 24 | |
605 | #define IFC_NAND_ECCSTAT2_ERRCNT_SECTOR9_MASK 0x000F0000 | |
606 | #define IFC_NAND_ECCSTAT2_ERRCNT_SECTOR9_SHIFT 16 | |
607 | #define IFC_NAND_ECCSTAT2_ERRCNT_SECTOR10_MASK 0x00000F00 | |
608 | #define IFC_NAND_ECCSTAT2_ERRCNT_SECTOR10_SHIFT 8 | |
609 | #define IFC_NAND_ECCSTAT2_ERRCNT_SECTOR11_MASK 0x0000000F | |
610 | #define IFC_NAND_ECCSTAT2_ERRCNT_SECTOR11_SHIFT 0 | |
611 | #define IFC_NAND_ECCSTAT3_ERRCNT_SECTOR12_MASK 0x0F000000 | |
612 | #define IFC_NAND_ECCSTAT3_ERRCNT_SECTOR12_SHIFT 24 | |
613 | #define IFC_NAND_ECCSTAT3_ERRCNT_SECTOR13_MASK 0x000F0000 | |
614 | #define IFC_NAND_ECCSTAT3_ERRCNT_SECTOR13_SHIFT 16 | |
615 | #define IFC_NAND_ECCSTAT3_ERRCNT_SECTOR14_MASK 0x00000F00 | |
616 | #define IFC_NAND_ECCSTAT3_ERRCNT_SECTOR14_SHIFT 8 | |
617 | #define IFC_NAND_ECCSTAT3_ERRCNT_SECTOR15_MASK 0x0000000F | |
618 | #define IFC_NAND_ECCSTAT3_ERRCNT_SECTOR15_SHIFT 0 | |
619 | ||
620 | /* | |
621 | * NAND Control Register (NANDCR) | |
622 | */ | |
623 | #define IFC_NAND_NCR_FTOCNT_MASK 0x1E000000 | |
624 | #define IFC_NAND_NCR_FTOCNT_SHIFT 25 | |
625 | #define IFC_NAND_NCR_FTOCNT(n) ((_ilog2(n) - 8) << IFC_NAND_NCR_FTOCNT_SHIFT) | |
626 | ||
627 | /* | |
628 | * NAND_AUTOBOOT_TRGR | |
629 | */ | |
630 | /* Trigger RCW load */ | |
631 | #define IFC_NAND_AUTOBOOT_TRGR_RCW_LD 0x80000000 | |
632 | /* Trigget Auto Boot */ | |
633 | #define IFC_NAND_AUTOBOOT_TRGR_BOOT_LD 0x20000000 | |
634 | ||
635 | /* | |
636 | * NAND_MDR | |
637 | */ | |
638 | /* 1st read data byte when opcode SBRD */ | |
639 | #define IFC_NAND_MDR_RDATA0 0xFF000000 | |
640 | /* 2nd read data byte when opcode SBRD */ | |
641 | #define IFC_NAND_MDR_RDATA1 0x00FF0000 | |
642 | ||
643 | /* | |
644 | * NOR Machine Specific Registers | |
645 | */ | |
646 | /* | |
647 | * NOR Event and Error Status Register (NOR_EVTER_STAT) | |
648 | */ | |
649 | /* NOR Command Sequence Operation Complete */ | |
650 | #define IFC_NOR_EVTER_STAT_OPC_NOR 0x80000000 | |
651 | /* Write Protect Error */ | |
652 | #define IFC_NOR_EVTER_STAT_WPER 0x04000000 | |
653 | /* Command Sequence Timeout Error */ | |
654 | #define IFC_NOR_EVTER_STAT_STOER 0x01000000 | |
655 | ||
656 | /* | |
657 | * NOR Event and Error Enable Register (NOR_EVTER_EN) | |
658 | */ | |
659 | /* NOR Command Seq complete event enable */ | |
660 | #define IFC_NOR_EVTER_EN_OPCEN_NOR 0x80000000 | |
661 | /* Write Protect Error Checking Enable */ | |
662 | #define IFC_NOR_EVTER_EN_WPEREN 0x04000000 | |
663 | /* Timeout Error Enable */ | |
664 | #define IFC_NOR_EVTER_EN_STOEREN 0x01000000 | |
665 | ||
666 | /* | |
667 | * NOR Event and Error Interrupt Enable Register (NOR_EVTER_INTR_EN) | |
668 | */ | |
669 | /* Enable interrupt for OPC complete */ | |
670 | #define IFC_NOR_EVTER_INTR_OPCEN_NOR 0x80000000 | |
671 | /* Enable interrupt for write protect error */ | |
672 | #define IFC_NOR_EVTER_INTR_WPEREN 0x04000000 | |
673 | /* Enable interrupt for timeout error */ | |
674 | #define IFC_NOR_EVTER_INTR_STOEREN 0x01000000 | |
675 | ||
676 | /* | |
677 | * NOR Transfer Error Attribute Register-0 (NOR_ERATTR0) | |
678 | */ | |
679 | /* Source ID for error transaction */ | |
680 | #define IFC_NOR_ERATTR0_ERSRCID 0xFF000000 | |
681 | /* AXI ID for error transation */ | |
682 | #define IFC_NOR_ERATTR0_ERAID 0x000FF000 | |
683 | /* Chip select corresponds to NOR error */ | |
684 | #define IFC_NOR_ERATTR0_ERCS_CS0 0x00000000 | |
685 | #define IFC_NOR_ERATTR0_ERCS_CS1 0x00000010 | |
686 | #define IFC_NOR_ERATTR0_ERCS_CS2 0x00000020 | |
687 | #define IFC_NOR_ERATTR0_ERCS_CS3 0x00000030 | |
688 | /* Type of transaction read/write */ | |
689 | #define IFC_NOR_ERATTR0_ERTYPE_READ 0x00000001 | |
690 | ||
691 | /* | |
692 | * NOR Transfer Error Attribute Register-2 (NOR_ERATTR2) | |
693 | */ | |
694 | #define IFC_NOR_ERATTR2_ER_NUM_PHASE_EXP 0x000F0000 | |
695 | #define IFC_NOR_ERATTR2_ER_NUM_PHASE_PER 0x00000F00 | |
696 | ||
697 | /* | |
698 | * NOR Control Register (NORCR) | |
699 | */ | |
700 | #define IFC_NORCR_MASK 0x0F0F0000 | |
701 | /* No. of Address/Data Phase */ | |
702 | #define IFC_NORCR_NUM_PHASE_MASK 0x0F000000 | |
703 | #define IFC_NORCR_NUM_PHASE_SHIFT 24 | |
704 | #define IFC_NORCR_NUM_PHASE(n) ((n-1) << IFC_NORCR_NUM_PHASE_SHIFT) | |
705 | /* Sequence Timeout Count */ | |
706 | #define IFC_NORCR_STOCNT_MASK 0x000F0000 | |
707 | #define IFC_NORCR_STOCNT_SHIFT 16 | |
708 | #define IFC_NORCR_STOCNT(n) ((__ilog2(n) - 8) << IFC_NORCR_STOCNT_SHIFT) | |
709 | ||
710 | /* | |
711 | * GPCM Machine specific registers | |
712 | */ | |
713 | /* | |
714 | * GPCM Event and Error Status Register (GPCM_EVTER_STAT) | |
715 | */ | |
716 | /* Timeout error */ | |
717 | #define IFC_GPCM_EVTER_STAT_TOER 0x04000000 | |
718 | /* Parity error */ | |
719 | #define IFC_GPCM_EVTER_STAT_PER 0x01000000 | |
720 | ||
721 | /* | |
722 | * GPCM Event and Error Enable Register (GPCM_EVTER_EN) | |
723 | */ | |
724 | /* Timeout error enable */ | |
725 | #define IFC_GPCM_EVTER_EN_TOER_EN 0x04000000 | |
726 | /* Parity error enable */ | |
727 | #define IFC_GPCM_EVTER_EN_PER_EN 0x01000000 | |
728 | ||
729 | /* | |
730 | * GPCM Event and Error Interrupt Enable Register (GPCM_EVTER_INTR_EN) | |
731 | */ | |
732 | /* Enable Interrupt for timeout error */ | |
733 | #define IFC_GPCM_EEIER_TOERIR_EN 0x04000000 | |
734 | /* Enable Interrupt for Parity error */ | |
735 | #define IFC_GPCM_EEIER_PERIR_EN 0x01000000 | |
736 | ||
737 | /* | |
738 | * GPCM Transfer Error Attribute Register-0 (GPCM_ERATTR0) | |
739 | */ | |
740 | /* Source ID for error transaction */ | |
741 | #define IFC_GPCM_ERATTR0_ERSRCID 0xFF000000 | |
742 | /* AXI ID for error transaction */ | |
743 | #define IFC_GPCM_ERATTR0_ERAID 0x000FF000 | |
744 | /* Chip select corresponds to GPCM error */ | |
745 | #define IFC_GPCM_ERATTR0_ERCS_CS0 0x00000000 | |
746 | #define IFC_GPCM_ERATTR0_ERCS_CS1 0x00000040 | |
747 | #define IFC_GPCM_ERATTR0_ERCS_CS2 0x00000080 | |
748 | #define IFC_GPCM_ERATTR0_ERCS_CS3 0x000000C0 | |
749 | /* Type of transaction read/Write */ | |
750 | #define IFC_GPCM_ERATTR0_ERTYPE_READ 0x00000001 | |
751 | ||
752 | /* | |
753 | * GPCM Transfer Error Attribute Register-2 (GPCM_ERATTR2) | |
754 | */ | |
755 | /* On which beat of address/data parity error is observed */ | |
756 | #define IFC_GPCM_ERATTR2_PERR_BEAT 0x00000C00 | |
757 | /* Parity Error on byte */ | |
758 | #define IFC_GPCM_ERATTR2_PERR_BYTE 0x000000F0 | |
759 | /* Parity Error reported in addr or data phase */ | |
760 | #define IFC_GPCM_ERATTR2_PERR_DATA_PHASE 0x00000001 | |
761 | ||
762 | /* | |
763 | * GPCM Status Register (GPCM_STAT) | |
764 | */ | |
765 | #define IFC_GPCM_STAT_BSY 0x80000000 /* GPCM is busy */ | |
766 | ||
767 | ||
768 | #ifndef __ASSEMBLY__ | |
769 | #include <asm/io.h> | |
770 | ||
771 | extern void print_ifc_regs(void); | |
772 | extern void init_early_memctl_regs(void); | |
773 | ||
774 | #define IFC_BASE_ADDR ((struct fsl_ifc *)CONFIG_SYS_IFC_ADDR) | |
775 | ||
ffdf8890 | 776 | #define get_ifc_cspr_ext(i) (in_be32(&(IFC_BASE_ADDR)->cspr_cs[i].cspr_ext)) |
d789b5f5 | 777 | #define get_ifc_cspr(i) (in_be32(&(IFC_BASE_ADDR)->cspr_cs[i].cspr)) |
ffdf8890 | 778 | #define get_ifc_csor_ext(i) (in_be32(&(IFC_BASE_ADDR)->csor_cs[i].csor_ext)) |
d789b5f5 DD |
779 | #define get_ifc_csor(i) (in_be32(&(IFC_BASE_ADDR)->csor_cs[i].csor)) |
780 | #define get_ifc_amask(i) (in_be32(&(IFC_BASE_ADDR)->amask_cs[i].amask)) | |
781 | #define get_ifc_ftim(i, j) (in_be32(&(IFC_BASE_ADDR)->ftim_cs[i].ftim[j])) | |
782 | ||
ffdf8890 | 783 | #define set_ifc_cspr_ext(i, v) (out_be32(&(IFC_BASE_ADDR)->cspr_cs[i].cspr_ext, v)) |
d789b5f5 | 784 | #define set_ifc_cspr(i, v) (out_be32(&(IFC_BASE_ADDR)->cspr_cs[i].cspr, v)) |
ffdf8890 | 785 | #define set_ifc_csor_ext(i, v) (out_be32(&(IFC_BASE_ADDR)->csor_cs[i].csor_ext, v)) |
d789b5f5 DD |
786 | #define set_ifc_csor(i, v) (out_be32(&(IFC_BASE_ADDR)->csor_cs[i].csor, v)) |
787 | #define set_ifc_amask(i, v) (out_be32(&(IFC_BASE_ADDR)->amask_cs[i].amask, v)) | |
788 | #define set_ifc_ftim(i, j, v) \ | |
789 | (out_be32(&(IFC_BASE_ADDR)->ftim_cs[i].ftim[j], v)) | |
790 | ||
d789b5f5 DD |
791 | enum ifc_chip_sel { |
792 | IFC_CS0, | |
793 | IFC_CS1, | |
794 | IFC_CS2, | |
795 | IFC_CS3, | |
362ee04b MH |
796 | IFC_CS4, |
797 | IFC_CS5, | |
798 | IFC_CS6, | |
799 | IFC_CS7, | |
d789b5f5 DD |
800 | }; |
801 | ||
802 | enum ifc_ftims { | |
803 | IFC_FTIM0, | |
804 | IFC_FTIM1, | |
805 | IFC_FTIM2, | |
806 | IFC_FTIM3, | |
807 | }; | |
808 | ||
809 | /* | |
810 | * IFC Controller NAND Machine registers | |
811 | */ | |
812 | struct fsl_ifc_nand { | |
813 | u32 ncfgr; | |
814 | u32 res1[0x4]; | |
815 | u32 nand_fcr0; | |
816 | u32 nand_fcr1; | |
817 | u32 res2[0x8]; | |
818 | u32 row0; | |
819 | u32 res3; | |
820 | u32 col0; | |
821 | u32 res4; | |
822 | u32 row1; | |
823 | u32 res5; | |
824 | u32 col1; | |
825 | u32 res6; | |
826 | u32 row2; | |
827 | u32 res7; | |
828 | u32 col2; | |
829 | u32 res8; | |
830 | u32 row3; | |
831 | u32 res9; | |
832 | u32 col3; | |
833 | u32 res10[0x24]; | |
834 | u32 nand_fbcr; | |
835 | u32 res11; | |
836 | u32 nand_fir0; | |
837 | u32 nand_fir1; | |
838 | u32 nand_fir2; | |
839 | u32 res12[0x10]; | |
840 | u32 nand_csel; | |
841 | u32 res13; | |
842 | u32 nandseq_strt; | |
843 | u32 res14; | |
844 | u32 nand_evter_stat; | |
845 | u32 res15; | |
846 | u32 pgrdcmpl_evt_stat; | |
847 | u32 res16[0x2]; | |
848 | u32 nand_evter_en; | |
849 | u32 res17[0x2]; | |
850 | u32 nand_evter_intr_en; | |
851 | u32 res18[0x2]; | |
852 | u32 nand_erattr0; | |
853 | u32 nand_erattr1; | |
854 | u32 res19[0x10]; | |
855 | u32 nand_fsr; | |
856 | u32 res20; | |
52f90dad | 857 | u32 nand_eccstat[4]; |
d789b5f5 DD |
858 | u32 res21[0x20]; |
859 | u32 nanndcr; | |
860 | u32 res22[0x2]; | |
861 | u32 nand_autoboot_trgr; | |
862 | u32 res23; | |
863 | u32 nand_mdr; | |
864 | u32 res24[0x5C]; | |
865 | }; | |
866 | ||
867 | /* | |
868 | * IFC controller NOR Machine registers | |
869 | */ | |
870 | struct fsl_ifc_nor { | |
871 | u32 nor_evter_stat; | |
872 | u32 res1[0x2]; | |
873 | u32 nor_evter_en; | |
874 | u32 res2[0x2]; | |
875 | u32 nor_evter_intr_en; | |
876 | u32 res3[0x2]; | |
877 | u32 nor_erattr0; | |
878 | u32 nor_erattr1; | |
879 | u32 nor_erattr2; | |
880 | u32 res4[0x4]; | |
881 | u32 norcr; | |
882 | u32 res5[0xEF]; | |
883 | }; | |
884 | ||
885 | /* | |
886 | * IFC controller GPCM Machine registers | |
887 | */ | |
888 | struct fsl_ifc_gpcm { | |
889 | u32 gpcm_evter_stat; | |
890 | u32 res1[0x2]; | |
891 | u32 gpcm_evter_en; | |
892 | u32 res2[0x2]; | |
893 | u32 gpcm_evter_intr_en; | |
894 | u32 res3[0x2]; | |
895 | u32 gpcm_erattr0; | |
896 | u32 gpcm_erattr1; | |
897 | u32 gpcm_erattr2; | |
898 | u32 gpcm_stat; | |
899 | u32 res4[0x1F3]; | |
900 | }; | |
901 | ||
362ee04b MH |
902 | #ifdef CONFIG_SYS_FSL_IFC_BANK_COUNT |
903 | #if (CONFIG_SYS_FSL_IFC_BANK_COUNT <= 8) | |
904 | #define IFC_CSPR_REG_LEN 148 | |
905 | #define IFC_AMASK_REG_LEN 144 | |
906 | #define IFC_CSOR_REG_LEN 144 | |
907 | #define IFC_FTIM_REG_LEN 576 | |
908 | ||
909 | #define IFC_CSPR_USED_LEN sizeof(struct fsl_ifc_cspr) * \ | |
910 | CONFIG_SYS_FSL_IFC_BANK_COUNT | |
911 | #define IFC_AMASK_USED_LEN sizeof(struct fsl_ifc_amask) * \ | |
912 | CONFIG_SYS_FSL_IFC_BANK_COUNT | |
913 | #define IFC_CSOR_USED_LEN sizeof(struct fsl_ifc_csor) * \ | |
914 | CONFIG_SYS_FSL_IFC_BANK_COUNT | |
915 | #define IFC_FTIM_USED_LEN sizeof(struct fsl_ifc_ftim) * \ | |
916 | CONFIG_SYS_FSL_IFC_BANK_COUNT | |
917 | #else | |
918 | #error IFC BANK count not vaild | |
919 | #endif | |
920 | #else | |
921 | #error IFC BANK count not defined | |
922 | #endif | |
923 | ||
924 | struct fsl_ifc_cspr { | |
925 | u32 cspr_ext; | |
926 | u32 cspr; | |
927 | u32 res; | |
928 | }; | |
929 | ||
930 | struct fsl_ifc_amask { | |
931 | u32 amask; | |
932 | u32 res[0x2]; | |
933 | }; | |
934 | ||
935 | struct fsl_ifc_csor { | |
936 | u32 csor; | |
937 | u32 csor_ext; | |
938 | u32 res; | |
939 | }; | |
940 | ||
941 | struct fsl_ifc_ftim { | |
942 | u32 ftim[4]; | |
943 | u32 res[0x8]; | |
944 | }; | |
d789b5f5 DD |
945 | |
946 | /* | |
947 | * IFC Controller Registers | |
948 | */ | |
949 | struct fsl_ifc { | |
950 | u32 ifc_rev; | |
ffdf8890 | 951 | u32 res1[0x2]; |
362ee04b MH |
952 | struct fsl_ifc_cspr cspr_cs[CONFIG_SYS_FSL_IFC_BANK_COUNT]; |
953 | u8 res2[IFC_CSPR_REG_LEN - IFC_CSPR_USED_LEN]; | |
954 | struct fsl_ifc_amask amask_cs[CONFIG_SYS_FSL_IFC_BANK_COUNT]; | |
955 | u8 res3[IFC_AMASK_REG_LEN - IFC_AMASK_USED_LEN]; | |
956 | struct fsl_ifc_csor csor_cs[CONFIG_SYS_FSL_IFC_BANK_COUNT]; | |
957 | u8 res4[IFC_CSOR_REG_LEN - IFC_CSOR_USED_LEN]; | |
958 | struct fsl_ifc_ftim ftim_cs[CONFIG_SYS_FSL_IFC_BANK_COUNT]; | |
959 | u8 res5[IFC_FTIM_REG_LEN - IFC_FTIM_USED_LEN]; | |
d789b5f5 | 960 | u32 rb_stat; |
362ee04b | 961 | u32 res6[0x2]; |
d789b5f5 | 962 | u32 ifc_gcr; |
362ee04b | 963 | u32 res7[0x2]; |
d789b5f5 | 964 | u32 cm_evter_stat; |
362ee04b | 965 | u32 res8[0x2]; |
d789b5f5 | 966 | u32 cm_evter_en; |
362ee04b | 967 | u32 res9[0x2]; |
d789b5f5 | 968 | u32 cm_evter_intr_en; |
362ee04b | 969 | u32 res10[0x2]; |
d789b5f5 DD |
970 | u32 cm_erattr0; |
971 | u32 cm_erattr1; | |
362ee04b | 972 | u32 res11[0x2]; |
d789b5f5 DD |
973 | u32 ifc_ccr; |
974 | u32 ifc_csr; | |
362ee04b | 975 | u32 res12[0x2EB]; |
d789b5f5 DD |
976 | struct fsl_ifc_nand ifc_nand; |
977 | struct fsl_ifc_nor ifc_nor; | |
978 | struct fsl_ifc_gpcm ifc_gpcm; | |
979 | }; | |
980 | ||
42aee64b PA |
981 | #ifdef CONFIG_SYS_FSL_ERRATUM_IFC_A002769 |
982 | #undef CSPR_MSEL_NOR | |
983 | #define CSPR_MSEL_NOR CSPR_MSEL_GPCM | |
984 | #endif | |
362ee04b | 985 | #endif /* CONFIG_FSL_IFC */ |
42aee64b | 986 | |
d789b5f5 | 987 | #endif /* __ASSEMBLY__ */ |
0b66513b | 988 | #endif /* __FSL_IFC_H */ |