[thirdparty/qemu.git] / include / hw / adc / stm32f2xx_adc.h

/*
 * STM32F2XX ADC
 *
 * Copyright (c) 2014 Alistair Francis <alistair@alistair23.me>
 *
 * Permission is hereby granted, free of charge, to any person obtaining a copy
 * of this software and associated documentation files (the "Software"), to deal
 * in the Software without restriction, including without limitation the rights
 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
 * copies of the Software, and to permit persons to whom the Software is
 * furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
 * THE SOFTWARE.
 */

#ifndef HW_STM32F2XX_ADC_H
#define HW_STM32F2XX_ADC_H

#include "hw/sysbus.h"
#include "qom/object.h"

#define ADC_SR    0x00
#define ADC_CR1   0x04
#define ADC_CR2   0x08
#define ADC_SMPR1 0x0C
#define ADC_SMPR2 0x10
#define ADC_JOFR1 0x14
#define ADC_JOFR2 0x18
#define ADC_JOFR3 0x1C
#define ADC_JOFR4 0x20
#define ADC_HTR   0x24
#define ADC_LTR   0x28
#define ADC_SQR1  0x2C
#define ADC_SQR2  0x30
#define ADC_SQR3  0x34
#define ADC_JSQR  0x38
#define ADC_JDR1  0x3C
#define ADC_JDR2  0x40
#define ADC_JDR3  0x44
#define ADC_JDR4  0x48
#define ADC_DR    0x4C

#define ADC_CR2_ADON    0x01
#define ADC_CR2_CONT    0x02
#define ADC_CR2_ALIGN   0x800
#define ADC_CR2_SWSTART 0x40000000

#define ADC_CR1_RES 0x3000000

#define ADC_COMMON_ADDRESS 0x100

#define TYPE_STM32F2XX_ADC "stm32f2xx-adc"
typedef struct STM32F2XXADCState STM32F2XXADCState;
#define STM32F2XX_ADC(obj) \
    OBJECT_CHECK(STM32F2XXADCState, (obj), TYPE_STM32F2XX_ADC)

struct STM32F2XXADCState {
    /* <private> */
    SysBusDevice parent_obj;

    /* <public> */
    MemoryRegion mmio;

    uint32_t adc_sr;
    uint32_t adc_cr1;
    uint32_t adc_cr2;
    uint32_t adc_smpr1;
    uint32_t adc_smpr2;
    uint32_t adc_jofr[4];
    uint32_t adc_htr;
    uint32_t adc_ltr;
    uint32_t adc_sqr1;
    uint32_t adc_sqr2;
    uint32_t adc_sqr3;
    uint32_t adc_jsqr;
    uint32_t adc_jdr[4];
    uint32_t adc_dr;

    qemu_irq irq;
};

#endif /* HW_STM32F2XX_ADC_H */
Commit	Line	Data
d1f711d4 AF	1	/*
	2	* STM32F2XX ADC
	3	*
	4	* Copyright (c) 2014 Alistair Francis <alistair@alistair23.me>
	5	*
	6	* Permission is hereby granted, free of charge, to any person obtaining a copy
	7	* of this software and associated documentation files (the "Software"), to deal
	8	* in the Software without restriction, including without limitation the rights
	9	* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
	10	* copies of the Software, and to permit persons to whom the Software is
	11	* furnished to do so, subject to the following conditions:
	12	*
	13	* The above copyright notice and this permission notice shall be included in
	14	* all copies or substantial portions of the Software.
	15	*
	16	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	17	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	18	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	19	* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
	20	* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
	21	* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
	22	* THE SOFTWARE.
	23	*/
	24
	25	#ifndef HW_STM32F2XX_ADC_H
	26	#define HW_STM32F2XX_ADC_H
	27
ec150c7e	28	#include "hw/sysbus.h"
db1015e9	29	#include "qom/object.h"
ec150c7e	30
d1f711d4 AF	31	#define ADC_SR 0x00
	32	#define ADC_CR1 0x04
	33	#define ADC_CR2 0x08
	34	#define ADC_SMPR1 0x0C
	35	#define ADC_SMPR2 0x10
	36	#define ADC_JOFR1 0x14
	37	#define ADC_JOFR2 0x18
	38	#define ADC_JOFR3 0x1C
	39	#define ADC_JOFR4 0x20
	40	#define ADC_HTR 0x24
	41	#define ADC_LTR 0x28
	42	#define ADC_SQR1 0x2C
	43	#define ADC_SQR2 0x30
	44	#define ADC_SQR3 0x34
	45	#define ADC_JSQR 0x38
	46	#define ADC_JDR1 0x3C
	47	#define ADC_JDR2 0x40
	48	#define ADC_JDR3 0x44
	49	#define ADC_JDR4 0x48
	50	#define ADC_DR 0x4C
	51
	52	#define ADC_CR2_ADON 0x01
	53	#define ADC_CR2_CONT 0x02
	54	#define ADC_CR2_ALIGN 0x800
	55	#define ADC_CR2_SWSTART 0x40000000
	56
	57	#define ADC_CR1_RES 0x3000000
	58
	59	#define ADC_COMMON_ADDRESS 0x100
	60
	61	#define TYPE_STM32F2XX_ADC "stm32f2xx-adc"
db1015e9	62	typedef struct STM32F2XXADCState STM32F2XXADCState;
d1f711d4 AF	63	#define STM32F2XX_ADC(obj) \
	64	OBJECT_CHECK(STM32F2XXADCState, (obj), TYPE_STM32F2XX_ADC)
	65
db1015e9	66	struct STM32F2XXADCState {
d1f711d4 AF	67	/* <private> */
	68	SysBusDevice parent_obj;
	69
	70	/* <public> */
	71	MemoryRegion mmio;
	72
	73	uint32_t adc_sr;
	74	uint32_t adc_cr1;
	75	uint32_t adc_cr2;
	76	uint32_t adc_smpr1;
	77	uint32_t adc_smpr2;
	78	uint32_t adc_jofr[4];
	79	uint32_t adc_htr;
	80	uint32_t adc_ltr;
	81	uint32_t adc_sqr1;
	82	uint32_t adc_sqr2;
	83	uint32_t adc_sqr3;
	84	uint32_t adc_jsqr;
	85	uint32_t adc_jdr[4];
	86	uint32_t adc_dr;
	87
	88	qemu_irq irq;
db1015e9	89	};
d1f711d4 AF	90
d1f711d4 AF	91	#endif /* HW_STM32F2XX_ADC_H */