[thirdparty/qemu.git] / include / hw / i386 / ich9.h

#ifndef HW_ICH9_H
#define HW_ICH9_H

#include "hw/isa/isa.h"
#include "hw/sysbus.h"
#include "hw/i386/pc.h"
#include "hw/isa/apm.h"
#include "hw/i386/ioapic.h"
#include "hw/pci/pci.h"
#include "hw/pci/pcie_host.h"
#include "hw/pci/pci_bridge.h"
#include "hw/acpi/acpi.h"
#include "hw/acpi/ich9.h"
#include "hw/pci/pci_bus.h"

void ich9_lpc_set_irq(void *opaque, int irq_num, int level);
int ich9_lpc_map_irq(PCIDevice *pci_dev, int intx);
PCIINTxRoute ich9_route_intx_pin_to_irq(void *opaque, int pirq_pin);
void ich9_lpc_pm_init(PCIDevice *pci_lpc, bool smm_enabled);
I2CBus *ich9_smb_init(PCIBus *bus, int devfn, uint32_t smb_io_base);

void ich9_generate_smi(void);

#define ICH9_CC_SIZE (16 * 1024) /* 16KB. Chipset configuration registers */

#define TYPE_ICH9_LPC_DEVICE "ICH9-LPC"
#define ICH9_LPC_DEVICE(obj) \
     OBJECT_CHECK(ICH9LPCState, (obj), TYPE_ICH9_LPC_DEVICE)

typedef struct ICH9LPCState {
    /* ICH9 LPC PCI to ISA bridge */
    PCIDevice d;

    /* (pci device, intx) -> pirq
     * In real chipset case, the unused slots are never used
     * as ICH9 supports only D25-D31 irq routing.
     * On the other hand in qemu case, any slot/function can be populated
     * via command line option.
     * So fallback interrupt routing for any devices in any slots is necessary.
    */
    uint8_t irr[PCI_SLOT_MAX][PCI_NUM_PINS];

    APMState apm;
    ICH9LPCPMRegs pm;
    uint32_t sci_level; /* track sci level */
    uint8_t sci_gsi;

    /* 2.24 Pin Straps */
    struct {
        bool spkr_hi;
    } pin_strap;

    /* 10.1 Chipset Configuration registers(Memory Space)
     which is pointed by RCBA */
    uint8_t chip_config[ICH9_CC_SIZE];

    /*
     * 13.7.5 RST_CNT---Reset Control Register (LPC I/F---D31:F0)
     *
     * register contents and IO memory region
     */
    uint8_t rst_cnt;
    MemoryRegion rst_cnt_mem;

    /* SMI feature negotiation via fw_cfg */
    uint64_t smi_host_features;       /* guest-invisible, host endian */
    uint8_t smi_host_features_le[8];  /* guest-visible, read-only, little
                                       * endian uint64_t */
    uint8_t smi_guest_features_le[8]; /* guest-visible, read-write, little
                                       * endian uint64_t */
    uint8_t smi_features_ok;          /* guest-visible, read-only; selecting it
                                       * triggers feature lockdown */
    uint64_t smi_negotiated_features; /* guest-invisible, host endian */

    /* isa bus */
    ISABus *isa_bus;
    MemoryRegion rcrb_mem; /* root complex register block */
    Notifier machine_ready;

    qemu_irq gsi[GSI_NUM_PINS];
} ICH9LPCState;

#define Q35_MASK(bit, ms_bit, ls_bit) \
((uint##bit##_t)(((1ULL << ((ms_bit) + 1)) - 1) & ~((1ULL << ls_bit) - 1)))

/* ICH9: Chipset Configuration Registers */
#define ICH9_CC_ADDR_MASK                       (ICH9_CC_SIZE - 1)

#define ICH9_CC
#define ICH9_CC_D28IP                           0x310C
#define ICH9_CC_D28IP_SHIFT                     4
#define ICH9_CC_D28IP_MASK                      0xf
#define ICH9_CC_D28IP_DEFAULT                   0x00214321
#define ICH9_CC_D31IR                           0x3140
#define ICH9_CC_D30IR                           0x3142
#define ICH9_CC_D29IR                           0x3144
#define ICH9_CC_D28IR                           0x3146
#define ICH9_CC_D27IR                           0x3148
#define ICH9_CC_D26IR                           0x314C
#define ICH9_CC_D25IR                           0x3150
#define ICH9_CC_DIR_DEFAULT                     0x3210
#define ICH9_CC_D30IR_DEFAULT                   0x0
#define ICH9_CC_DIR_SHIFT                       4
#define ICH9_CC_DIR_MASK                        0x7
#define ICH9_CC_OIC                             0x31FF
#define ICH9_CC_OIC_AEN                         0x1
#define ICH9_CC_GCS                             0x3410
#define ICH9_CC_GCS_DEFAULT                     0x00000020
#define ICH9_CC_GCS_NO_REBOOT                   (1 << 5)

/* D28:F[0-5] */
#define ICH9_PCIE_DEV                           28
#define ICH9_PCIE_FUNC_MAX                      6


/* D29:F0 USB UHCI Controller #1 */
#define ICH9_USB_UHCI1_DEV                      29
#define ICH9_USB_UHCI1_FUNC                     0

/* D30:F0 DMI-to-PCI bridge */
#define ICH9_D2P_BRIDGE                         "ICH9 D2P BRIDGE"
#define ICH9_D2P_BRIDGE_SAVEVM_VERSION          0

#define ICH9_D2P_BRIDGE_DEV                     30
#define ICH9_D2P_BRIDGE_FUNC                    0

#define ICH9_D2P_SECONDARY_DEFAULT              (256 - 8)

#define ICH9_D2P_A2_REVISION                    0x92

/* D31:F0 LPC Processor Interface */
#define ICH9_RST_CNT_IOPORT                     0xCF9

/* D31:F1 LPC controller */
#define ICH9_A2_LPC                             "ICH9 A2 LPC"
#define ICH9_A2_LPC_SAVEVM_VERSION              0

#define ICH9_LPC_DEV                            31
#define ICH9_LPC_FUNC                           0

#define ICH9_A2_LPC_REVISION                    0x2
#define ICH9_LPC_NB_PIRQS                       8       /* PCI A-H */

#define ICH9_LPC_PMBASE                         0x40
#define ICH9_LPC_PMBASE_BASE_ADDRESS_MASK       Q35_MASK(32, 15, 7)
#define ICH9_LPC_PMBASE_RTE                     0x1
#define ICH9_LPC_PMBASE_DEFAULT                 0x1
#define ICH9_LPC_ACPI_CTRL                      0x44
#define ICH9_LPC_ACPI_CTRL_ACPI_EN              0x80
#define ICH9_LPC_ACPI_CTRL_SCI_IRQ_SEL_MASK     Q35_MASK(8, 2, 0)
#define ICH9_LPC_ACPI_CTRL_9                    0x0
#define ICH9_LPC_ACPI_CTRL_10                   0x1
#define ICH9_LPC_ACPI_CTRL_11                   0x2
#define ICH9_LPC_ACPI_CTRL_20                   0x4
#define ICH9_LPC_ACPI_CTRL_21                   0x5
#define ICH9_LPC_ACPI_CTRL_DEFAULT              0x0

#define ICH9_LPC_PIRQA_ROUT                     0x60
#define ICH9_LPC_PIRQB_ROUT                     0x61
#define ICH9_LPC_PIRQC_ROUT                     0x62
#define ICH9_LPC_PIRQD_ROUT                     0x63

#define ICH9_LPC_PIRQE_ROUT                     0x68
#define ICH9_LPC_PIRQF_ROUT                     0x69
#define ICH9_LPC_PIRQG_ROUT                     0x6a
#define ICH9_LPC_PIRQH_ROUT                     0x6b

#define ICH9_LPC_PIRQ_ROUT_IRQEN                0x80
#define ICH9_LPC_PIRQ_ROUT_MASK                 Q35_MASK(8, 3, 0)
#define ICH9_LPC_PIRQ_ROUT_DEFAULT              0x80

#define ICH9_LPC_GEN_PMCON_1                    0xa0
#define ICH9_LPC_GEN_PMCON_1_SMI_LOCK           (1 << 4)
#define ICH9_LPC_GEN_PMCON_2                    0xa2
#define ICH9_LPC_GEN_PMCON_3                    0xa4
#define ICH9_LPC_GEN_PMCON_LOCK                 0xa6

#define ICH9_LPC_RCBA                           0xf0
#define ICH9_LPC_RCBA_BA_MASK                   Q35_MASK(32, 31, 14)
#define ICH9_LPC_RCBA_EN                        0x1
#define ICH9_LPC_RCBA_DEFAULT                   0x0

#define ICH9_LPC_PIC_NUM_PINS                   16
#define ICH9_LPC_IOAPIC_NUM_PINS                24

#define ICH9_GPIO_GSI "gsi"

/* D31:F2 SATA Controller #1 */
#define ICH9_SATA1_DEV                          31
#define ICH9_SATA1_FUNC                         2

/* D31:F0 power management I/O registers
   offset from the address ICH9_LPC_PMBASE */

/* ICH9 LPC PM I/O registers are 128 ports and 128-aligned */
#define ICH9_PMIO_SIZE                          128
#define ICH9_PMIO_MASK                          (ICH9_PMIO_SIZE - 1)

#define ICH9_PMIO_PM1_STS                       0x00
#define ICH9_PMIO_PM1_EN                        0x02
#define ICH9_PMIO_PM1_CNT                       0x04
#define ICH9_PMIO_PM1_TMR                       0x08
#define ICH9_PMIO_GPE0_STS                      0x20
#define ICH9_PMIO_GPE0_EN                       0x28
#define ICH9_PMIO_GPE0_LEN                      16
#define ICH9_PMIO_SMI_EN                        0x30
#define ICH9_PMIO_SMI_EN_APMC_EN                (1 << 5)
#define ICH9_PMIO_SMI_EN_TCO_EN                 (1 << 13)
#define ICH9_PMIO_SMI_STS                       0x34
#define ICH9_PMIO_TCO_RLD                       0x60
#define ICH9_PMIO_TCO_LEN                       32

/* FADT ACPI_ENABLE/ACPI_DISABLE */
#define ICH9_APM_ACPI_ENABLE                    0x2
#define ICH9_APM_ACPI_DISABLE                   0x3


/* D31:F3 SMBus controller */
#define TYPE_ICH9_SMB_DEVICE "ICH9 SMB"

#define ICH9_A2_SMB_REVISION                    0x02
#define ICH9_SMB_PI                             0x00

#define ICH9_SMB_SMBMBAR0                       0x10
#define ICH9_SMB_SMBMBAR1                       0x14
#define ICH9_SMB_SMBM_BAR                       0
#define ICH9_SMB_SMBM_SIZE                      (1 << 8)
#define ICH9_SMB_SMB_BASE                       0x20
#define ICH9_SMB_SMB_BASE_BAR                   4
#define ICH9_SMB_SMB_BASE_SIZE                  (1 << 5)
#define ICH9_SMB_HOSTC                          0x40
#define ICH9_SMB_HOSTC_SSRESET                  ((uint8_t)(1 << 3))
#define ICH9_SMB_HOSTC_I2C_EN                   ((uint8_t)(1 << 2))
#define ICH9_SMB_HOSTC_SMB_SMI_EN               ((uint8_t)(1 << 1))
#define ICH9_SMB_HOSTC_HST_EN                   ((uint8_t)(1 << 0))

/* D31:F3 SMBus I/O and memory mapped I/O registers */
#define ICH9_SMB_DEV                            31
#define ICH9_SMB_FUNC                           3

#define ICH9_SMB_HST_STS                        0x00
#define ICH9_SMB_HST_CNT                        0x02
#define ICH9_SMB_HST_CMD                        0x03
#define ICH9_SMB_XMIT_SLVA                      0x04
#define ICH9_SMB_HST_D0                         0x05
#define ICH9_SMB_HST_D1                         0x06
#define ICH9_SMB_HOST_BLOCK_DB                  0x07

/* bit positions used in fw_cfg SMI feature negotiation */
#define ICH9_LPC_SMI_F_BROADCAST_BIT            0

#endif /* HW_ICH9_H */
Commit	Line	Data
e516572f JB	1	#ifndef HW_ICH9_H
	2	#define HW_ICH9_H
	3
0d09e41a	4	#include "hw/isa/isa.h"
83c9f4ca	5	#include "hw/sysbus.h"
0d09e41a PB	6	#include "hw/i386/pc.h"
	7	#include "hw/isa/apm.h"
	8	#include "hw/i386/ioapic.h"
83c9f4ca PB	9	#include "hw/pci/pci.h"
	10	#include "hw/pci/pcie_host.h"
	11	#include "hw/pci/pci_bridge.h"
0d09e41a PB	12	#include "hw/acpi/acpi.h"
0d09e41a PB	13	#include "hw/acpi/ich9.h"
83c9f4ca	14	#include "hw/pci/pci_bus.h"
e516572f JB	15
	16	void ich9_lpc_set_irq(void *opaque, int irq_num, int level);
	17	int ich9_lpc_map_irq(PCIDevice *pci_dev, int intx);
91c3f2f0	18	PCIINTxRoute ich9_route_intx_pin_to_irq(void *opaque, int pirq_pin);
18d6abae	19	void ich9_lpc_pm_init(PCIDevice *pci_lpc, bool smm_enabled);
a5c82852	20	I2CBus ich9_smb_init(PCIBus bus, int devfn, uint32_t smb_io_base);
e516572f	21
92055797	22	void ich9_generate_smi(void);
92055797	23
7335a95a	24	#define ICH9_CC_SIZE (16 * 1024) /* 16KB. Chipset configuration registers */
e516572f	25
292b1634	26	#define TYPE_ICH9_LPC_DEVICE "ICH9-LPC"
e516572f JB	27	#define ICH9_LPC_DEVICE(obj) \
	28	OBJECT_CHECK(ICH9LPCState, (obj), TYPE_ICH9_LPC_DEVICE)
	29
	30	typedef struct ICH9LPCState {
	31	/* ICH9 LPC PCI to ISA bridge */
	32	PCIDevice d;
	33
	34	/* (pci device, intx) -> pirq
	35	* In real chipset case, the unused slots are never used
0668a06b	36	* as ICH9 supports only D25-D31 irq routing.
e516572f JB	37	* On the other hand in qemu case, any slot/function can be populated
	38	* via command line option.
	39	* So fallback interrupt routing for any devices in any slots is necessary.
	40	*/
	41	uint8_t irr[PCI_SLOT_MAX][PCI_NUM_PINS];
	42
	43	APMState apm;
	44	ICH9LPCPMRegs pm;
	45	uint32_t sci_level; /* track sci level */
8f242cb7	46	uint8_t sci_gsi;
e516572f	47
5add35be PA	48	/* 2.24 Pin Straps */
	49	struct {
	50	bool spkr_hi;
	51	} pin_strap;
	52
e516572f JB	53	/* 10.1 Chipset Configuration registers(Memory Space)
	54	which is pointed by RCBA */
	55	uint8_t chip_config[ICH9_CC_SIZE];
0e98b436 LE	56
	57	/*
	58	* 13.7.5 RST_CNT---Reset Control Register (LPC I/F---D31:F0)
	59	*
	60	* register contents and IO memory region
	61	*/
	62	uint8_t rst_cnt;
	63	MemoryRegion rst_cnt_mem;
	64
50de920b LE	65	/* SMI feature negotiation via fw_cfg */
	66	uint64_t smi_host_features; /* guest-invisible, host endian */
	67	uint8_t smi_host_features_le[8]; /* guest-visible, read-only, little
	68	* endian uint64_t */
	69	uint8_t smi_guest_features_le[8]; /* guest-visible, read-write, little
	70	* endian uint64_t */
	71	uint8_t smi_features_ok; /* guest-visible, read-only; selecting it
	72	* triggers feature lockdown */
	73	uint64_t smi_negotiated_features; /* guest-invisible, host endian */
	74
e516572f JB	75	/* isa bus */
e516572f JB	76	ISABus *isa_bus;
7335a95a	77	MemoryRegion rcrb_mem; /* root complex register block */
3f5bc9e8	78	Notifier machine_ready;
e516572f	79
f999c0de	80	qemu_irq gsi[GSI_NUM_PINS];
e516572f JB	81	} ICH9LPCState;
	82
	83	#define Q35_MASK(bit, ms_bit, ls_bit) \
	84	((uint##bit##_t)(((1ULL << ((ms_bit) + 1)) - 1) & ~((1ULL << ls_bit) - 1)))
	85
	86	/* ICH9: Chipset Configuration Registers */
	87	#define ICH9_CC_ADDR_MASK (ICH9_CC_SIZE - 1)
	88
	89	#define ICH9_CC
	90	#define ICH9_CC_D28IP 0x310C
	91	#define ICH9_CC_D28IP_SHIFT 4
	92	#define ICH9_CC_D28IP_MASK 0xf
	93	#define ICH9_CC_D28IP_DEFAULT 0x00214321
	94	#define ICH9_CC_D31IR 0x3140
	95	#define ICH9_CC_D30IR 0x3142
	96	#define ICH9_CC_D29IR 0x3144
	97	#define ICH9_CC_D28IR 0x3146
	98	#define ICH9_CC_D27IR 0x3148
	99	#define ICH9_CC_D26IR 0x314C
	100	#define ICH9_CC_D25IR 0x3150
	101	#define ICH9_CC_DIR_DEFAULT 0x3210
	102	#define ICH9_CC_D30IR_DEFAULT 0x0
	103	#define ICH9_CC_DIR_SHIFT 4
	104	#define ICH9_CC_DIR_MASK 0x7
	105	#define ICH9_CC_OIC 0x31FF
	106	#define ICH9_CC_OIC_AEN 0x1
92055797 PA	107	#define ICH9_CC_GCS 0x3410
	108	#define ICH9_CC_GCS_DEFAULT 0x00000020
	109	#define ICH9_CC_GCS_NO_REBOOT (1 << 5)
e516572f JB	110
	111	/* D28:F[0-5] */
	112	#define ICH9_PCIE_DEV 28
	113	#define ICH9_PCIE_FUNC_MAX 6
	114
	115
	116	/* D29:F0 USB UHCI Controller #1 */
	117	#define ICH9_USB_UHCI1_DEV 29
	118	#define ICH9_USB_UHCI1_FUNC 0
	119
263cf436	120	/* D30:F0 DMI-to-PCI bridge */
e516572f JB	121	#define ICH9_D2P_BRIDGE "ICH9 D2P BRIDGE"
	122	#define ICH9_D2P_BRIDGE_SAVEVM_VERSION 0
	123
	124	#define ICH9_D2P_BRIDGE_DEV 30
	125	#define ICH9_D2P_BRIDGE_FUNC 0
	126
	127	#define ICH9_D2P_SECONDARY_DEFAULT (256 - 8)
	128
	129	#define ICH9_D2P_A2_REVISION 0x92
	130
0e98b436 LE	131	/* D31:F0 LPC Processor Interface */
0e98b436 LE	132	#define ICH9_RST_CNT_IOPORT 0xCF9
e516572f JB	133
	134	/* D31:F1 LPC controller */
	135	#define ICH9_A2_LPC "ICH9 A2 LPC"
	136	#define ICH9_A2_LPC_SAVEVM_VERSION 0
	137
	138	#define ICH9_LPC_DEV 31
	139	#define ICH9_LPC_FUNC 0
	140
	141	#define ICH9_A2_LPC_REVISION 0x2
	142	#define ICH9_LPC_NB_PIRQS 8 /* PCI A-H */
	143
	144	#define ICH9_LPC_PMBASE 0x40
	145	#define ICH9_LPC_PMBASE_BASE_ADDRESS_MASK Q35_MASK(32, 15, 7)
	146	#define ICH9_LPC_PMBASE_RTE 0x1
	147	#define ICH9_LPC_PMBASE_DEFAULT 0x1
	148	#define ICH9_LPC_ACPI_CTRL 0x44
	149	#define ICH9_LPC_ACPI_CTRL_ACPI_EN 0x80
	150	#define ICH9_LPC_ACPI_CTRL_SCI_IRQ_SEL_MASK Q35_MASK(8, 2, 0)
	151	#define ICH9_LPC_ACPI_CTRL_9 0x0
	152	#define ICH9_LPC_ACPI_CTRL_10 0x1
	153	#define ICH9_LPC_ACPI_CTRL_11 0x2
	154	#define ICH9_LPC_ACPI_CTRL_20 0x4
	155	#define ICH9_LPC_ACPI_CTRL_21 0x5
	156	#define ICH9_LPC_ACPI_CTRL_DEFAULT 0x0
	157
	158	#define ICH9_LPC_PIRQA_ROUT 0x60
	159	#define ICH9_LPC_PIRQB_ROUT 0x61
	160	#define ICH9_LPC_PIRQC_ROUT 0x62
	161	#define ICH9_LPC_PIRQD_ROUT 0x63
	162
	163	#define ICH9_LPC_PIRQE_ROUT 0x68
	164	#define ICH9_LPC_PIRQF_ROUT 0x69
	165	#define ICH9_LPC_PIRQG_ROUT 0x6a
	166	#define ICH9_LPC_PIRQH_ROUT 0x6b
	167
	168	#define ICH9_LPC_PIRQ_ROUT_IRQEN 0x80
	169	#define ICH9_LPC_PIRQ_ROUT_MASK Q35_MASK(8, 3, 0)
	170	#define ICH9_LPC_PIRQ_ROUT_DEFAULT 0x80
	171
11e66a15 GH	172	#define ICH9_LPC_GEN_PMCON_1 0xa0
	173	#define ICH9_LPC_GEN_PMCON_1_SMI_LOCK (1 << 4)
	174	#define ICH9_LPC_GEN_PMCON_2 0xa2
	175	#define ICH9_LPC_GEN_PMCON_3 0xa4
	176	#define ICH9_LPC_GEN_PMCON_LOCK 0xa6
	177
e516572f JB	178	#define ICH9_LPC_RCBA 0xf0
	179	#define ICH9_LPC_RCBA_BA_MASK Q35_MASK(32, 31, 14)
	180	#define ICH9_LPC_RCBA_EN 0x1
	181	#define ICH9_LPC_RCBA_DEFAULT 0x0
	182
	183	#define ICH9_LPC_PIC_NUM_PINS 16
	184	#define ICH9_LPC_IOAPIC_NUM_PINS 24
	185
f999c0de EV	186	#define ICH9_GPIO_GSI "gsi"
f999c0de EV	187
e516572f JB	188	/* D31:F2 SATA Controller #1 */
	189	#define ICH9_SATA1_DEV 31
	190	#define ICH9_SATA1_FUNC 2
	191
0668a06b	192	/* D31:F0 power management I/O registers
e516572f JB	193	offset from the address ICH9_LPC_PMBASE */
	194
	195	/* ICH9 LPC PM I/O registers are 128 ports and 128-aligned */
	196	#define ICH9_PMIO_SIZE 128
	197	#define ICH9_PMIO_MASK (ICH9_PMIO_SIZE - 1)
	198
	199	#define ICH9_PMIO_PM1_STS 0x00
	200	#define ICH9_PMIO_PM1_EN 0x02
	201	#define ICH9_PMIO_PM1_CNT 0x04
	202	#define ICH9_PMIO_PM1_TMR 0x08
	203	#define ICH9_PMIO_GPE0_STS 0x20
	204	#define ICH9_PMIO_GPE0_EN 0x28
	205	#define ICH9_PMIO_GPE0_LEN 16
	206	#define ICH9_PMIO_SMI_EN 0x30
	207	#define ICH9_PMIO_SMI_EN_APMC_EN (1 << 5)
92055797	208	#define ICH9_PMIO_SMI_EN_TCO_EN (1 << 13)
e516572f	209	#define ICH9_PMIO_SMI_STS 0x34
92055797 PA	210	#define ICH9_PMIO_TCO_RLD 0x60
92055797 PA	211	#define ICH9_PMIO_TCO_LEN 32
e516572f JB	212
	213	/* FADT ACPI_ENABLE/ACPI_DISABLE */
	214	#define ICH9_APM_ACPI_ENABLE 0x2
	215	#define ICH9_APM_ACPI_DISABLE 0x3
	216
	217
	218	/* D31:F3 SMBus controller */
f2dd8ebd EV	219	#define TYPE_ICH9_SMB_DEVICE "ICH9 SMB"
f2dd8ebd EV	220
e516572f JB	221	#define ICH9_A2_SMB_REVISION 0x02
	222	#define ICH9_SMB_PI 0x00
	223
	224	#define ICH9_SMB_SMBMBAR0 0x10
	225	#define ICH9_SMB_SMBMBAR1 0x14
	226	#define ICH9_SMB_SMBM_BAR 0
	227	#define ICH9_SMB_SMBM_SIZE (1 << 8)
	228	#define ICH9_SMB_SMB_BASE 0x20
	229	#define ICH9_SMB_SMB_BASE_BAR 4
	230	#define ICH9_SMB_SMB_BASE_SIZE (1 << 5)
	231	#define ICH9_SMB_HOSTC 0x40
	232	#define ICH9_SMB_HOSTC_SSRESET ((uint8_t)(1 << 3))
	233	#define ICH9_SMB_HOSTC_I2C_EN ((uint8_t)(1 << 2))
	234	#define ICH9_SMB_HOSTC_SMB_SMI_EN ((uint8_t)(1 << 1))
	235	#define ICH9_SMB_HOSTC_HST_EN ((uint8_t)(1 << 0))
	236
	237	/* D31:F3 SMBus I/O and memory mapped I/O registers */
	238	#define ICH9_SMB_DEV 31
	239	#define ICH9_SMB_FUNC 3
	240
	241	#define ICH9_SMB_HST_STS 0x00
	242	#define ICH9_SMB_HST_CNT 0x02
	243	#define ICH9_SMB_HST_CMD 0x03
	244	#define ICH9_SMB_XMIT_SLVA 0x04
	245	#define ICH9_SMB_HST_D0 0x05
	246	#define ICH9_SMB_HST_D1 0x06
	247	#define ICH9_SMB_HOST_BLOCK_DB 0x07
	248
5ce45c7a LE	249	/* bit positions used in fw_cfg SMI feature negotiation */
	250	#define ICH9_LPC_SMI_F_BROADCAST_BIT 0
	251
e516572f	252	#endif /* HW_ICH9_H */