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1da12ec4
LT
1/*
2 * QEMU emulation of an Intel IOMMU (VT-d)
3 * (DMA Remapping device)
4 *
5 * Copyright (C) 2013 Knut Omang, Oracle <knut.omang@oracle.com>
6 * Copyright (C) 2014 Le Tan, <tamlokveer@gmail.com>
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17
18 * You should have received a copy of the GNU General Public License along
19 * with this program; if not, see <http://www.gnu.org/licenses/>.
20 */
21
22#ifndef INTEL_IOMMU_H
23#define INTEL_IOMMU_H
a27bd6c7 24
1da12ec4 25#include "sysemu/dma.h"
1c7955c4 26#include "hw/i386/x86-iommu.h"
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27#include "hw/i386/ioapic.h"
28#include "hw/pci/msi.h"
8b5ed7df 29#include "hw/sysbus.h"
63b88968 30#include "qemu/iova-tree.h"
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31
32#define TYPE_INTEL_IOMMU_DEVICE "intel-iommu"
33#define INTEL_IOMMU_DEVICE(obj) \
34 OBJECT_CHECK(IntelIOMMUState, (obj), TYPE_INTEL_IOMMU_DEVICE)
35
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36#define TYPE_INTEL_IOMMU_MEMORY_REGION "intel-iommu-iommu-memory-region"
37
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38/* DMAR Hardware Unit Definition address (IOMMU unit) */
39#define Q35_HOST_BRIDGE_IOMMU_ADDR 0xfed90000ULL
40
41#define VTD_PCI_BUS_MAX 256
42#define VTD_PCI_SLOT_MAX 32
43#define VTD_PCI_FUNC_MAX 8
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44#define VTD_PCI_SLOT(devfn) (((devfn) >> 3) & 0x1f)
45#define VTD_PCI_FUNC(devfn) ((devfn) & 0x07)
1e06f131 46#define VTD_SID_TO_BUS(sid) (((sid) >> 8) & 0xff)
d92fa2dc 47#define VTD_SID_TO_DEVFN(sid) ((sid) & 0xff)
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48
49#define DMAR_REG_SIZE 0x230
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50#define VTD_HOST_AW_39BIT 39
51#define VTD_HOST_AW_48BIT 48
52#define VTD_HOST_ADDRESS_WIDTH VTD_HOST_AW_39BIT
53#define VTD_HAW_MASK(aw) ((1ULL << (aw)) - 1)
1da12ec4 54
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55#define DMAR_REPORT_F_INTR (1)
56
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57#define VTD_MSI_ADDR_HI_MASK (0xffffffff00000000ULL)
58#define VTD_MSI_ADDR_HI_SHIFT (32)
59#define VTD_MSI_ADDR_LO_MASK (0x00000000ffffffffULL)
60
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61typedef struct VTDContextEntry VTDContextEntry;
62typedef struct VTDContextCacheEntry VTDContextCacheEntry;
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63typedef struct IntelIOMMUState IntelIOMMUState;
64typedef struct VTDAddressSpace VTDAddressSpace;
b5a280c0 65typedef struct VTDIOTLBEntry VTDIOTLBEntry;
7df953bd 66typedef struct VTDBus VTDBus;
bc38ee10 67typedef union VTD_IR_TableEntry VTD_IR_TableEntry;
1f91acee 68typedef union VTD_IR_MSIAddress VTD_IR_MSIAddress;
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69typedef struct VTDPASIDDirEntry VTDPASIDDirEntry;
70typedef struct VTDPASIDEntry VTDPASIDEntry;
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71
72/* Context-Entry */
73struct VTDContextEntry {
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74 union {
75 struct {
76 uint64_t lo;
77 uint64_t hi;
78 };
79 struct {
80 uint64_t val[4];
81 };
82 };
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83};
84
85struct VTDContextCacheEntry {
86 /* The cache entry is obsolete if
87 * context_cache_gen!=IntelIOMMUState.context_cache_gen
88 */
89 uint32_t context_cache_gen;
90 struct VTDContextEntry context_entry;
91};
92
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93/* PASID Directory Entry */
94struct VTDPASIDDirEntry {
95 uint64_t val;
96};
97
98/* PASID Table Entry */
99struct VTDPASIDEntry {
100 uint64_t val[8];
101};
102
1da12ec4 103struct VTDAddressSpace {
7df953bd 104 PCIBus *bus;
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105 uint8_t devfn;
106 AddressSpace as;
3df9d748 107 IOMMUMemoryRegion iommu;
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108 MemoryRegion root; /* The root container of the device */
109 MemoryRegion nodmar; /* The alias of shared nodmar MR */
651e4cef 110 MemoryRegion iommu_ir; /* Interrupt region: 0xfeeXXXXX */
1da12ec4 111 IntelIOMMUState *iommu_state;
d92fa2dc 112 VTDContextCacheEntry context_cache_entry;
b4a4ba0d 113 QLIST_ENTRY(VTDAddressSpace) next;
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114 /* Superset of notifier flags that this address space has */
115 IOMMUNotifierFlag notifier_flags;
63b88968 116 IOVATree *iova_tree; /* Traces mapped IOVA ranges */
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117};
118
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119struct VTDBus {
120 PCIBus* bus; /* A reference to the bus to provide translation for */
121 VTDAddressSpace *dev_as[0]; /* A table of VTDAddressSpace objects indexed by devfn */
122};
123
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124struct VTDIOTLBEntry {
125 uint64_t gfn;
126 uint16_t domain_id;
127 uint64_t slpte;
d66b969b 128 uint64_t mask;
07f7b733 129 uint8_t access_flags;
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130};
131
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132/* VT-d Source-ID Qualifier types */
133enum {
134 VTD_SQ_FULL = 0x00, /* Full SID verification */
135 VTD_SQ_IGN_3 = 0x01, /* Ignore bit 3 */
136 VTD_SQ_IGN_2_3 = 0x02, /* Ignore bits 2 & 3 */
137 VTD_SQ_IGN_1_3 = 0x03, /* Ignore bits 1-3 */
138 VTD_SQ_MAX,
139};
140
141/* VT-d Source Validation Types */
142enum {
143 VTD_SVT_NONE = 0x00, /* No validation */
144 VTD_SVT_ALL = 0x01, /* Do full validation */
145 VTD_SVT_BUS = 0x02, /* Validate bus range */
146 VTD_SVT_MAX,
147};
148
1f91acee 149/* Interrupt Remapping Table Entry Definition */
bc38ee10 150union VTD_IR_TableEntry {
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151 struct {
152#ifdef HOST_WORDS_BIGENDIAN
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153 uint32_t __reserved_1:8; /* Reserved 1 */
154 uint32_t vector:8; /* Interrupt Vector */
155 uint32_t irte_mode:1; /* IRTE Mode */
156 uint32_t __reserved_0:3; /* Reserved 0 */
157 uint32_t __avail:4; /* Available spaces for software */
158 uint32_t delivery_mode:3; /* Delivery Mode */
159 uint32_t trigger_mode:1; /* Trigger Mode */
160 uint32_t redir_hint:1; /* Redirection Hint */
161 uint32_t dest_mode:1; /* Destination Mode */
162 uint32_t fault_disable:1; /* Fault Processing Disable */
163 uint32_t present:1; /* Whether entry present/available */
164#else
165 uint32_t present:1; /* Whether entry present/available */
166 uint32_t fault_disable:1; /* Fault Processing Disable */
167 uint32_t dest_mode:1; /* Destination Mode */
168 uint32_t redir_hint:1; /* Redirection Hint */
169 uint32_t trigger_mode:1; /* Trigger Mode */
170 uint32_t delivery_mode:3; /* Delivery Mode */
171 uint32_t __avail:4; /* Available spaces for software */
172 uint32_t __reserved_0:3; /* Reserved 0 */
173 uint32_t irte_mode:1; /* IRTE Mode */
174 uint32_t vector:8; /* Interrupt Vector */
175 uint32_t __reserved_1:8; /* Reserved 1 */
1f91acee 176#endif
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177 uint32_t dest_id; /* Destination ID */
178 uint16_t source_id; /* Source-ID */
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179#ifdef HOST_WORDS_BIGENDIAN
180 uint64_t __reserved_2:44; /* Reserved 2 */
181 uint64_t sid_vtype:2; /* Source-ID Validation Type */
182 uint64_t sid_q:2; /* Source-ID Qualifier */
183#else
184 uint64_t sid_q:2; /* Source-ID Qualifier */
185 uint64_t sid_vtype:2; /* Source-ID Validation Type */
186 uint64_t __reserved_2:44; /* Reserved 2 */
187#endif
bc38ee10 188 } QEMU_PACKED irte;
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189 uint64_t data[2];
190};
191
192#define VTD_IR_INT_FORMAT_COMPAT (0) /* Compatible Interrupt */
193#define VTD_IR_INT_FORMAT_REMAP (1) /* Remappable Interrupt */
194
195/* Programming format for MSI/MSI-X addresses */
196union VTD_IR_MSIAddress {
197 struct {
198#ifdef HOST_WORDS_BIGENDIAN
199 uint32_t __head:12; /* Should always be: 0x0fee */
200 uint32_t index_l:15; /* Interrupt index bit 14-0 */
201 uint32_t int_mode:1; /* Interrupt format */
202 uint32_t sub_valid:1; /* SHV: Sub-Handle Valid bit */
203 uint32_t index_h:1; /* Interrupt index bit 15 */
204 uint32_t __not_care:2;
205#else
206 uint32_t __not_care:2;
207 uint32_t index_h:1; /* Interrupt index bit 15 */
208 uint32_t sub_valid:1; /* SHV: Sub-Handle Valid bit */
209 uint32_t int_mode:1; /* Interrupt format */
210 uint32_t index_l:15; /* Interrupt index bit 14-0 */
211 uint32_t __head:12; /* Should always be: 0x0fee */
212#endif
bc38ee10 213 } QEMU_PACKED addr;
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214 uint32_t data;
215};
216
217/* When IR is enabled, all MSI/MSI-X data bits should be zero */
218#define VTD_IR_MSI_DATA (0)
219
1da12ec4
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220/* The iommu (DMAR) device state struct */
221struct IntelIOMMUState {
1c7955c4 222 X86IOMMUState x86_iommu;
1da12ec4 223 MemoryRegion csrmem;
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224 MemoryRegion mr_nodmar;
225 MemoryRegion mr_ir;
226 MemoryRegion mr_sys_alias;
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227 uint8_t csr[DMAR_REG_SIZE]; /* register values */
228 uint8_t wmask[DMAR_REG_SIZE]; /* R/W bytes */
229 uint8_t w1cmask[DMAR_REG_SIZE]; /* RW1C(Write 1 to Clear) bytes */
230 uint8_t womask[DMAR_REG_SIZE]; /* WO (write only - read returns 0) */
231 uint32_t version;
232
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233 bool caching_mode; /* RO - is cap CM enabled? */
234 bool scalable_mode; /* RO - is Scalable Mode supported? */
3b40f0e5 235
1da12ec4 236 dma_addr_t root; /* Current root table pointer */
fb43cf73 237 bool root_scalable; /* Type of root table (scalable or not) */
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238 bool dmar_enabled; /* Set if DMA remapping is enabled */
239
240 uint16_t iq_head; /* Current invalidation queue head */
241 uint16_t iq_tail; /* Current invalidation queue tail */
242 dma_addr_t iq; /* Current invalidation queue pointer */
243 uint16_t iq_size; /* IQ Size in number of entries */
c0c1d351 244 bool iq_dw; /* IQ descriptor width 256bit or not */
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245 bool qi_enabled; /* Set if the QI is enabled */
246 uint8_t iq_last_desc_type; /* The type of last completed descriptor */
247
248 /* The index of the Fault Recording Register to be used next.
249 * Wraps around from N-1 to 0, where N is the number of FRCD_REG.
250 */
251 uint16_t next_frcd_reg;
252
253 uint64_t cap; /* The value of capability reg */
254 uint64_t ecap; /* The value of extended capability reg */
255
d92fa2dc 256 uint32_t context_cache_gen; /* Should be in [1,MAX] */
b5a280c0 257 GHashTable *iotlb; /* IOTLB */
d92fa2dc 258
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259 GHashTable *vtd_as_by_busptr; /* VTDBus objects indexed by PCIBus* reference */
260 VTDBus *vtd_as_by_bus_num[VTD_PCI_BUS_MAX]; /* VTDBus objects indexed by bus number */
dd4d607e 261 /* list of registered notifiers */
b4a4ba0d 262 QLIST_HEAD(, VTDAddressSpace) vtd_as_with_notifiers;
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263
264 /* interrupt remapping */
265 bool intr_enabled; /* Whether guest enabled IR */
266 dma_addr_t intr_root; /* Interrupt remapping table pointer */
267 uint32_t intr_size; /* Number of IR table entries */
28589311 268 bool intr_eime; /* Extended interrupt mode enabled */
e6b6af05 269 OnOffAuto intr_eim; /* Toggle for EIM cabability */
fb506e70 270 bool buggy_eim; /* Force buggy EIM unless eim=off */
37f51384 271 uint8_t aw_bits; /* Host/IOVA address width (in bits) */
ccc23bb0 272 bool dma_drain; /* Whether DMA r/w draining enabled */
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273
274 /*
275 * Protects IOMMU states in general. Currently it protects the
276 * per-IOMMU IOTLB cache, and context entry cache in VTDAddressSpace.
277 */
278 QemuMutex iommu_lock;
1da12ec4
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279};
280
7df953bd
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281/* Find the VTD Address space associated with the given bus pointer,
282 * create a new one if none exists
283 */
284VTDAddressSpace *vtd_find_add_as(IntelIOMMUState *s, PCIBus *bus, int devfn);
285
1da12ec4 286#endif