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2a6a4076 MA |
1 | #ifndef OPENPIC_H |
2 | #define OPENPIC_H | |
b7169916 | 3 | |
f7bd7941 | 4 | #include "hw/sysbus.h" |
2e5b09fd | 5 | #include "hw/core/cpu.h" |
db1015e9 | 6 | #include "qom/object.h" |
8935a442 | 7 | |
f7bd7941 MCA |
8 | #define MAX_CPU 32 |
9 | #define MAX_MSI 8 | |
10 | #define VID 0x03 /* MPIC version ID */ | |
e1766344 | 11 | |
b7169916 AJ |
12 | /* OpenPIC have 5 outputs per CPU connected and one IRQ out single output */ |
13 | enum { | |
14 | OPENPIC_OUTPUT_INT = 0, /* IRQ */ | |
15 | OPENPIC_OUTPUT_CINT, /* critical IRQ */ | |
16 | OPENPIC_OUTPUT_MCK, /* Machine check event */ | |
17 | OPENPIC_OUTPUT_DEBUG, /* Inconditional debug event */ | |
18 | OPENPIC_OUTPUT_RESET, /* Core reset event */ | |
19 | OPENPIC_OUTPUT_NB, | |
20 | }; | |
21 | ||
9929301e GK |
22 | typedef struct IrqLines { qemu_irq irq[OPENPIC_OUTPUT_NB]; } IrqLines; |
23 | ||
d0b72631 AG |
24 | #define OPENPIC_MODEL_RAVEN 0 |
25 | #define OPENPIC_MODEL_FSL_MPIC_20 1 | |
e0dfe5b1 | 26 | #define OPENPIC_MODEL_FSL_MPIC_42 2 |
58b62835 | 27 | #define OPENPIC_MODEL_KEYLARGO 3 |
5861a338 | 28 | |
8935a442 SW |
29 | #define OPENPIC_MAX_SRC 256 |
30 | #define OPENPIC_MAX_TMR 4 | |
31 | #define OPENPIC_MAX_IPI 4 | |
32 | #define OPENPIC_MAX_IRQ (OPENPIC_MAX_SRC + OPENPIC_MAX_IPI + \ | |
33 | OPENPIC_MAX_TMR) | |
34 | ||
f7bd7941 MCA |
35 | /* Raven */ |
36 | #define RAVEN_MAX_CPU 2 | |
37 | #define RAVEN_MAX_EXT 48 | |
38 | #define RAVEN_MAX_IRQ 64 | |
39 | #define RAVEN_MAX_TMR OPENPIC_MAX_TMR | |
40 | #define RAVEN_MAX_IPI OPENPIC_MAX_IPI | |
41 | ||
42 | /* KeyLargo */ | |
43 | #define KEYLARGO_MAX_CPU 4 | |
44 | #define KEYLARGO_MAX_EXT 64 | |
45 | #define KEYLARGO_MAX_IPI 4 | |
46 | #define KEYLARGO_MAX_IRQ (64 + KEYLARGO_MAX_IPI) | |
47 | #define KEYLARGO_MAX_TMR 0 | |
48 | #define KEYLARGO_IPI_IRQ (KEYLARGO_MAX_EXT) /* First IPI IRQ */ | |
49 | /* Timers don't exist but this makes the code happy... */ | |
50 | #define KEYLARGO_TMR_IRQ (KEYLARGO_IPI_IRQ + KEYLARGO_MAX_IPI) | |
51 | ||
52 | /* Interrupt definitions */ | |
53 | #define RAVEN_FE_IRQ (RAVEN_MAX_EXT) /* Internal functional IRQ */ | |
54 | #define RAVEN_ERR_IRQ (RAVEN_MAX_EXT + 1) /* Error IRQ */ | |
55 | #define RAVEN_TMR_IRQ (RAVEN_MAX_EXT + 2) /* First timer IRQ */ | |
56 | #define RAVEN_IPI_IRQ (RAVEN_TMR_IRQ + RAVEN_MAX_TMR) /* First IPI IRQ */ | |
57 | /* First doorbell IRQ */ | |
58 | #define RAVEN_DBL_IRQ (RAVEN_IPI_IRQ + (RAVEN_MAX_CPU * RAVEN_MAX_IPI)) | |
59 | ||
60 | typedef struct FslMpicInfo { | |
61 | int max_ext; | |
62 | } FslMpicInfo; | |
63 | ||
64 | typedef enum IRQType { | |
65 | IRQ_TYPE_NORMAL = 0, | |
66 | IRQ_TYPE_FSLINT, /* FSL internal interrupt -- level only */ | |
67 | IRQ_TYPE_FSLSPECIAL, /* FSL timer/IPI interrupt, edge, no polarity */ | |
68 | } IRQType; | |
69 | ||
70 | /* Round up to the nearest 64 IRQs so that the queue length | |
71 | * won't change when moving between 32 and 64 bit hosts. | |
72 | */ | |
73 | #define IRQQUEUE_SIZE_BITS ((OPENPIC_MAX_IRQ + 63) & ~63) | |
74 | ||
75 | typedef struct IRQQueue { | |
76 | unsigned long *queue; | |
77 | int32_t queue_size; /* Only used for VMSTATE_BITMAP */ | |
78 | int next; | |
79 | int priority; | |
80 | } IRQQueue; | |
81 | ||
82 | typedef struct IRQSource { | |
83 | uint32_t ivpr; /* IRQ vector/priority register */ | |
84 | uint32_t idr; /* IRQ destination register */ | |
85 | uint32_t destmask; /* bitmap of CPU destinations */ | |
86 | int last_cpu; | |
87 | int output; /* IRQ level, e.g. OPENPIC_OUTPUT_INT */ | |
88 | int pending; /* TRUE if IRQ is pending */ | |
89 | IRQType type; | |
90 | bool level:1; /* level-triggered */ | |
91 | bool nomask:1; /* critical interrupts ignore mask on some FSL MPICs */ | |
92 | } IRQSource; | |
93 | ||
94 | #define IVPR_MASK_SHIFT 31 | |
95 | #define IVPR_MASK_MASK (1U << IVPR_MASK_SHIFT) | |
96 | #define IVPR_ACTIVITY_SHIFT 30 | |
97 | #define IVPR_ACTIVITY_MASK (1U << IVPR_ACTIVITY_SHIFT) | |
98 | #define IVPR_MODE_SHIFT 29 | |
99 | #define IVPR_MODE_MASK (1U << IVPR_MODE_SHIFT) | |
100 | #define IVPR_POLARITY_SHIFT 23 | |
101 | #define IVPR_POLARITY_MASK (1U << IVPR_POLARITY_SHIFT) | |
102 | #define IVPR_SENSE_SHIFT 22 | |
103 | #define IVPR_SENSE_MASK (1U << IVPR_SENSE_SHIFT) | |
104 | ||
105 | #define IVPR_PRIORITY_MASK (0xFU << 16) | |
106 | #define IVPR_PRIORITY(_ivprr_) ((int)(((_ivprr_) & IVPR_PRIORITY_MASK) >> 16)) | |
107 | #define IVPR_VECTOR(opp, _ivprr_) ((_ivprr_) & (opp)->vector_mask) | |
108 | ||
109 | /* IDR[EP/CI] are only for FSL MPIC prior to v4.0 */ | |
110 | #define IDR_EP 0x80000000 /* external pin */ | |
111 | #define IDR_CI 0x40000000 /* critical interrupt */ | |
112 | ||
113 | typedef struct OpenPICTimer { | |
114 | uint32_t tccr; /* Global timer current count register */ | |
115 | uint32_t tbcr; /* Global timer base count register */ | |
116 | int n_IRQ; | |
117 | bool qemu_timer_active; /* Is the qemu_timer is running? */ | |
118 | struct QEMUTimer *qemu_timer; | |
119 | struct OpenPICState *opp; /* Device timer is part of. */ | |
120 | /* The QEMU_CLOCK_VIRTUAL time (in ns) corresponding to the last | |
121 | current_count written or read, only defined if qemu_timer_active. */ | |
122 | uint64_t origin_time; | |
123 | } OpenPICTimer; | |
124 | ||
125 | typedef struct OpenPICMSI { | |
126 | uint32_t msir; /* Shared Message Signaled Interrupt Register */ | |
127 | } OpenPICMSI; | |
128 | ||
129 | typedef struct IRQDest { | |
130 | int32_t ctpr; /* CPU current task priority */ | |
131 | IRQQueue raised; | |
132 | IRQQueue servicing; | |
133 | qemu_irq *irqs; | |
134 | ||
135 | /* Count of IRQ sources asserting on non-INT outputs */ | |
136 | uint32_t outputs_active[OPENPIC_OUTPUT_NB]; | |
137 | } IRQDest; | |
138 | ||
139 | #define TYPE_OPENPIC "openpic" | |
8063396b | 140 | OBJECT_DECLARE_SIMPLE_TYPE(OpenPICState, OPENPIC) |
f7bd7941 | 141 | |
db1015e9 | 142 | struct OpenPICState { |
f7bd7941 MCA |
143 | /*< private >*/ |
144 | SysBusDevice parent_obj; | |
145 | /*< public >*/ | |
146 | ||
147 | MemoryRegion mem; | |
148 | ||
149 | /* Behavior control */ | |
150 | FslMpicInfo *fsl; | |
151 | uint32_t model; | |
152 | uint32_t flags; | |
153 | uint32_t nb_irqs; | |
154 | uint32_t vid; | |
155 | uint32_t vir; /* Vendor identification register */ | |
156 | uint32_t vector_mask; | |
157 | uint32_t tfrr_reset; | |
158 | uint32_t ivpr_reset; | |
159 | uint32_t idr_reset; | |
160 | uint32_t brr1; | |
161 | uint32_t mpic_mode_mask; | |
162 | ||
163 | /* Sub-regions */ | |
164 | MemoryRegion sub_io_mem[6]; | |
165 | ||
166 | /* Global registers */ | |
167 | uint32_t frr; /* Feature reporting register */ | |
168 | uint32_t gcr; /* Global configuration register */ | |
169 | uint32_t pir; /* Processor initialization register */ | |
170 | uint32_t spve; /* Spurious vector register */ | |
171 | uint32_t tfrr; /* Timer frequency reporting register */ | |
172 | /* Source registers */ | |
173 | IRQSource src[OPENPIC_MAX_IRQ]; | |
174 | /* Local registers per output pin */ | |
175 | IRQDest dst[MAX_CPU]; | |
176 | uint32_t nb_cpus; | |
177 | /* Timer registers */ | |
178 | OpenPICTimer timers[OPENPIC_MAX_TMR]; | |
179 | uint32_t max_tmr; | |
180 | ||
181 | /* Shared MSI registers */ | |
182 | OpenPICMSI msi[MAX_MSI]; | |
183 | uint32_t max_irq; | |
184 | uint32_t irq_ipi0; | |
185 | uint32_t irq_tim0; | |
186 | uint32_t irq_msi; | |
db1015e9 | 187 | }; |
f7bd7941 | 188 | |
2a6a4076 | 189 | #endif /* OPENPIC_H */ |